CN103474340A - Method for releasing Fermi level pining by utilizing double-layer insulating layer - Google Patents
Method for releasing Fermi level pining by utilizing double-layer insulating layer Download PDFInfo
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- CN103474340A CN103474340A CN2013104491008A CN201310449100A CN103474340A CN 103474340 A CN103474340 A CN 103474340A CN 2013104491008 A CN2013104491008 A CN 2013104491008A CN 201310449100 A CN201310449100 A CN 201310449100A CN 103474340 A CN103474340 A CN 103474340A
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Abstract
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method for releasing Fermi level pining produced when metal is in contact with a semiconductor by utilizing a double-layer insulating layer. One ultra-thin double-layer insulating layer is inserted between the metal and the semiconductor, and a high schottky barrier formed by the Fermi level pining produced when the metal is in contact with the semiconductor is lowered by an electric dipole formed between the insulating layer and the semiconductor and an electric dipole formed between two insulating layer bodies in a pulling mode. The method is simple and effective, the Fermi level pining can be effectively released, the schottky barrier is lowered, the contact resistance between the metal and the semiconductor is reduced, and ohmic contact is achieved.
Description
Technical field
The invention belongs to the semiconductor integrated circuit technical field, be specifically related to a kind of method of releasing Fermi level pinning.
Background technology
Development along with the large scale integrated circuit technology, semiconductor device is just towards the future development of miniaturization, high speed, high integration and low energy consumption, attain ripe amorphous silicon film transistor technique and appeared gradually its limitation, be mainly reflected in that mobility is low, opacity and band gap little, this has restricted speed, the aperture opening ratio of device.Zinc oxide is the II-V family N-shaped transparent semiconductor material of a kind of broad-band gap (3.37eV), there are high-melting-point, high exciton bind energy and exciton gain, the advantages such as epitaxial growth temperature is low, cost is low, easy etching, so the Thin Film Transistor (TFT) of Zinc oxide-base (TFT) is considered to replace the metal-oxide semiconductor fieldeffect transistor of future generation of the amorphous silicon membrane field-effect transistor of current extensive industrialization.
The source of Thin Film Transistor (TFT), drain electrode material requirements resistivity be low, with semi-conductive the contact, be that the Schottky barrier at ohmic contact and interface is little.In theory, for N-shaped zinc-oxide film field-effect transistor, should select the metal of low work function as source-drain electrode, as metal materials such as aluminium, silver, titaniums.P-type zinc-oxide film field-effect transistor should select metal that work function is high as source-drain electrode, as metal materials such as gold, lead, nickel, platinum.Yet, in fact, metal is difficult to do the trick while contacting with zinc oxide, this is to have caused the lax of charge density because total interface energy on metal and semi-conductive contact-making surface minimizes, produced an interface dipole, make the Fermi level of metal be pinned at higher position, in this case, the effective work function of metal has departed from its numerical value in a vacuum, cause actual Schottky barrier bigger than normal, and use the metal material of different work functions little on the adjusting impact of schottky barrier height.
At present, the source of acquisition N-shaped zinc-oxide film field-effect transistor, the method for leakage ohmic contact are mainly by short annealing and surface treatment, at semiconductor surface, produce a large amount of alms giver's defects, make Fermi level move at the bottom of conduction band, charge carrier is easy to tunnelling, thus the contact obtained.The problem that the method exists is when annealing temperature higher (600 ℃), due to metal and the variation of N-shaped Zinc Oxide Interface reacting phase, phase counterdiffusion between metal and the factors such as decomposition of zinc oxide, makes surface become coarse, causes the contact resistance increase.
Summary of the invention
In view of this, the object of the invention is to propose a kind of method of fermi level pinning when discharging metal and contacting with semiconductor, to reduce schottky barrier height, improve the performance of thin-film transistor.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of method of fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor, concrete steps are:
The first ultra-thin insulating barrier of growth one on semiconductor layer;
Ultra-thin the second insulating barrier that is different from the first insulating barrier of growth one on described the first insulating barrier;
Deposit top electrode on described the second insulating barrier.
In the present invention, described semiconductor layer material is zinc oxide.
The method of fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor as above, described top electrode can or be titanium for aluminium, platinum, palladium, gold, nickel, lead, silver.
In the present invention, described the first insulating barrier and the second insulating layer material can or be zirconia for aluminium oxide, hafnium oxide, titanium oxide; The thickness range of the double hyer insulation layer that the first insulating barrier and the second insulating barrier form is the 1-3 nanometer.
The present invention inserts a ultra-thin double hyer insulation layer between metal and semiconductor, utilize the electric dipole formed between the electric dipole that forms between insulating barrier and semiconductor and dielectric layers to drag down the formed high schottky barrier height of fermi level pinning while contacting with semiconductor due to metal, method is simply effective, and releasing Fermi level pinning effectively, reduce schottky barrier height, reduce metal and semi-conductive contact resistance, realize ohmic contact.
The accompanying drawing explanation
Fig. 1 is the sectional view of an embodiment of fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor proposed by the invention.
Fig. 2 is energy band diagram when after insertion double hyer insulation layer, metal contacts with semiconductor.Wherein, the energy band diagram while (a) directly contacting with semiconductor for metal, (b) be the energy band diagram after between metal and semiconductor, inserting the double hyer insulation layer.
Fig. 3-Fig. 7 is the process chart of an embodiment of the method for fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor proposed by the invention.
Number in the figure: 101 is zinc oxide semiconductor layer, and 102 is the first insulating barrier, and 103 is the second insulating barrier, and 104 is metal level.
Embodiment
With embodiment, the present invention is further detailed explanation by reference to the accompanying drawings for face.In the drawings, for convenience of description, zoomed in or out the layer and regional thickness, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, they or complete reflection zone and form the mutual alignment between structure, particularly form the upper and lower and neighbouring relations between structure.
Fig. 1 is the sectional view of an embodiment of fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor proposed by the invention, as Fig. 1, shown in 101 be zinc oxide semiconductor layer, shown in 102 be the first insulating barrier, shown in 103 be the second insulating barrier, described 104 is metal level.The first insulating barrier 102 is different with the material of the second insulating barrier 103, and can or be all the high dielectric constant materials such as zirconia for aluminium oxide, hafnium oxide, titanium oxide, the thickness range of the double hyer insulation layer simultaneously, consisted of the first insulating barrier 102 and the second insulating barrier 103 is preferably the 1-3 nanometer.Metal level 104 can or be the metal materials such as titanium for aluminium, platinum, palladium, gold, nickel, lead, silver.
Fig. 2 is the energy band diagram of metal while contacting with semiconductor, and wherein, the energy band diagram while (a) directly contacting with semiconductor for metal, (b) be the energy band diagram after insertion double hyer insulation layer between metal and semiconductor.When metal directly contacts with semiconductor, because minimizing, total interface energy on metal and semi-conductive contact-making surface caused the lax of charge density, produced an interface dipole, make the Fermi level of metal be pinned at higher position, the effective work function of metal has departed from its numerical value in a vacuum, causes actual Schottky barrier (Φ b.eff) bigger than normal.After inserting a ultra-thin double hyer insulation layer (such as being aluminium oxide and hafnium oxide) between metal and semiconductor, at the positive electric dipole formed between insulating barrier and semiconductor and between dielectric layers, electric dipole can drag down schottky barrier height, thereby reduces schottky barrier height, realize ohmic contact.
Fig. 3-Fig. 7 is the process chart of an embodiment of the method for fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor proposed by the invention.
At first, as shown in Figure 3, the Semiconductor substrate 200 provided is carried out to the cleaning of standard chemical cleaning, cleaner by rinsed with deionized water, then with High Purity Nitrogen, it is dried up.Then, deposition hearth electrode 201 on substrate 200.
Take at PET substrate and IT0 hearth electrode is example, and the substrate that has deposited the IT0 hearth electrode is put into to the acetone ultrasonic cleaning 5 minutes, then with deionized water, substrate is rinsed well, then with High Purity Nitrogen, it is dried up.
Next, depositing zinc oxide semiconductor layer 202 on hearth electrode 201, as shown in Figure 4.
The manufacture method of zinc oxide semiconductor layer can adopt molecular beam epitaxy, magnetron sputtering technique, metal-organic chemical vapor deposition equipment, pulsed laser deposition, spraying thermal decomposition, sol-gel process and atomic layer deposition etc., and the method is all that industry is known.The employing atomic layer deposition zinc oxide of take is example, with diethyl zinc (DEZn) and water (H
2o) be precursors, reaction temperature is 200 ℃, and reaction chamber air pressure is 5 holders.Comprise single reaction time the gas of liquid diethyl zinc volatilization is passed into to reaction chamber, the reaction time is 500ms, then the nitrogen that passes into 2s is removed unreacted metal organic precursor body and accessory substance; Steam is passed into to reaction chamber, and the reaction time is 500ms, then the nitrogen that passes into 2s is removed unreacted steam and accessory substance.Reaction is carried out 250 cycles, obtains the approximately zinc-oxide film of 54 nanometer thickness.Adopt uniformity of film and the favorable repeatability of the growth of atomic layer deposition technique, and can very accurately control by the periodicity that changes deposit the thickness of film.
Next, growth the first insulating barrier 203 on zinc oxide semiconductor layer 202, as shown in Figure 5.
The material of the first insulating barrier can be the high dielectric constant materials such as aluminium oxide, hafnium oxide, titanium oxide, zirconia.The embodiment of the present invention take that to adopt the atomic layer deposition aluminium oxide be example.With trimethyl aluminium (TMA) and H
2o is precursors, and reaction temperature is 200 ℃, and reaction chamber air pressure is 5 holders.Comprise single reaction time the gas of liquid trimethyl aluminium volatilization is passed into to reaction chamber, the reaction time is 100ms, then the nitrogen that passes into 1s is removed unreacted metal organic precursor body and accessory substance; Steam is passed into to reaction chamber, and the reaction time is 100ms, then the nitrogen that passes into 1s is removed unreacted steam and accessory substance.Reaction is carried out 10 cycles, obtains the approximately aluminum oxide film of 1.3 nanometer thickness.
Next, growth the second insulating barrier 204 on the first insulating barrier 203, as shown in Figure 6.
The material of the second insulating barrier 204 can be the high dielectric constant materials such as aluminium oxide, hafnium oxide, titanium oxide, zirconia, but should be different from the material of the first insulating barrier 203.The embodiment of the present invention be take the atomic layer deposition hafnium oxide as example.With tetraethyl methylamino hafnium (TEMAH) and H
2o is precursors, before reaction, first the atomic layer deposition reactions chamber is heated to 300 ℃, and presoma TEMAH is heated to 70 ℃, and keeps temperature-resistant in whole growth course, and reaction chamber air pressure is 5 holders.Comprise that the gas that the organic substance precursors TEMAH of the hafnium of heating is volatilized usings nitrogen and circulate into reaction chamber as vector gas single reaction time, the reaction time is 1s, then the nitrogen that passes into 3s is removed unreacted metal organic precursor body and accessory substance; Steam is passed into to reaction chamber, and the reaction time is 300ms, the nitrogen of more logical 2s is removed unreacted steam and accessory substance.Reaction is carried out 10 cycles, obtains the hafnia film of about 0.8 nanometer thickness.
The thickness of the double hyer insulation layer consisted of the first insulating barrier 203 and the second insulating barrier 204 should be preferably between the 1-3 nanometer.
Next, the long-pending top electrode 205 of deposition on the second insulating barrier 204, as shown in Figure 7.Top electrode 205 can or be the metal materials such as titanium for aluminium, platinum, palladium, gold, nickel, lead, silver, and its preparation method can adopt the techniques such as evaporation, sputter.Take and select that directly to contact with zinc oxide the argent that has the pinning phenomenon be example as top electrode, adopt physical vapour deposition (PVD) (PVD) depositing technics, under the power power-supply of the chamber pressure of 1 handkerchief, 150w, deposition is 5 minutes, can obtain the approximately silver-colored film of 200 nanometer thickness.
As mentioned above, in the situation that do not depart from spirit and scope of the invention, can also form many embodiment that very big difference is arranged.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in specification.
Claims (4)
1. the method for a fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor, is characterized in that, concrete steps are:
The first ultra-thin insulating barrier of growth one on semiconductor layer;
Ultra-thin the second insulating barrier that is different from the first insulating barrier of growth one on described the first insulating barrier;
Deposit top electrode on described the second insulating barrier.
2. the method for fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor as claimed in claim 1, is characterized in that, described semiconductor layer is zinc oxide.
3. the method for fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor as claimed in claim 1, is characterized in that, described top electrode is a kind of in aluminium, platinum, palladium, gold, nickel, lead, silver, titanium.
4. the method for fermi level pinning while utilizing the double hyer insulation layer to discharge metal to contact with semiconductor as claimed in claim 1, it is characterized in that, described the first insulating barrier and the second insulating layer material be aluminium oxide, hafnium oxide, titanium oxide or be zirconia, and the thickness range of the double hyer insulation layer that the first insulating barrier and the second insulating barrier form is the 1-3 nanometer.
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| CN101325158A (en) * | 2007-06-15 | 2008-12-17 | 东部高科股份有限公司 | Semiconductor device and method of forming gate thereof |
| CN101609843A (en) * | 2008-06-18 | 2009-12-23 | 三星移动显示器株式会社 | Thin-film transistor, its manufacture method and have the flat panel display equipment of thin-film transistor |
| CN101866953A (en) * | 2010-05-26 | 2010-10-20 | 清华大学 | Low Schottky barrier semiconductor structure and formation method thereof |
| CN102222687A (en) * | 2011-06-23 | 2011-10-19 | 北京大学 | Germanium-based NMOS (N-metal-oxide-semiconductor) device and preparation method thereof |
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- 2013-09-28 CN CN2013104491008A patent/CN103474340A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1697181A (en) * | 2004-05-14 | 2005-11-16 | 国际商业机器公司 | Mutual compensating metals-oxides-semiconductor structure and its mfg. method |
| JP2007081211A (en) * | 2005-09-15 | 2007-03-29 | Fujitsu Ltd | Insulated gate semiconductor device and method of manufacturing same |
| CN101325158A (en) * | 2007-06-15 | 2008-12-17 | 东部高科股份有限公司 | Semiconductor device and method of forming gate thereof |
| CN101609843A (en) * | 2008-06-18 | 2009-12-23 | 三星移动显示器株式会社 | Thin-film transistor, its manufacture method and have the flat panel display equipment of thin-film transistor |
| CN101866953A (en) * | 2010-05-26 | 2010-10-20 | 清华大学 | Low Schottky barrier semiconductor structure and formation method thereof |
| CN102222687A (en) * | 2011-06-23 | 2011-10-19 | 北京大学 | Germanium-based NMOS (N-metal-oxide-semiconductor) device and preparation method thereof |
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Application publication date: 20131225 |