CN103460361A - 在切割胶带上施加有底部填料膜的预切割的晶片 - Google Patents

在切割胶带上施加有底部填料膜的预切割的晶片 Download PDF

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CN103460361A
CN103460361A CN2012800074663A CN201280007466A CN103460361A CN 103460361 A CN103460361 A CN 103460361A CN 2012800074663 A CN2012800074663 A CN 2012800074663A CN 201280007466 A CN201280007466 A CN 201280007466A CN 103460361 A CN103460361 A CN 103460361A
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bottom filling
wafer
semiconductor wafer
dicing tape
semiconductor
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CN103460361B (zh
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G·黄
Y·金
R·吉诺
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Henkel AG and Co KGaA
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Abstract

本发明提供一种制造具有预先施加的底部填料的半导体的方法，包括：(a)提供在有源面上具有多个金属凸块的减薄的硅半导体晶片，任选地，硅通孔垂直穿过所述硅半导体晶片；(b)在切割支撑胶带上提供底部填料，其中所述底部填料被预先切割为所述半导体晶片的形状；(c)将所述切割支撑胶带上的底部填料与所述半导体晶片对齐布置，并将所述底部填料层合至所述半导体晶片。

Description

在切割胶带上施加有底部填料膜的预切割的晶片
相关申请的交叉引用
本申请要求2011年2月1日提交的美国临时专利申请NO.61／438,341的优先权，其内容援引加入本文。
背景技术
本发明涉及一种制造半导体管芯(semiconductor die)的方法。
电气和电子设备的微型化和薄型化已经导致对更薄半导体器件和更薄半导体封装的需求。一种实现上述需求的方法是通过从半导体晶片的背侧去除多余材料来减薄晶片，这通常在晶片被切割成各个半导体管芯之前完成。
另一种制造更小的和更有效的半导体封装(semiconductorpackage)的方法是利用金属凸块的阵列接合到晶片的有源面。金属凸块被布置为与衬底上的接合焊垫相匹配。当金属回流成熔体时，其与接合焊垫连接，形成电气和机械连接。由于凸起的半导体被倒装以接合至它们的衬底，这种金属凸块封装通常被称为“倒装芯片”。
由于存在于半导体和衬底之间的热失配，反复的热循环给金属互连带来压力，可能导致最终的器件失效。为抵消这种现象，一种一般称作底部填料(underfill)的封装材料被设置在半导体和衬底之间的围绕和支撑金属凸块的空隙中。
半导体封装制造中的当前趋势偏向于在晶片级完成尽可能多的工艺步骤，允许同时处理多个集成电路，而不是逐个地发生在管芯分割(die singulation)之后。然而，减薄的硅半导体晶片是脆弱的，因此在半导体制造中使用如下工艺是有利的，在将晶片切割成单独的半导体管芯时不威胁晶片的完整性，并且具有尽可能少的步骤。
一种将半导体晶片切割成各个管芯的新方法被称为“隐形切割(stealth dicing)”。隐形切割是这样一种切割方法，其中激光束被照射到半导体晶片内部选定的区域，从而削弱这些区域中的硅键，使得在这些区域中更容易地分割硅晶片。使用隐形切割，很薄的半导体晶片可以被切割，而不会给晶片带来物理上的压力，减轻对晶片的损害，并且各个管芯的管芯强度没有减少。制备用于切割的晶片是有利的，从而可以利用隐形激光切割。
发明内容
本发明是一种制备用于切割的具有施加的底部填料的减薄的半导体晶片的方法，该方法减少了传统制造中的步骤，并且有助于隐形切割。该方法包括：(a)提供在有源面上具有多个金属凸块的减薄的半导体晶片，并且任选地，硅通孔垂直穿过所述硅晶片；(b)在切割支撑胶带上提供底部填料，其中所述底部填料被预先切割为所述半导体晶片的形状；(c)将所述切割支撑胶带上的底部填料与所述半导体晶片对齐布置，并且将所述底部填料层合至所述半导体晶片。在本方法的一个实施方式中，在底部填料和切割胶带之间设置分离层。在另一实施方式中，本发明是在其一侧上设置有具有底部填料的切割胶带。在另一实施方式中，分离层被设置在底部填料和切割胶带之间。
附图说明
图1描绘了待用于切割的具有预先施加的底部填料的减薄的半导体晶片的现有技术的制备方法。
图2描绘了待用于切割的具有预先施加的底部填料的减薄的半导体晶片的本发明的制备方法，和一些附加的制备步骤。
具体实施方式
本发明是一种用于制备用于切割的半导体晶片的方法。所述半导体晶片在其有源面上具有多个金属凸块。本发明的关键是使用在其一侧上布置有底部填料的切割胶带。由此，所述切割胶带／底部填料在一步中提供所述底部填料和所述切割胶带。并非将底部填料施加至半导体晶片，而是在单独的步骤中，将切割胶带安装至底部填料，切割胶带和底部填料的组合使用减少了制造工艺中的步骤。切割胶带、底部填料和晶片的集合(assembly)可以被设置在切割框架中，以便晶片的无源面朝上，便于隐形切割。
晶片按照已知方法从半导体材料来制备，通常为硅、砷化镓、锗或类似的化合物半导体材料。晶片顶侧上的多个金属凸块的形成以及它们的金属成分，是根据工业文献中充分记载的半导体和金属制造方法制成的。金属凸块被布置在半导体晶片的被称为有源面的一个面上，以匹配用于半导体的衬底上的金属接合焊垫。当金属回流成熔体时，其连接接合焊垫形成电气和机械连接。
硅通孔是完全延伸穿过硅晶片的垂直通道，目的是将电路从一个半导体晶片连接至另一个半导体晶片或连接至用于半导体的衬底。
切割胶带在制造过程中用于在切割操作中，即，在将半导体晶片切割成各个半导体管芯的过程中支撑晶片。切割胶带从多个来源可商购获得，并且可以是多种形式，包括在载体上的热敏、压敏或紫外线敏感粘合剂。载体通常是聚烯烃或聚酰亚胺的柔性衬底。当分别施加热、拉应力或紫外线时，粘合性减小，使得切割胶带被移除。通常，剥离衬里(releaseliner)覆盖粘合剂层，并且可以在使用切割胶带之前即刻容易地移除。
在制造过程中使用保护性支撑胶带或载体来在晶片减薄(或背研磨)工艺中保护和支撑金属凸块和晶片的有源面。在一些制造方法中，保护性支撑可以是玻璃板或片、另一硅晶片、或适于背研磨的胶带。背磨胶带从多个来源可商购获得，并且可以是多种形式，包括在载体上的热敏、压敏或紫外线敏感粘合剂。载体通常是聚烯烃或聚酰亚胺的柔性衬底。当分别施加热、拉应力或紫外线时，粘合性减小，使得保护性支撑胶带被移除。通常，剥离衬里覆盖粘合剂层，并且可以在使用保护性支撑之前即刻容易地移除。背研磨操作可以由机械研磨、激光研磨或刻蚀来实施。
已知的是适合用作底部填料化学性质的粘合剂和密封剂可以是以膜的形式，制备底部填料膜的方法也是已知的。适合的底部填料膜可以从例如环氧树脂、丙烯酸酯或硅基化学组成以及用于这些化学组成的硬化剂来制备。底部填料的厚度可以被调整以使金属凸块在层压之后可以完全或仅部分地被覆盖。不论在何种情况下，底部填料都被以一定数量和一定形式来提供以使其完全填充半导体和预定的衬底之间的空间。在实践中，底部填料被提供在载体上，并且由剥离衬里保护。从而，底部填料被提供为三层的形式，其中依次第一层是载体，如柔性的聚烯烃或聚酰亚胺胶带，第二层是底部填料，第三层是剥离衬里。仅在使用之前，剥离衬里被移除，底部填料通常在仍然附着至载体上时被施加。在向晶片施加底部填料之后，载体被移除。
在本发明中，底部填料密封剂被提供在切割胶带上。切割胶带可以是薄片形式，并且包含衬底膜和在所述衬底膜一侧上的压敏粘合剂层。底部填料密封剂以预先切割为晶片的尺寸和形状的形式被设置在切割胶带上。剥离衬里被安装至底部填料上，并且与底部填料和未被底部填料覆盖的切割胶带的部分(归因于底部填料的预先切割的形状)相接触。
参考附图对本发明做进一步说明。在图中，显示了切割胶带、硅晶片、金属凸块、底部填料和保护性支撑中一个或多个元件的集合(assembly)，硅晶片的有源面(包含金属凸块的面)朝上或朝下。所述集合可以在由执行者决定的对要执行的操作是适合和有益的任意方向上被处理。显示了切割胶带、背磨胶带和底部填料的每一个，而未示出剥离衬里。切割胶带和背磨胶带在使用后被丢弃。本领域技术人员能够理解剥离衬里通常用来保护切割胶带或背磨胶带的压敏粘合剂，并且仅在使用前移除剥离衬里。被层合至晶片的有源侧上的底部填料层会继续前进到切割和粘合步骤。
图1描绘了现有技术制备用于切割的具有预先施加的底部填料的凸起半导体的方法。制备减薄的半导体晶片13，其具有多个金属凸块11和保护性支撑12。晶片、凸块和保护性支撑的集合被支撑在例如真空吸盘台17上，然后移除保护性支撑12。底部填料14被层合至晶片的有源面，围绕和包封金属凸块11。切割胶带15被安装到底部填料上，并且切割胶带、底部填料和凸起晶片的集合被安装进切割框架(或夹具)16中，晶片的背侧朝上并暴露以用于后续的切割。
图2描绘本发明的方法，以及附加的步骤，以更完整说明如何实施本发明的方法。制备减薄的半导体晶片13，其在一面上具有多个金属凸块11和保护性支撑12。晶片、凸块和保护性支撑的集合被例如支撑在真空吸盘台17上，然后移除保护性支撑12。制备具有底部填料层14的切割胶带15作为切割胶带／底部填料的组合18。底部填料层14被预先切割为晶片的形状。切割胶带／预先切割的底部填料的这种组合被设置在半导体晶片13的金属凸块和有源面上，围绕和包封金属凸块11。切割胶带、底部填料和凸起晶片的集合被安装进切割框架16中，晶片的背侧朝上并暴露以用于后续的切割。这个朝向适合于隐形切割。
从而，在一个实施方式中，本发明是一种制备用于切割的具有施加的预先切割的底部填料的减薄的半导体晶片的方法，包括：(a)提供在有源面上具有多个金属凸块的减薄的硅半导体晶片，并且任选地，硅通孔垂直穿过所述硅半导体晶片；(b)在切割支撑胶带上提供底部填料，其中所述底部填料被预先切割成所述半导体晶片的形状；(c)将所述切割支撑胶带上的底部填料和所述半导体晶片对齐布置，并且将所述底部填料层合至所述半导体晶片。

Claims (2)

1.制造用于切割的具有施加的底部填料的减薄的半导体晶片的方法，包括：
(a)提供在有源面上具有多个金属凸块的减薄的硅半导体晶片，并且任选地，硅通孔垂直穿过所述硅半导体晶片；
(b)在切割支撑胶带上提供底部填料，其中所述底部填料被预先切割为所述半导体晶片的形状；
(c)将所述切割支撑胶带上的所述底部填料与所述半导体晶片对齐布置，并且将所述底部填料层合至所述半导体晶片。
2.支撑在切割胶带上的底部填料。
CN201280007466.3A 2011-02-01 2012-01-30 在切割胶带上施加有底部填料膜的预切割的晶片 Active CN103460361B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1484290A (zh) * 2002-07-12 2004-03-24 三星电子株式会社 切割带贴合单元和具有切割带贴合单元的序列式***
US20050006767A1 (en) * 2001-06-29 2005-01-13 Takashi Kumamoto Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
US20100047969A1 (en) * 2008-08-20 2010-02-25 Kim Won-Keun Backgrinding-underfill film, method of forming the same, semiconductor package using the backgrinding-underfill film, and method of forming the semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006767A1 (en) * 2001-06-29 2005-01-13 Takashi Kumamoto Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
CN1484290A (zh) * 2002-07-12 2004-03-24 三星电子株式会社 切割带贴合单元和具有切割带贴合单元的序列式***
US20100047969A1 (en) * 2008-08-20 2010-02-25 Kim Won-Keun Backgrinding-underfill film, method of forming the same, semiconductor package using the backgrinding-underfill film, and method of forming the semiconductor package

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