CN103456788B - 垂直功率mosfet及其形成方法 - Google Patents

垂直功率mosfet及其形成方法 Download PDF

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CN103456788B
CN103456788B CN201210309436.XA CN201210309436A CN103456788B CN 103456788 B CN103456788 B CN 103456788B CN 201210309436 A CN201210309436 A CN 201210309436A CN 103456788 B CN103456788 B CN 103456788B
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gate electrode
doped
drain region
semiconductor
region
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CN103456788A (zh
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苏柏智
周学良
柳瑞兴
伍震威
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种器件，包括半导体芯片中的半导体区，在所述半导体区上方的栅极介电层，以及在所述栅介电层上方的栅电极。漏极区设置在所述半导体区的顶面处并且与所述栅电极相邻。栅极间隔件在所述栅电极的侧壁上。介电层设置在栅电极和所述栅极间隔件上方。导电场板位于所述介电层上方，其中所述导电场板具有在所述栅电极的漏极侧上的部分。深金属通孔设置在所述半导体区中。源电极位于所述半导体区的下方，其中所述源电极通过所述深金属通孔与所述导电场板电短接。本发明还公开了垂直功率MOSFET及其形成方法。

Description

垂直功率MOSFET及其形成方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及垂直功率MOSFET及其形成方法。
背景技术
在传统的垂直功率金属氧化物半导体场效应晶体管(MOSFET)中，两个p体区形成在n型外延区中。由于垂直功率MOSFET的源电极和漏极区重叠，因而垂直功率MOSFET被如此命名。对两个p型体区之间的部分外延区进行轻掺杂以形成n型掺杂区，所述n型掺杂区有时称为N型结场效应晶体管(n-JFET)区。p体区和n-JFET区在栅极介电层和栅电极下方。当栅极被施加正电压时，在p体区中形成电子的聚集区。聚集区充当连接垂直功率MOSFET的源极区至n-JFET区的沟道区，n-JFET区进一步通过n型外延区连接至功率MOSFET的漏极区。因此，源极至漏极的电流从源极区传导至p体区、n-JFET区、外延区的沟道，然后至漏极区。
n-JFET区在栅电极下方，并且栅极介电层设置在n-JFET区和栅电极之间。在栅电极和n-JFET区之间存在大的重叠区。结果，存在明显的栅极至漏极电容，该栅极至漏极电容对影响垂直MOSFET的性能(包括速度)造成不利影响。而且，由于n-JFET区是n型外延区的部分，因此n-JFET区被轻掺杂。因此，n-JFET区的电阻很高，这对垂直功率MOSFET的驱动电流造成不利影响。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，包括：
位于半导体芯片中的半导体区；
位于所述半导体区上方的栅极介电层；
位于所述栅极介电层上方的栅电极；
位于所述半导体区的顶面并与所述栅电极相邻的漏极区；
位于所述栅电极的侧壁上的栅极间隔件；
位于所述栅电极和所述栅极间隔件上方的介电层；
位于所述介电层上方的导电场板，其中，所述导电场板包括位于所述栅电极的漏极侧上的部分；
位于所述半导体区中的深金属通孔；以及
位于所述半导体区下方的源电极，其中，所述源电极通过所述深金属通孔与所述导电场板电短接。
在可选实施例中，所述器件进一步包括位于所述半导体区中的掺杂漏极(DD)区，其中，所述DD区的杂质浓度低于所述漏极区的杂质浓度，以及所述DD区横向位于所述栅电极和所述漏极区之间并具有比所述漏极区的底部低的底部。
在可选实施例中，所述DD区的边缘与所述栅电极的边缘基本对准。
在可选实施例中，所述器件进一步包括：半导体源极区，所述半导体源极区和所述漏极区位于所述栅电极的相对侧并具有相同的导电类型；以及延伸至所述栅电极下方的体区，所述半导体源极区位于所述体区中，其中，所述体区在所述栅电极下方延伸，并且所述深金属通孔接触所述半导体源极区的侧壁和所述体区的侧壁。
在可选实施例中，所述半导体区包括：重掺杂层；以及位于所述重掺杂层上方的轻掺杂层，其中，所述轻掺杂层和所述重掺杂层的导电类型与所述漏极区的导电类型相反，所述深金属通孔穿透所述轻掺杂层并与所述重掺杂层接触。
在可选实施例中，所述器件进一步包括：另外的MOS器件，选自基本由形成在所述半导体区的顶面处的低压MOSFET和高端MOSFET所组成的组。
在可选实施例中，所述源电极在所述另外的MOS器件的下方延伸。
根据本发明的另一个方面，还提供了一种器件，包括：
金属源电极；
位于所述金属源电极上方且为第一导电类型的重掺杂半导体层；
位于所述重掺杂半导体层上方且为所述第一导电类型的轻掺杂半导体层；
位于所述轻掺杂半导体层上方的栅极介电层；
位于所述栅极介电层上方的栅电极；
位于所述栅电极的相对侧上的源极区和漏极区，所述源极区和所述漏极区具有与所述第一导电类型相反的第二导电类型；以及
从所述源极区的顶面向下延伸以接触所述重掺杂半导体层的深金属通孔，其中，所述深金属通孔与所述金属源电极电短接。
在可选实施例中，所述器件进一步包括：在所述栅电极下方延伸且为所述第一导电类型的体区，其中，所述源极区位于所述体区中，并且所述深金属通孔与所述源极区的侧壁和所述体区的侧壁接触。
在可选实施例中，所述器件进一步包括：掺杂漏极(DD)区，具有与所述栅电极的边缘基本对准的边缘，其中所述漏极区位于所述DD区中，并且所述DD区的一部分将所述漏极区与所述栅电极横向隔开。
在可选实施例中，所述器件进一步包括：
介电层，包括位于所述栅电极的顶面上方的第一部分以及覆盖所述DD区的第二部分；以及位于所述介电层上方的导电场板，其中所述导电场板包括与所述栅电极齐平并覆盖所述DD区的一部分，并且所述导电场板与所述深金属通孔电短接。
在可选实施例中，所述导电场板和所述深金属通孔由相同的材料形成。
在可选实施例中，所述器件进一步包括：位于所述轻掺杂半导体层的顶部中且为所述第二导电类型的高压阱区；以及包括源极区和漏极区的低压MOS器件，其中，所述低压MOS器件的源极区和漏极区位于所述高压阱区中。
在可选实施例中，所述器件进一步包括：位于所述轻掺杂半导体层的顶部中且为所述第二导电类型的高压阱区；以及包括源极区和漏极区的高端MOS器件，其中所述高端MOS器件的源极区和漏极区位于所述高压阱区中。
根据本发明的又一个方面，还提供了一种方法，包括：
实施外延以在为第一导电类型的重掺杂半导体衬底上方形成为所述第一导电类型的轻掺杂半导体层；
在所述轻掺杂半导体层上方形成栅极介电层；
在所述栅极介电层上方形成栅电极；
在所述栅电极的相对侧上形成漏极区和源极区，其中所述漏极区和所述源极区具有与所述第一导电类型相反的第二导电类型；
形成从所述源极区的顶面向下延伸以接触所述轻掺杂半导体衬底的沟槽；
用金属材料填充所述沟槽以形成深金属通孔；以及
在所述重掺杂半导体衬底下方沉积源电极，其中所述深金属通孔与所述源极区和所述源电极短接。
在可选实施例中，所述方法进一步包括：形成导电场板，所述导电场板包括位于所述栅电极的漏极侧上的部分；以及形成使所述导电场板与所述深金属通孔电短接的电连接。
在可选实施例中，在所述方法中，同时进行填充所述沟槽的步骤和形成所述导电场板的步骤。
在可选实施例中，所述方法进一步包括：实施垂直注入以注入所述轻掺杂半导体层来形成所述第二导电类型的掺杂漏极(DD)区，其中所述漏极区在所述DD区中，并且所述DD区的一部分将所述漏极区与所述栅电极横向隔开。
在可选实施例中，所述方法进一步包括：
当进行形成所述栅极介电层和所述栅电极的步骤时，同时形成用于低压MOS器件的栅极介电层和栅电极；以及，当进行形成所述源极区和所述漏极区的步骤时，同时形成用于所述低压MOS器件的源极区和漏极区。
在可选实施例中，所述方法进一步包括：
当进行形成所述栅极介电层和所述栅电极的步骤时，同时形成用于高端MOS器件的栅极介电层和栅电极；以及，当进行形成所述源极区和所述漏极区的步骤时，同时形成用于所述高端MOS器件的源极区和漏极区。
附图说明
为了更完整理解实施方式，以及其优势，现在结合附图参考下面的描述，其中：
图1至图9是根据一些示例性实施方式的垂直功率金属氧化物半导体场效应晶体管(MOSFET)制造过程中的中间阶段的截面图。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅是示例说明，并不用于限制本发明的范围。
根据各种示例性实施方式，提供了垂直功率金属氧化物半导体场效应晶体管(MOSFET)及其形成方法。示例说明了形成垂直功率MOSFET的中间阶段。讨论了实施例的变形。贯穿各种视图和示例说明的实施例，相同的标号用于指代相同的元件。
图1至图9是n型垂直功率MOSFET形成过程中的中间阶段的截面图。参照图1，提供了可以为半导体衬底的半导体层20。半导体层20可以具有晶体硅结构。可选地，半导体层20由其他材料形成，例如，硅锗。在一些实施例中，半导体层20是重掺杂层(P+层)，掺杂有杂质浓度在大约1019/cm3和大约1021/cm3之间的p型杂质(例如，磷或者砷)。在所描述的实施例中，术语“重掺杂”指杂质浓度在大约1019/cm3以上。然而，本领域技术人员会理解，重掺杂是取决于具体的器件类型、技术代、最小部件尺寸等的技术术语。因此，意图基于被评估的技术解释术语，并不受限于所描述的实施例。
外延层22通过外延形成在重掺杂半导体层20上方，并且轻掺杂有p型杂质。外延层22的杂质浓度在大约1014/cm3和大约1016/cm3之间。然而，应当理解，整个说明书的所述数值仅是实例，并且可以改变成不同的数值。因此，外延层22为P层，并且此后称为P外延层22。P外延层22可以为硅层，然而其他的半导体材料(例如，锗、硅锗、III-V化合物半导体或类似物)也可用于形成P外延层22。
与P外延层22的顶面相邻形成隔离区24。隔离区24可以为浅沟槽隔离(STI)区，并且此后称为STI区24，然而它们还可以为其他类型的隔离区，例如，通过局部氧化P型外延层22形成的场氧化物。STI区24可被用于分离不同的器件区，包括垂直功率MOSFET区100、高端MOSFET区200，低压NMOSFET区300以及低压PMOSFET区400。
参照图2，通过诸如向外延层22内注入n型杂质在高端MOSFET区200中形成高压N阱(HVNW)区226。还分别在低压NMOSFET区300和低压PMOSFET区400中形成HVNW区326和426。HVNW区226、326和426从P外延层22的顶面向下延伸至P外延层22内。HVNW区226、326和426的底面高于重掺杂半导体层20的顶面。因此，HVNW区226、326和426通过部分P外延层22与重掺杂半导体层20间隔开。例如，HVNW区226、326和426可以具有在大约1014/cm3和大约1017/cm3之间的杂质浓度。
再次参照2，p阱区330通过诸如注入形成在低压NMOSFET区300中。P阱区330从HVNW区326的顶面延伸至HVNW区326内。p阱区330的底面可以高于HVNW区326的底面。因此，p阱区330通过部分HVNW区326与P外延层22分隔开。P阱区330可以具有在大约1015/cm3和大约1018/cm3之间的杂质浓度。
接着，如图3所示，形成栅氧化层32。在一些实施例中，形成工艺包括热氧化工艺。因此，栅氧化层32可包括氧化硅。在可选的实施例中，栅氧化层32通过沉积形成。相应的栅氧化层32可包含氧化硅、氮化硅、氮氧化硅、碳化硅、它们的组合或它们的多层。栅电极层34形成在栅氧化层32上方。形成工艺可包括均厚沉积导电材料。在一些实施例中，栅电极层34包括多晶硅，然而其他导电材料(例如，金属、金属硅化物，等等)也可被使用。
同样，如图3所示，垂直功率MOSFET区100和高端MOSFET区200中的部分栅电极层34在图案化步骤中被去除。然后，实施注入以通过向P外延层22中注入p型杂质来形成p体区136和236。p体区136和236的p型杂质浓度可在大约1016/cm3和大约1019/cm3之间。在一些示例性实施例中，p体区136和236的注入在图案化栅电极层34之后以及在位于栅电极层34的所去除部分下面的栅氧化层32部分去除之前实施。在注入后，位于栅电极层34的所去除部分下面的栅氧化层32部分也被去除。
接着，参照图4，进一步图案化栅氧化层32和栅电极层34以分别在器件区100、200、300以及400中形成栅堆叠件135、235、335以及435。然后，实施注入以分别在垂直功率MOSFET区100和高端MOSFET区200中形成N型掺杂漏极(NDD)区138和238。注入的n型杂质可包括磷和/或砷。NDD区138和238的n型杂质浓度可在大约1016/cm3和大约1019/cm3之间。注入可以是基本垂直的，以便边缘138A和238A分别与栅电极134和234的边缘134A和234A对准，因此，NDD区138和238的形成是与134A和234A的边缘自对准的。结果，在栅电极134和NDD区138之间基本不存在重叠，并且在栅电极234和NDD区238之间基本不存在重叠。这归因于器件区100和200中所得到的MOSFET的栅极-漏极电容降低。
在图5中，栅极间隔件139、239、339和439例如通过以下方式形成：沉积介电层，然后蚀刻介电层以去除水平部分。介电层的剩余的垂直部分形成栅极间隔件139、239、339以及439。
参照图6，实施n型注入步骤以形成重掺杂n型源极区/漏极区140、142、240、242、340和342以及n型拾取区444。注入区可具有诸如在大约1019/cm3和大约1021/cm3之间的n型掺杂浓度。而且，实施p型注入步骤以形成重掺杂p型源极区/漏极区440和442以及P+拾取区244和344。注入区可具有诸如大约1019/cm3和1021/cm3之间的p型掺杂浓度。
参照图7，形成介电层146和246。介电层146可包括位于栅电极134、栅极间隔件139和/或NDD区138上方的部分。在一些实施例中，介电层146可进一步覆盖N+区140。介电层246可包括位于栅电极234、栅极间隔件239和/或NDD区238上方的部分。介电层146和246可包括氧化物、氮化物、氮氧化物、它们的组合以及它们的多层。形成工艺可包括形成均厚层的均厚沉积(blanket deposition)步骤，接着是图案化均厚层的图案化步骤。在可选的实施例中，均厚层的图案化可在场板152和252以及深金属通孔150(未在图7中示出，请参见图8)形成之后实施。
同样，如图7所示，实施蚀刻步骤以蚀刻N+源极区140、p体区136以及P外延层22。通过所得到的沟槽148暴露重掺杂半导体层20。沟槽148还可延伸进入重掺杂半导体区20的顶部。重掺杂半导体区20的底部不被蚀刻。在一些实施例中，沟槽148还暴露N+区140和p体区136的侧壁。
在图8中，导电材料被填充至沟槽148内以及介电层146和246的上方。形成工艺可包括均厚沉积步骤，以及去除导电材料的多余部分的图案化/后蚀刻步骤。介电层146和246上方的导电材料部分分别形成场板(fieldplate)152和252。场板152可以或者可以不包括与部分栅电极134重叠的第一部分，并且可以包括与栅电极134的漏极侧齐平并且在其上的第二部分。场板152的第二部分与NDD区138重叠。同样地，场板252可以包括，或者可以不包括与部分栅电极234重叠的第一部分，并且可进一步地包括与栅电极234的漏极侧齐平并且在其上的第二部分。用于形成场板152和252的导电材料可包括金属(例如，钨、铝、镍，等等)，然而也可使用其它的导电材料(例如，多晶硅、金属硅化物，等等)。导电材料的一部分形成电连接并且接触N+区140和p体区136的深通孔150。深通孔150还与重掺杂半导体层20电短接。
参照图9，形成电连接以将深金属通孔150与场板152电短接。例如，电连接可包括接触插塞154和金属线158。而且，导电材料被沉积在重掺杂半导体区20上以形成源电极153。因此，源极区和漏极区140/142以及源电极153形成在各自的晶圆和芯片的相对的面上。在一些实施例中，源电极153包括诸如铝、铜、钨、镍等的金属。随着深通孔152的形成，场板152与短接源电极153(通过重掺杂半导体层20)。同样，源极区140通过深通孔150连接至源电极153。因此，也形成垂直功率MOSFET 160。也完成高端MOSFET 260、低压NMOSFET 360以及低压PMOSFET 460的形成。
使用弯箭头62示意性示出垂直功率MOSFET100的电流，所述弯箭头62穿过漏极区142、NDD区138、P外延层22和p型体136中的沟道区64、源极区140、深通孔150、重掺杂半导体层20并且到达源电极153。
尽管图1至图9中示出的实施例提供了形成n-型垂直功率MOSFET的方法，本领域技术人员会理解所提供的教导易于适用于p-型垂直功率MOSFET的形成，其相应的掺杂半导体区的导电类型相反。
在实施例中，NDD区138与栅电极134的边缘自对准。因此，使得栅电极134和NDD区138之间的重叠最小化，并因此最小化栅极到漏极的电容。场板152与半导体源极区140和源电极153短接，并且因此场板152不贡献栅极到漏极的电容。源电极153和源极区/漏极区140/142在各自芯片的相对侧，并且源电极153位于源极区/漏极区140/142的下方。由于沟道64是水平的，各MSOFET 160的击穿电压由横向尺寸决定，例如，NDD区138的宽度和p体区136的宽度，以及p体区136和NDD区138之间P外延层22部分的宽度。可以为金属通孔的深通孔150连接至重掺杂半导体层20。深通孔150形成了用于降低垂直功率MOSFET 160的体电阻的深体拾取区。
根据一种实施例，一种器件，包括半导体芯片中的半导体区，半导体区上方的栅极介电层，以及栅极介电层上方的栅电极。漏极区设置在半导体区的顶面并且与栅电极相邻。栅极间隔件在栅电极的侧壁上。介电层设置在栅电极和栅极间隔件的上方。导电场板位于介电层上方，其中导电场板具有栅电极的漏极侧上的一部分。深金属通孔设置在半导体区中。源电极位于半导体区下方，其中源电极通过深金属通孔对导电场板短接。
根据另一种实施例，一种器件，包括金属源电极，位于金属源电极上方且为第一导电类型的重掺杂半导体层，位于重掺杂半导体层上方且为第一导电类型的轻掺杂半导体层。栅极介电层位于轻掺杂半导体层上方。栅电极位于栅极介电层上方。漏极区和源极区位于栅电极的相对侧，其中漏极区和源极区具有与第一导电类型相反的第二导电类型。深金属通孔从源极区的顶面向下延伸以接触重掺杂半导体层，其中深金属通孔与源极区电短接。
根据又一种实施例，一种方法，包括实施外延以在第一导电类型的重掺杂半导体衬底上方形成为第一导电类型的轻掺杂半导体层，在轻掺杂半导体层上方形成栅极介电层，在栅极介电层上方形成栅电极。在栅电极的相对侧形成漏极区和源极区，其中漏极区和源极区具有与第一导电类型相反的第二导电类型。形成从源极区的顶面向下延伸以接触重掺杂半导体衬底的沟槽。所述沟槽用金属材料填充以形成深金属通孔。源电极沉积在重掺杂半导体衬底的下方，其中深金属通孔与源极区和源电极短接。
尽管已经详细地描述了本发明及其优点，但应该理解为，在不背离所附权利要求限定的本发明主旨和范围的情况下，可以做各种不同的改变，替换和更改。而且，本申请的范围并不旨在仅限于本说明书中描述的工艺、机器、制造，材料组分、器件、方法和步骤的特定实施例。作为本领域普通技术人员从说明书中应理解，根据本发明，现有或今后开发的与在此描述的实施例实现基本相同的功能或者获得相同结果的工艺、机器、制造，材料组分、装置、方法或步骤也可以使用。因此，所附权利要求旨在将这样的工艺、机器、制造、材料组分、器件、方法或步骤包括在保护范围内。此外，每项权利要求构成单独的实施例，各项权利要求和实施例的组合包括在本发明范围内。

Claims (18)

1.一种半导体器件，包括：
位于半导体芯片中的半导体区；
位于所述半导体区上方的栅极介电层；
位于所述栅极介电层上方的栅电极；
位于所述半导体区的顶面并与所述栅电极相邻的漏极区，以及位于所述半导体区中的掺杂漏极(DD)区，其中，所述掺杂漏极区的边缘与所述栅电极的边缘基本对准；
位于所述栅电极的侧壁上的栅极间隔件；
位于所述栅电极和所述栅极间隔件上方的介电层；
位于所述介电层上方的导电场板，其中，所述导电场板包括位于所述栅电极的漏极侧上的部分；
位于所述半导体区中的深金属通孔；以及
位于所述半导体区下方的源电极，其中，所述源电极通过所述深金属通孔与所述导电场板电短接，所述导电场板与所述深金属通孔通过金属线和接触插塞电连接。
2.根据权利要求1所述的器件，其中，所述掺杂漏极区的杂质浓度低于所述漏极区的杂质浓度，以及所述掺杂漏极区横向位于所述栅电极和所述漏极区之间并具有比所述漏极区的底部低的底部。
3.根据权利要求1所述的器件，进一步包括：
半导体源极区，所述半导体源极区和所述漏极区位于所述栅电极的相对侧并具有相同的导电类型；以及
延伸至所述栅电极下方的体区，所述半导体源极区位于所述体区中，其中，所述体区在所述栅电极下方延伸，并且所述深金属通孔接触所述半导体源极区的侧壁和所述体区的侧壁。
4.根据权利要求1所述的器件，其中所述半导体区包括：
重掺杂层；以及
位于所述重掺杂层上方的轻掺杂层，其中，所述轻掺杂层和所述重掺杂层的导电类型与所述漏极区的导电类型相反，所述深金属通孔穿透所述轻掺杂层并与所述重掺杂层接触。
5.根据权利要求1所述的器件，进一步包括：
另外的MOS器件，选自由形成在所述半导体区的顶面处的低压MOSFET和高端MOSFET所组成的组。
6.根据权利要求5所述的器件，其中，所述源电极在所述另外的MOS器件的下方延伸。
7.一种半导体器件，包括：
金属源电极；
位于所述金属源电极上方且为第一导电类型的重掺杂半导体层；
位于所述重掺杂半导体层上方且为所述第一导电类型的轻掺杂半导体层；
位于所述轻掺杂半导体层上方的栅极介电层；
位于所述栅极介电层上方的栅电极；
位于所述栅电极的相对侧上的源极区和漏极区，所述源极区和所述漏极区具有与所述第一导电类型相反的第二导电类型，以及位于所述半导体区中的掺杂漏极(DD)区，所述掺杂漏极(DD)区具有与所述栅电极的边缘基本对准的边缘；
位于所述栅电极的顶面上方的介电层；
从所述源极区的顶面向下延伸以接触所述重掺杂半导体层的深金属通孔，其中，所述深金属通孔与所述金属源电极电短接；以及
位于所述介电层上方的导电场板，所述导电场板与所述深金属通孔通过金属线和接触插塞电连接。
8.根据权利要求7所述的器件，进一步包括：在所述栅电极下方延伸且为所述第一导电类型的体区，其中，所述源极区位于所述体区中，并且所述深金属通孔与所述源极区的侧壁和所述体区的侧壁接触。
9.根据权利要求7所述的器件，其中，所述漏极区位于所述掺杂漏极区中，并且所述掺杂漏极区的一部分将所述漏极区与所述栅电极横向隔开。
10.根据权利要求9所述的器件，其中，
所述介电层包括位于所述栅电极的顶面上方的第一部分以及覆盖所述掺杂漏极区的第二部分；以及
所述导电场板包括与所述栅电极齐平并覆盖所述掺杂漏极区的一部分。
11.根据权利要求10所述的器件，其中，所述导电场板和所述深金属通孔由相同的材料形成。
12.根据权利要求7所述的器件，进一步包括：
位于所述轻掺杂半导体层的顶部中且为所述第二导电类型的高压阱区；以及
包括源极区和漏极区的低压MOS器件，其中，所述低压MOS器件的源极区和漏极区位于所述高压阱区中。
13.根据权利要求7所述的器件，进一步包括：
位于所述轻掺杂半导体层的顶部中且为所述第二导电类型的高压阱区；以及
包括源极区和漏极区的高端MOS器件，其中所述高端MOS器件的源极区和漏极区位于所述高压阱区中。
14.一种形成半导体器件的方法，包括：
实施外延以在为第一导电类型的重掺杂半导体衬底上方形成为所述第一导电类型的轻掺杂半导体层；
在所述轻掺杂半导体层上方形成栅极介电层；
在所述栅极介电层上方形成栅电极；
在所述栅电极的相对侧上形成漏极区和源极区，其中所述漏极区和所述源极区具有与所述第一导电类型相反的第二导电类型，其中，实施垂直注入以注入所述轻掺杂半导体层来形成所述第二导电类型的掺杂漏极(DD)区；
在所述栅电极上方形成介电层；
形成从所述源极区的顶面向下延伸以接触所述轻掺杂半导体衬底的沟槽；
用金属材料填充所述沟槽以形成深金属通孔；
形成导电场板，所述导电场板包括位于所述栅电极的漏极侧上的部分；
形成使所述导电场板与所述深金属通孔通过金属线和接触插塞电连接；以及
在所述重掺杂半导体衬底下方沉积源电极，其中所述深金属通孔与所述源极区和所述源电极短接。
15.根据权利要求14所述的方法，其中，同时进行填充所述沟槽的步骤和形成所述导电场板的步骤。
16.根据权利要求14所述的方法，其中，所述漏极区在所述掺杂漏极区中，并且所述掺杂漏极区的一部分将所述漏极区与所述栅电极横向隔开。
17.根据权利要求14所述的方法，进一步包括：
当进行形成所述栅极介电层和所述栅电极的步骤时，同时形成用于低压MOS器件的栅极介电层和栅电极；以及
当进行形成所述源极区和所述漏极区的步骤时，同时形成用于所述低压MOS器件的源极区和漏极区。
18.根据权利要求14所述的方法，进一步包括：
当进行形成所述栅极介电层和所述栅电极的步骤时，同时形成用于高端MOS器件的栅极介电层和栅电极；以及
当进行形成所述源极区和所述漏极区的步骤时，同时形成用于所述高端MOS器件的源极区和漏极区。
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