CN103456692A - Method for forming complementary metal-oxide-semiconductor tube - Google Patents
Method for forming complementary metal-oxide-semiconductor tube Download PDFInfo
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- CN103456692A CN103456692A CN2012101747164A CN201210174716A CN103456692A CN 103456692 A CN103456692 A CN 103456692A CN 2012101747164 A CN2012101747164 A CN 2012101747164A CN 201210174716 A CN201210174716 A CN 201210174716A CN 103456692 A CN103456692 A CN 103456692A
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Abstract
The invention discloses a method for forming a complementary metal-oxide-semiconductor tube. The method includes that a semiconductor substrate comprises a first area and a second area which are adjacent to each other, an insulating layer is formed on the surface of the semiconductor substrate, a first opening is formed in the first area and penetrates the insulating layer, a second opening is formed in the second area and penetrates the insulating layer, a first functional layer and a first sacrificial layer are formed in the bottom and the side walls of the first opening, and the first sacrificial layer is flush with the surface of the insulating layer; a second functional layer is formed, not only is positioned at the bottom and on the side walls of the second opening, but also covers the surface of the insulating layer and the surface of the first sacrificial layer; a second sacrificial layer positioned in the second area is formed, and the second functional layer in the first area, the first sacrificial layer and the second sacrificial layer are removed in the same step; a first gate electrode layer and a second gate electrode layer are formed, the first gate electrode layer covers the first functional layer, and the second gate electrode layer covers the second functional layer. The method in an embodiment of the invention has the advantages that the gate electrode height of the CMOS (complementary metal-oxide-semiconductor) tube is identical to a designed height, technological steps are simple, and the CMOS tube is stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe.
Background technology
At present, CMOS (Complementary Metal Oxide Semiconductor) pipe (Complementary Metal-Oxide-Semiconductor, CMOS) has become the basic device in chip.Described CMOS pipe comprises: P-type mos (PMOS) and N-type metal-oxide semiconductor (MOS) (NMOS).
Along with the development of semiconductor fabrication, CMOS manages continuous scaled down, to obtain the higher chip of integrated level.Yet, after the CMOS pipe narrows down to a certain degree, the grid length in the CMOS pipe foreshortens to the limit, short-channel effect highlights.In order to control short-channel effect, improve gate electrode electric capacity, prior art adopts the high K dielectric material to replace for example silica formation gate dielectric layer of traditional dielectric material, and employing metal material for example aluminium (Al) replaces polysilicon as gate electrode.
Threshold voltage for PMOS pipe and NMOS tube grid in adjusting CMOS pipe, also need to manage at PMOS, the gate dielectric layer surface of NMOS pipe forms functional layer (work function layer), because the functional layer of the PMOS pipe formed and NMOS pipe is different, when prior art forms the CMOS (Complementary Metal Oxide Semiconductor) pipe, zone at the zone that forms the PMOS pipe and formation NMOS pipe forms dummy gate structure, take described dummy gate structure after mask forms source/drain region, need to remove the dummy gate structure in a zone in above-mentioned two zones, form successively gate dielectric layer, functional layer and gate electrode layer, then remove the dummy gate structure in another zone, form and be positioned at this regional gate dielectric layer successively again, functional layer and gate electrode layer.
The performance of the CMOS (Complementary Metal Oxide Semiconductor) pipe that prior art forms is stable not.
More methods of the formation about the CMOS (Complementary Metal Oxide Semiconductor) pipe, please refer to the United States Patent (USP) that publication number is " US20100065915 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe of good stability.
For addressing the above problem, embodiments of the invention provide a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe, comprising:
Provide and comprise adjacent first area and the Semiconductor substrate of second area, described semiconductor substrate surface is formed with insulating barrier, and described first area has the first opening that runs through described insulating barrier, the bottom of described the first opening and sidewall are formed with the first functional layer, described the first functional layer surface coverage has the first sacrifice layer, described the first sacrifice layer flushes with described surface of insulating layer, and described second area has the second opening that runs through described insulating barrier;
Form the second functional layer, described the second functional layer covers bottom and sidewall, surface of insulating layer and first sacrificial layer surface of described the second opening;
Form the second sacrifice layer, described the second sacrifice layer covers insulating barrier and the second functional layer in second area;
Remove the second functional layer and first sacrifice layer of described first area, and remove the second sacrifice layer of described second area, expose the first interior functional layer of the first opening and the second functional layer of second area;
After removing the first sacrifice layer and the second sacrifice layer, form to cover the first grid electrode layer of described the first functional layer, form the second gate electrode layer that covers described the second functional layer, and described first grid electrode layer and second gate electrode layer flush with described surface of insulating layer.
Alternatively, the material of described the first functional layer and the second functional layer is one or more combinations in titanium nitride, tantalum, tantalum nitride, titanium aluminide, titanium, cobalt or nickel, and the material of described the first functional layer is different from the material of described the second functional layer.
Alternatively, polishing speed during described the first sacrifice layer of chemico-mechanical polishing is greater than the polishing speed of described insulating barrier.
Alternatively, the material of described the first sacrifice layer is polysilicon, poly-SiGe or unformed silicon.
Alternatively, the etch rate of the material of described the second sacrifice layer is greater than the etch rate of described insulating barrier.
Alternatively, the etch rate of described the second sacrifice layer is identical with the etch rate of described the first sacrifice layer.
Alternatively, the material of described the second sacrifice layer is photoresist, and the method for described the second sacrifice layer of follow-up removal is the cineration technics that comprises oxygen.
Alternatively, the formation technique of described the first sacrifice layer is physics or chemical vapour deposition (CVD).
Alternatively, the power of described chemical vapour deposition (CVD) is less than 400 watts.
Alternatively, the technique of removing the second sacrifice layer of described second area is dry etch process.
Alternatively, the etching gas that described dry etch process adopts is fluorine-containing or chloride gas, and the bias power of etching is less than 200 watts.
Alternatively, also comprise: form first grid dielectric layer and second gate dielectric layer, described first grid dielectric layer is formed between the bottom and the first functional layer of described the first opening, and described second gate dielectric layer is formed between the bottom and the second functional layer of described the second opening.
Alternatively, also comprise: form the first boundary layer and second contact surface layer, described the first boundary layer is formed between Semiconductor substrate and first grid dielectric layer, between the formation of described second contact surface layer and Semiconductor substrate and second gate dielectric layer.
Alternatively, also comprise: form the first protective layer and the second protective layer, described the first protective layer is formed at described first grid dielectric layer surface, and described the second protective layer is formed at described second gate dielectric layer surface.
Alternatively, the material of described the first protective layer and the second protective layer is titanium nitride or tantalum nitride or both combinations.
Compared with prior art, embodiments of the invention have the following advantages:
The second functional layer formed is except the bottom and sidewall of the insulating barrier that covers second area, the second opening; also cover insulating barrier and first sacrifice layer of described first area; the second functional layer that covers first area insulating barrier and the first sacrifice layer can protect insulating barrier not suffer a loss in subsequent technique; thereby make the first grid electrode layer of follow-up formation and the height of second gate electrode layer can not reduce; the PMOS pipe formed and the stable performance of NMOS pipe, the stable performance of the final CMOS pipe formed.
The accompanying drawing explanation
Fig. 1 is the schematic flow sheet of formation method of the CMOS (Complementary Metal Oxide Semiconductor) pipe of the embodiment of the present invention;
Fig. 2-Fig. 9 is the cross-sectional view of formation method of the CMOS (Complementary Metal Oxide Semiconductor) pipe of the embodiment of the present invention.
Embodiment
From background technology, the performance of the CMOS (Complementary Metal Oxide Semiconductor) pipe that prior art forms is stable not.
Through research, the inventor finds, the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe in prior art, the step that has comprised twice chemico-mechanical polishing and etching, the step of described twice chemico-mechanical polishing and etching very easily causes the height little (gate height loss) of gate electrode layer of aspect ratio design of the gate electrode layer of actual formation, thereby has affected the stability of semiconductor device.
After further research, invent a kind of formation method that everybody provides new CMOS (Complementary Metal Oxide Semiconductor) pipe, saved processing step, the stable performance of the CMOS (Complementary Metal Oxide Semiconductor) pipe of formation.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Please refer to Fig. 1, the formation method of the CMOS (Complementary Metal Oxide Semiconductor) pipe of the embodiment of the present invention comprises:
Step S201, provide and comprise adjacent first area and the Semiconductor substrate of second area, described semiconductor substrate surface is formed with insulating barrier, and described first area has the first opening that runs through described insulating barrier, the bottom of described the first opening and sidewall are formed with the first functional layer, described the first functional layer surface coverage has the first sacrifice layer, and described the first sacrifice layer flushes with described surface of insulating layer, and described second area has the second opening that runs through described insulating barrier;
Step S203, form the second functional layer, and described the second functional layer covers bottom and sidewall, surface of insulating layer and first sacrificial layer surface of described the second opening;
Step S205, form the second sacrifice layer, and described the second sacrifice layer covers insulating barrier and the second functional layer in second area;
Step S207, remove the second functional layer and first sacrifice layer of described first area, and remove the second sacrifice layer of described second area, exposes the first interior functional layer of the first opening and the second functional layer of second area;
Step S209, after removing the first sacrifice layer and the second sacrifice layer, form to cover the first grid electrode layer of described the first functional layer, form the second gate electrode layer that covers described the second functional layer, and described first grid electrode layer and second gate electrode layer flush with described surface of insulating layer.
Concrete, please refer to Fig. 2-Fig. 9, Fig. 2-Fig. 9 shows the cross-sectional view of the forming process of CMOS (Complementary Metal Oxide Semiconductor) pipe of the present invention.
Please refer to Fig. 2, the Semiconductor substrate 200 that comprises adjacent first area I and second area II is provided, described Semiconductor substrate 200 surfaces are formed with insulating barrier 203, and described first area I has the first dummy gate structure 205 that runs through described insulating barrier 203, described second area II has the second dummy gate structure 207 that runs through described insulating barrier 203.
Described Semiconductor substrate 200 is used to subsequent technique that platform is provided.Described Semiconductor substrate 200 is body silicon or silicon-on-insulator (SOI).In an embodiment of the present invention, described Semiconductor substrate 200 is body silicon.
Described first area I is adjacent with second area II, and both are isolated by fleet plough groove isolation structure 201, to form respectively PMOS pipe and NMOS pipe.In an embodiment of the present invention, described first area I is used to form the PMOS pipe, and described second area II is used to form the NMOS pipe, and the material of described fleet plough groove isolation structure 201 is silica.
It should be noted that, in other embodiments of the invention, can be also: described first area I be used to form the NMOS pipe, and described second area II is used to form the PMOS pipe.
Described the first dummy gate structure 205 and the second dummy gate structure 207 are for the position of the gate electrode layer of the gate electrode layer that defines the PMOS pipe and NMOS pipe.The material of described the first dummy gate structure 205 and the second dummy gate structure 207 is polysilicon.The formation step of described the first dummy gate structure 205 and the second dummy gate structure 207 comprises: the dummy grid film (not shown) that forms Semiconductor substrate 200 surfaces that cover described first area I and second area II; Formation is positioned at first mask layer (for example photoresist layer) of described dummy grid film surface; Take described photoresist layer as the described dummy grid film of mask etching, form respectively the first dummy gate structure 205 and the second dummy gate structure 207.
Described insulating barrier 203 is for the gate electrode layer of follow-up isolation PMOS pipe and the gate electrode layer of NMOS pipe.The formation technique of described insulating barrier 203 is depositing operation, for example physics or chemical vapor deposition method.The material of described insulating barrier 203 is the dielectric materials such as silica, silicon oxynitride.In an embodiment of the present invention, described insulating barrier 203 forms after forming the first dummy gate structure 205 and the second dummy gate structure 207, and the formation step of described insulating barrier 203 comprises: form the insulation film (not shown) that covers described Semiconductor substrate 200, the first dummy gate structure 205 and the second dummy gate structure 207; The described insulation film of planarization, for example adopt CMP (Chemical Mechanical Polishing) process, forms the insulating barrier 203 with described the first dummy gate structure 205 and the second dummy gate structure 207 flush.
It should be noted that, for preventing, in subsequent etching technique, Semiconductor substrate 200 is caused to damage, in an embodiment of the present invention, also comprise: before forming insulating barrier 203, form the etching stop layer that covers described the first dummy gate structure 205, the second dummy gate structure 207 and Semiconductor substrate 200.The material of described etching stop layer is silicon nitride (SiN) or titanium nitride (TiN).
It should be noted that, in an embodiment of the present invention, also comprise: before forming the dummy grid film, form the described Semiconductor substrate 200 gate dielectric membrane (not shown) that cover first area I and second area II, described gate dielectric membrane is in the processing step of follow-up formation the first dummy gate structure 205 and the second dummy gate structure 207, formation is positioned at the first grid dielectric layer 209 on Semiconductor substrate 200 surfaces of first area I, and the second gate dielectric layer 211 on Semiconductor substrate 200 surfaces of second area II.For the performance of the CMOS pipe that improves follow-up formation, the material of described first grid dielectric layer 209 and second gate dielectric layer 211 is high K dielectric.
It should be noted that, for reducing the interface resistance between each gate dielectric layer and Semiconductor substrate 200, in an embodiment of the present invention, also comprise: before forming gate dielectric membrane, form the interfacial film that covers described Semiconductor substrate 200 surfaces, described interfacial film can be in the processing step of follow-up formation the first dummy gate structure 205 and the second dummy gate structure 207, formation is positioned at first boundary layer 213 on Semiconductor substrate 200 surfaces of first area I, and is positioned at the second contact surface layer 215 on Semiconductor substrate 200 surfaces of second area II.The material of described the first boundary layer 213 and second contact surface layer 215 is silicon oxide layer, or silicon oxynitride layer.Described the first boundary layer 213 is formed between Semiconductor substrate 200 and first grid dielectric layer 209, between described second contact surface layer 215 formation and Semiconductor substrate 200 and second gate dielectric layer 211.
It should be noted that; damage first grid dielectric layer 209 and second gate dielectric layer 211 for avoiding the subsequent etching technical process; also comprise: before forming the dummy grid film; forming the described interfacial film of protective film that covers described gate dielectric membrane can be in the processing step of follow-up formation the first dummy gate structure 205 and the second dummy gate structure 207; formation is positioned at first protective layer 217 on Semiconductor substrate 200 surfaces of first area I, and is positioned at second protective layer 219 on Semiconductor substrate 200 surfaces of second area II.The material of described the first protective layer 217 and the second protective layer 219 is titanium nitride or tantalum nitride or both combinations.Described the first protective layer 217 is formed at described first grid dielectric layer 209 surfaces, and described the second protective layer 219 is formed at described second gate dielectric layer 211 surfaces.
It should be noted that; in other embodiments of the invention; described first grid dielectric layer 209, the first boundary layer 213, the first protective layer 217 also can form successively after follow-up formation the first opening; described second gate dielectric layer 211, second contact surface layer 215, the second protective layer 219 also can form successively after follow-up formation the second opening, do not repeat them here.
Please refer to Fig. 3, remove described the first dummy gate structure, form the first opening 221.
The technique of removing described the first dummy gate structure is etching technics, and for example dry etch process, be well known to those skilled in the art owing to adopting dry etch process to remove described the first dummy gate structure, do not repeat them here.
Described the first opening 221 is for subsequent deposition the first functional layer.Described the first opening 221 runs through the thickness of insulating barrier 203.In an embodiment of the present invention, described the first opening 221 exposes the first protective layer 217 surfaces.
Please refer to Fig. 4, formation is positioned at shown in described first opening 221(Fig. 3) bottom and the first functional layer 223 of sidewall, form the first sacrifice layer 225, the surface of described the first sacrifice layer 225 and described insulating barrier 203 flush that cover described the first functional layer 223.
Described the first functional layer 223 is positioned at bottom and the sidewall of described the first opening 221, for the work function of the semiconductor device of follow-up adjustment first area I.The formation technique of described the first functional layer 223 is depositing operation, for example physics or chemical vapour deposition (CVD).
The material of described the first functional layer 223 is one or more combinations in titanium nitride, tantalum, tantalum nitride, titanium aluminide, titanium, cobalt or nickel.In an embodiment of the present invention, described the first functional layer 223 is for adjusting the work function of PMOS pipe, and to obtain higher threshold voltage, the material of described the first functional layer 223 is tantalum.
Described the first sacrifice layer 225 is not for being damaged in subsequent technique protection the first functional layer 223.Described the first sacrifice layer 225 is positioned at the first functional layer 223 surfaces of described the first opening 221, and with described insulating barrier 203 flush.The formation technique of described the first sacrifice layer 225 is depositing operation, for example physics or chemical deposition process.In an embodiment of the present invention, the formation technique of described the first sacrifice layer 225 is chemical vapor deposition method, for the quality of the first sacrifice layer 225 of making to form is good, and follow-uply more easily is removed, and the power of described chemical vapor deposition method is less than 400 watts.
In an embodiment of the present invention, the formation step of described the first sacrifice layer 225 and described the first functional layer 223 comprises: form the bottom of described the first opening 221 of covering and the first function film (not shown) on sidewall and insulating barrier 203 surfaces; Form the first sacrificial film (not shown) that covers described the first function film; Described the first sacrificial film of chemico-mechanical polishing and the first function film, until expose insulating barrier 203 surface and the second dummy gate structure 207 surfaces.Described the first sacrifice layer 225 and described the first functional layer 223 form in same chemical-mechanical polishing step, have saved processing step.
The inventor finds, material selection rotary coating glass (spin-on-glass when described the first sacrifice layer 225, SOG) time, during the first sacrifice layer 225 that the described material of subsequent chemical-mechanical polishing is rotary coating glass, the speed of the described insulating barrier 203 of polishing is greater than the speed of the described rotary coating glass of polishing, after polishing finishes, the thickness of described insulating barrier 203 is less than the thickness of the first sacrifice layer 225 that material is rotary coating glass, easily cause the thickness of the first grid electrode layer of follow-up formation to reduce, affect the stability of CMOS pipe.
Through research, the inventor finds, when the polishing speed when described the first sacrifice layer 225 is selected chemico-mechanical polishing is greater than the material of polishing speed of described insulating barrier 203, can avoid the generation of above-mentioned phenomenon, surface and described insulating barrier 203 flush of described the first sacrifice layer 225 formed, the stable performance of the CMOS pipe of follow-up formation.Therefore, in an embodiment of the present invention, the material of described the first sacrifice layer 225 is polysilicon, polycrystalline silicon germanium or unformed silicon.
Please refer to Fig. 5, remove described the second dummy gate structure, form the second opening 227.
The technique of removing described the second dummy gate structure is etching technics, for example dry etch process or wet-etching technology.In an example of the present invention, when the material of described the first sacrifice layer 225 is poly-SiGe, adopt Tetramethylammonium hydroxide (TMAH) or NaOH (NaOH) as chemical reagent, the speed of the described poly-SiGe of wet etching is less than the speed of etching the second dummy gate structure, after forming the first sacrificial film, directly adopt wet etching to remove the first sacrificial film and the second dummy gate structure of first area I, form the first sacrifice layer 225 and the second opening 227 simultaneously.
Described the second opening 227 is for subsequent deposition the second functional layer.Described the second opening 227 runs through the thickness of insulating barrier 203.In an embodiment of the present invention, described the second opening 227 exposes the second protective layer 219 surfaces.
After above-mentioned steps completes, in the embodiment of the present invention, step S201 is complete.
It should be noted that, in other embodiments of the invention, can also adopt other techniques or method to form the structure shown in step S201, provide and comprise adjacent first area and the Semiconductor substrate of second area, described semiconductor substrate surface is formed with insulating barrier, and described first area has the first opening that runs through described insulating barrier, the bottom of described the first opening and sidewall are formed with the first functional layer, described the first functional layer surface coverage has the first sacrifice layer, described the first sacrifice layer flushes with described surface of insulating layer, described second area has the second opening that runs through described insulating barrier, described the second opening exposes semiconductor substrate surface.Afterwards, execution step S203-step S209.
Please refer to Fig. 6, form the second functional layer 229, the bottom of described the second opening 227 of described the second functional layer 229 covering and sidewall, insulating barrier 203 surface and the first sacrifice layer 225 surfaces.
Described the second functional layer 229 is for the work function of the semiconductor device of follow-up adjustment second area II, and in embodiments of the invention, described the second functional layer 229, for adjusting the work function of NMOS pipe, improves its threshold voltage, improves the stability of CMOS pipe.The formation technique of described the second functional layer 229 is depositing operation, for example physics or chemical vapour deposition (CVD), the bottom of described second opening 227 of the second functional layer 229 covering of formation and sidewall, insulating barrier 203 surface and the first sacrifice layer 225 surfaces.
The inventor finds, while covering the second sacrifice layer that described second functional layer 229 of part on described the first sacrifice layer 225 surfaces can be in follow-up removal the second opening, by etching technics, removes together, without carrying out extra CMP (Chemical Mechanical Polishing) process.And because insulating barrier 203 surface coverage of first area I have the second functional layer 225, during the first sacrifice layer 225 in described the first opening of follow-up removal, what the insulating barrier 203 of described first area I was removed is less, significant change can not occur in the thickness of described insulating barrier 203, is conducive to the follow-up formation actual height gate electrode layer identical with design height.
The material of described the second functional layer 229 is one or more combinations in titanium nitride, tantalum, tantalum nitride, titanium aluminide, titanium, cobalt or nickel, but the material of described the second functional layer 229 is different from the material of described the first functional layer 223.In an embodiment of the present invention, the structure that described the second functional layer 229 is multiple-level stack, the material of described stacked structure is cobalt and titanium nitride.
Please refer to Fig. 7, form the second sacrifice layer 231, insulating barrier 203 and the second functional layer 229 that described the second sacrifice layer 231 covers in second area II.
The inventor finds, if at first described the second sacrifice layer 231 of chemico-mechanical polishing and the second functional layer 229, insulating barrier 203 to be exposed, behind the first sacrifice layer 225 surfaces, again the first sacrifice layer 225 and the second sacrifice layer 231 laid respectively in the first opening and the second opening carried out to etching, also can carry out etching to insulating barrier 203 during described etching process, make the thickness of insulating barrier 203 reduce, the height of corresponding the first opening and the second opening reduces, fill the first grid electrode layer that forms after metal material and the height of second gate electrode layer also can reduce accordingly to described the first opening and the second opening, be that follow-up actual first grid electrode layer and the second gate electrode layer height formed is less than former design height, thereby affected the performance of PMOS pipe and NMOS pipe, make the unstable properties of the CMOS pipe of formation.
Through research, when making described the second sacrifice layer 231 of follow-up removal, the damage that insulating barrier 203 is subject to is little, described the second sacrifice layer 231 should select its etch rate to be greater than the material of the etch rate of described insulating barrier 203, is beneficial to first grid electrode layer and second gate electrode layer that follow-up formation actual height is consistent with former design height.
In an embodiment of the present invention, in order to simplify technique, no longer on the second functional layer 229 surfaces of first area I, form mask, the material of described the second sacrifice layer 231 is photoresist (PR), can directly adopt exposure, developing technique to form photoresist as the second sacrifice layer 231 on the second functional layer 229 surfaces of described second area II, save processing step.
It should be noted that, in other embodiments of the invention, described the second sacrifice layer 231 can also be the etch rate material identical with the etch rate of the first sacrifice layer 225, when described the second sacrifice layer 231 material that to be other etch rates identical with the etch rate of the first sacrifice layer 225, also comprise: before forming the second sacrifice layer 231, form the second mask layer (not shown), described the second mask layer exposes the second functional layer 229 of second area II.Described the second mask layer can be removed in the lump when the second functional layer 229 of the described first area I of follow-up removal.
Please refer to Fig. 8, at first remove the second functional layer 229 of described first area I, then remove shown in first sacrifice layer 225(Fig. 7), and remove shown in second sacrifice layer 231(Fig. 7 of described second area II), expose the first functional layer 223 in the first opening and the second functional layer 229 of second area II.
Remove the second functional layer 229 of described first area I, its technique is etching technics, dry etch process for example, and the etching gas of employing is fluorine-containing (CF for example
4or C
2f
6) or chloride (Cl
2or BCl
3) gas.
Then remove described the first sacrifice layer 225, the technique of removing described the first sacrifice layer 225 is etching technics, for example dry etch process.While adopting described dry etch process, the etching gas of employing is fluorine-containing (CF for example
4or C
2f
6) or chloride (Cl for example
2or BCl
3) gas, bias power during described etching is less than 200 watts.
The technique of removing described the second sacrifice layer 231 is etching technics or cineration technics.In an embodiment of the present invention, because the material of described the second sacrifice layer 231 is photoresist, the technique of removing described the second sacrifice layer 231 employings is the cineration technics that comprises oxygen, after the second functional layer 229 of described cineration technics described first area I to be removed and the first sacrifice layer 225, carries out.
It should be noted that, when described the second sacrifice layer 231 material that to be etch rate identical with the etch rate of the first sacrifice layer 225, the technique of removing described the second sacrifice layer 231 is etching technics, dry etch process for example, the step of described removal the second sacrifice layer 231 can be carried out with the second functional layer 229 of removing described first area I, the step of the first sacrifice layer 225 simultaneously.When those skilled in the art can make to remove described the first sacrifice layer 225 end by the parameter (such as etching power, etching cavity pressure etc.) of adjusting etching technics, described the second sacrifice layer 231 just in time is removed.When adopting material that etch rate is identical with the etch rate of the first sacrifice layer 225 as the second sacrifice layer 231, the technique of removing described the second sacrifice layer 231 is simple, and can not form oxide film, the stable performance of the final CMOS pipe formed on remaining the second functional layer 229 surfaces.
After executing this step, expose the first interior functional layer 223 of the first opening and the second functional layer 229 of second area II, the second functional layer 229 in described remaining the first functional layer 223 and the second opening is respectively used to regulate the work function of PMOS pipe and NMOS pipe.
Please refer to Fig. 9, form the first grid electrode layer 233 that covers described the first functional layer 223, form the second gate electrode layer 235 that covers described the second functional layer 229, and described first grid electrode layer 233 and second gate electrode layer 235 and described insulating barrier 203 flush.
Described first grid electrode layer 233 is used to form the grid of PMOS pipe, and the formation technique of described first grid electrode layer 233 is depositing operation, for example physics or chemical vapour deposition (CVD).The material of described first grid electrode layer 233 is one or more in W, Cu, Ag, TiN, TaN or TiAl.
Described second gate electrode layer 235 is used to form the grid of NMOS pipe.The formation technique of described second gate electrode layer 235 is depositing operation, for example physics or chemical vapour deposition (CVD).The material of described second gate electrode layer 235 is one or more in W, Cu, Ag, TiN, TaN or TiAl.
In an embodiment of the present invention, for saving processing step, described first grid electrode layer 233 is identical with the material of second gate electrode layer 235, be tungsten (W), described first grid electrode layer 233 and described second gate electrode layer 235 form in same processing step, specifically comprise: form the gate electrode film (not shown) that covers described the first functional layer 223, the second functional layer 229 and insulating barrier 203, the described gate electrode film of chemico-mechanical polishing is until expose insulating barrier 203.
After above-mentioned steps completes, the completing of the CMOS pipe of the embodiment of the present invention.In the CMOS pipe that the embodiment of the present invention forms, the height of each regional gate electrode layer is identical with former design height, the stable performance of CMOS pipe.
In embodiments of the invention; the second functional layer formed is except the bottom and sidewall of the insulating barrier that covers second area, the second opening; also cover insulating barrier and first sacrifice layer of described first area; the second functional layer that covers first area insulating barrier and the first sacrifice layer can protect insulating barrier not suffer a loss in subsequent technique; thereby make the first grid electrode layer of follow-up formation and the height of second gate electrode layer can not reduce; the PMOS pipe formed and the stable performance of NMOS pipe, the stable performance of the final CMOS pipe formed.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. the formation method of a CMOS (Complementary Metal Oxide Semiconductor) pipe, is characterized in that, comprising:
Provide and comprise adjacent first area and the Semiconductor substrate of second area, described semiconductor substrate surface is formed with insulating barrier, and described first area has the first opening that runs through described insulating barrier, the bottom of described the first opening and sidewall are formed with the first functional layer, described the first functional layer surface coverage has the first sacrifice layer, described the first sacrifice layer flushes with described surface of insulating layer, and described second area has the second opening that runs through described insulating barrier;
Form the second functional layer, described the second functional layer covers bottom and sidewall, surface of insulating layer and first sacrificial layer surface of described the second opening;
Form the second sacrifice layer, described the second sacrifice layer covers insulating barrier and the second functional layer in second area;
Remove the second functional layer and first sacrifice layer of described first area, and remove the second sacrifice layer of described second area, expose the first interior functional layer of the first opening and the second functional layer of second area;
After removing the first sacrifice layer and the second sacrifice layer, form to cover the first grid electrode layer of described the first functional layer, form the second gate electrode layer that covers described the second functional layer, and described first grid electrode layer and second gate electrode layer flush with described surface of insulating layer.
2. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that,
The material of described the first functional layer and the second functional layer is one or more combinations in titanium nitride, tantalum, tantalum nitride, titanium aluminide, titanium, cobalt or nickel, and the material of described the first functional layer is different from the material of described the second functional layer.
3. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, polishing speed during described the first sacrifice layer of chemico-mechanical polishing is greater than the polishing speed of described insulating barrier.
4. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the material of described the first sacrifice layer is polysilicon, poly-SiGe or unformed silicon.
5. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the etch rate of described the second sacrifice layer is greater than the etch rate of described insulating barrier.
6. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 5, is characterized in that, the etch rate of described the second sacrifice layer is identical with the etch rate of described the first sacrifice layer.
7. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 5, is characterized in that, the material of described the second sacrifice layer is photoresist, and the method for described the second sacrifice layer of follow-up removal is the cineration technics that comprises oxygen.
8. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the formation technique of described the first sacrifice layer is physics or chemical vapour deposition (CVD).
9. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 8, is characterized in that, the power of described chemical vapour deposition (CVD) is less than 400 watts.
10. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the technique of removing the second sacrifice layer of described second area is dry etch process.
11. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 10, is characterized in that, the etching gas that described dry etch process adopts is fluorine-containing or chloride gas, and the bias power of etching is less than 200 watts.
12. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, also comprise: form first grid dielectric layer and second gate dielectric layer, described first grid dielectric layer is formed between the bottom and the first functional layer of described the first opening, and described second gate dielectric layer is formed between the bottom and the second functional layer of described the second opening.
13. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 12, it is characterized in that, also comprise: form the first boundary layer and second contact surface layer, described the first boundary layer is formed between Semiconductor substrate and first grid dielectric layer, between the formation of described second contact surface layer and Semiconductor substrate and second gate dielectric layer.
14. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 12; it is characterized in that; also comprise: form the first protective layer and the second protective layer; described the first protective layer is formed at described first grid dielectric layer surface, and described the second protective layer is formed at described second gate dielectric layer surface.
15. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 14, is characterized in that, the material of described the first protective layer and the second protective layer is titanium nitride or tantalum nitride or both combinations.
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| CN107092880A (en) * | 2017-04-14 | 2017-08-25 | 杭州士兰微电子股份有限公司 | Ultrasonic fingerprint sensor and its manufacture method |
| CN117577537A (en) * | 2024-01-17 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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| US20070190767A1 (en) * | 2006-02-10 | 2007-08-16 | Tokyo Electron Limited | Semiconductor device and manufacturing method thereof |
| CN102420185A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) |
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| US20070190767A1 (en) * | 2006-02-10 | 2007-08-16 | Tokyo Electron Limited | Semiconductor device and manufacturing method thereof |
| CN102420185A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) |
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| CN107092880A (en) * | 2017-04-14 | 2017-08-25 | 杭州士兰微电子股份有限公司 | Ultrasonic fingerprint sensor and its manufacture method |
| CN117577537A (en) * | 2024-01-17 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117577537B (en) * | 2024-01-17 | 2024-04-30 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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