CN103456680B - The method of hole slot is formed in low K dielectric layer - Google Patents
The method of hole slot is formed in low K dielectric layer Download PDFInfo
- Publication number
- CN103456680B CN103456680B CN201210183531.XA CN201210183531A CN103456680B CN 103456680 B CN103456680 B CN 103456680B CN 201210183531 A CN201210183531 A CN 201210183531A CN 103456680 B CN103456680 B CN 103456680B
- Authority
- CN
- China
- Prior art keywords
- low
- hole slot
- layer
- dielectric layer
- hard mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a kind of method forming hole slot in low K dielectric layer, comprising: Semiconductor substrate is provided; Form low K dielectric layer on the semiconductor substrate; Described low K dielectric layer forms silicon dioxide layer; Described silicon dioxide layer forms hard mask layer; Etch the silicon dioxide layer of described hard mask layer and segment thickness; Perform back carving technology to described hard mask layer, form opening, the sidewall of described opening and the angle of diapire are greater than 90 degree; Etch the silicon dioxide layer in described opening and low K dielectric layer, form hole slot.By after the silicon dioxide layer of etching hard mask layer and segment thickness, also carving technology is performed back to form opening to described hard mask layer, thus, the characteristic that the angle that the opening formed has sidewall and diapire is greater than 90 degree, thus avoid the problem of hard mask layer generation undercutting, improve the porefilling capability of copper electroplating technology, thus the reliability of device that improve semiconductor technology and formed.
Description
Technical field
The present invention relates to field of IC technique, particularly in a kind of low K dielectric layer, form the method for hole slot.
Background technology
At present, semiconductor circuit has developed into the integrated circuit (integratedcircuit, IC) with multilayer interconnection.In the IC of multilayer interconnection, the electric conducting material on interconnection layer needs to carry out electric insulation by the electric conducting material on dielectric layer and another interconnection layer.
But in the IC of single or multiple lift interconnection, all can form electric capacity with between the electric conducting material that dielectric layer is separated, the electric capacity that this interconnection is formed is not required in design process.Speed due to IC is inversely proportional to the interconnection resistance (R) of IC and the product of the electric capacity (C) of interconnection, the product of described RC, namely RC constant must be little as far as possible, to promote suitable Signal transmissions and switching speed, and reduces signal cross-talk as far as possible.Along with the growing requirement to IC more high integration and miniaturization of components, be the RC constant restriction in IC to a key constraints of system speed.Therefore, the resistance and the performance raising of electric capacity to IC that reduce IC interconnection play an important role.
Reducing the method for electric capacity between interconnection layer is use a low K dielectric layer, namely uses low-K material as the rete realizing electric insulation between interconnection layer.Described low-K material is such as: organic polymer, amorphous chlorination carbon, microminiature foamed plastics, include organic polymer Silicon On Insulator, be doped with the Si oxide of carbon and be doped with the Si oxide of chlorine.Wherein, K represents dielectric coefficient, and high and low is for the dielectric coefficient of silicon dioxide, and the dielectric coefficient of described silicon dioxide is generally 3.9.
Usually, metal interconnecting wires is formed in described low K dielectric layer, carries out electrical isolation by described low K dielectric layer.Concrete, described low K dielectric layer is formed a hard mask layer; Described hard mask layer forms opening, exposes described low K dielectric layer; Etch the low K dielectric layer exposed, form hole slot (comprising through hole and/or groove); Metal interconnecting wires is formed in described hole slot.
But; in above-mentioned technique, when utilizing hard mask layer to protect low K dielectric layer to form hole slot, very easily there is the problem of hard mask layer undercutting (undercut); specifically please refer to Fig. 1, it is the device profile schematic diagram after existing technique forms hole slot in low K dielectric layer.As shown in Figure 1, low K dielectric layer 11 is formed with hard mask layer 12; Hole slot 100 is formed in low K dielectric layer 11.But, due to the characteristic (particularly the isotropism of wet-etching technology and corrosive liquid are easy to pierce the characteristic between two retes) of etching technics, bottom described hard mask layer 12 (namely with low K dielectric layer 11 intersection) be formed with otch 101, i.e. the undercutting of hard mask layer.The undercutting of hard mask layer very easily causes hard mask layer 12 warpage, and the connection reliability namely between hard mask layer 12 and low K dielectric layer 11 reduces.And this problem reduces causing the reliability of follow-up series of process, such as, the deposition quality of the rete such as metal interconnecting wires (being mainly same interconnection line), metallic spacer (being mainly copper separator) of follow-up formation is poor, reduces the quality of the device formed the most at last.
Summary of the invention
The object of the present invention is to provide a kind of method forming hole slot in low K dielectric layer, to solve the problem of hard mask layer generation undercutting in existing technique and to improve the porefilling capability of copper electroplating technology.
For solving the problems of the technologies described above, the invention provides a kind of method forming hole slot in low K dielectric layer, comprising:
Semiconductor substrate is provided;
Form low K dielectric layer on the semiconductor substrate;
Described low K dielectric layer forms silicon dioxide layer;
Described silicon dioxide layer forms hard mask layer;
Etch the silicon dioxide layer of described hard mask layer and segment thickness;
Perform back carving technology to described hard mask layer, form opening, the sidewall of described opening and the angle of diapire are greater than 90 degree;
Etch the silicon dioxide layer in described opening and low K dielectric layer, form hole slot.
Optionally, formed in the method for hole slot in described low K dielectric layer, described sidewall comprises the first side wall and is positioned at the second sidewall on described the first side wall, and wherein, the angle of the first side wall and diapire is greater than 90 degree, and the second sidewall is vertical shape.
Optionally, formed in the method for hole slot in described low K dielectric layer, the angle of described the first side wall and diapire is 130 degree ~ 170 degree.
Optionally, formed in the method for hole slot in described low K dielectric layer, in the technique of silicon dioxide layer etching described hard mask layer and segment thickness, the silicon dioxide layer of the segment thickness of etching is 1/10 ~ 1/3 of the thickness of the silicon dioxide layer formed.
Optionally, formed in described low K dielectric layer in the method for hole slot, utilize the silicon dioxide layer of hard mask layer described in dry etching and segment thickness.
Optionally, formed in described low K dielectric layer in the method for hole slot, utilize the mixed liquor of the mixed liquor of salpeter solution or sulfuric acid and hydrogen peroxide or hydrochloric acid and hydrogen peroxide to perform back carving technology to described hard mask layer.
Optionally, formed in described low K dielectric layer in the method for hole slot, utilize silester to form silicon dioxide layer on described low K dielectric layer.
Optionally, formed in the method for hole slot in described low K dielectric layer, the material of described hard mask layer is metal or metallic compound.
Optionally, formed in the method for hole slot in described low K dielectric layer, described hole slot is larger than the cross-sectional width away from hole slot notch near the cross-sectional width of hole slot notch.
Optionally, formed in described low K dielectric layer in the method for hole slot, after formation hole slot, also comprise:
Form metal level, described metal level covers described hard mask layer, filling overflow described hole slot;
Metal level described in planarization, forms metal interconnecting wires.
Formed in low K dielectric layer provided by the invention in the method for hole slot, after the silicon dioxide layer etching hard mask layer and segment thickness, also carving technology is performed back to form opening to described hard mask layer, thus, the characteristic that the angle that the opening formed has sidewall and diapire is greater than 90 degree, thus avoid the problem of hard mask layer generation undercutting, improve the porefilling capability of copper electroplating technology, thus the reliability of device that improve semiconductor technology and formed.
Accompanying drawing explanation
Fig. 1 is the device profile schematic diagram after existing technique forms hole slot in low K dielectric layer;
Fig. 2 is the schematic flow sheet of the method forming hole slot in the low K dielectric layer of the embodiment of the present invention;
Fig. 3 a ~ 3g is the generalized section of each step device in the method forming hole slot in the low K dielectric layer of the embodiment of the present invention;
Fig. 4 is the device profile schematic diagram after forming metal interconnecting wires in the hole slot formed in the embodiment of the present invention.
Embodiment
The method forming hole slot in the low K dielectric layer proposed the present invention below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, it is the schematic flow sheet of the method forming hole slot in the low K dielectric layer of the embodiment of the present invention.As shown in Figure 2, the method forming hole slot in described low K dielectric layer comprises the steps:
S20: Semiconductor substrate is provided;
S21: form low K dielectric layer on the semiconductor substrate;
S22: form silicon dioxide layer on described low K dielectric layer;
S23: form hard mask layer on described silicon dioxide layer;
S24: the silicon dioxide layer etching described hard mask layer and segment thickness;
S25: carving technology is performed back to described hard mask layer, form opening, the sidewall of described opening and the angle of diapire are greater than 90 degree;
S26: etch the silicon dioxide layer in described opening and low K dielectric layer, forms hole slot.
Concrete, please refer to Fig. 3 a ~ 3g, it is the generalized section of each step device in the method forming hole slot in the low K dielectric layer of the embodiment of the present invention.
As shown in Figure 3 a, Semiconductor substrate 30 is provided, further, described Semiconductor substrate 30 comprises silicon substrate and covers the separator of described silicon substrate and the metal connecting line of lower one deck, further, described silicon substrate is formed with multiple semiconductor device, such as, forms PMOS transistor, nmos pass transistor etc., for illustrating conveniently, in Fig. 3 a and not shown said structure.
Then, as shown in Figure 3 b, described Semiconductor substrate 30 forms low K dielectric layer 31.Described low K dielectric layer 31 is formed by semiconductor technologies such as chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process.Preferably, the material of described low K dielectric layer 31 be organic polymer, amorphous chlorination carbon, microminiature foamed plastics, include organic polymer Silicon On Insulator, be doped with the Si oxide of carbon and be doped with the Si oxide etc. of chlorine.In the present embodiment, the thickness of described low K dielectric layer 31 is 1000 dust ~ 10000 dusts.
Then, as shown in Figure 3 c, described low K dielectric layer 31 forms silicon dioxide layer 32.In the present embodiment, silester (TEOS) is utilized to form described silicon dioxide layer 32.Concrete, plasma enhanced chemical vapor deposition technique (PECVD) can be utilized, in processing chamber, pass into silester and the formation of the oxygen-containing gas such as oxygen, ozone.Preferably, the thickness of described silicon dioxide layer 32 is 100 dust ~ 1000 dusts.
As shown in Figure 3 d, described silicon dioxide layer 32 forms hard mask layer 33.Preferably, the material of described hard mask layer 33 is metal or metallic compound, and such as, the material of described hard mask layer 33 is titanium, tungsten, titanium nitride, tungsten silicide, titanium silicide etc.Described hard mask layer 33 is formed by depositing operation, such as chemical vapor deposition method, physical gas-phase deposition etc.Preferably, the thickness of described hard mask layer 33 is 100 dust ~ 1000 dusts.
Then, as shown in Figure 3 e, etch the silicon dioxide layer 32 of described hard mask layer 33 and segment thickness, namely initial openings 300 ' is formed in this step (at this, this opening 300 ' is not the final opening formed, be only a middle transition opening, be therefore called initial openings 300 ').In the present embodiment, the silicon dioxide layer 32 of hard mask layer 33 and segment thickness described in dry etching can be utilized.Preferably, the silicon dioxide layer of the segment thickness of etching is 1/10 ~ 1/3 of the thickness of the silicon dioxide layer formed.In the present embodiment, the thickness of the silicon dioxide layer 32 of etching is 50 dust ~ 350 dusts, and (certainly, the thickness of the silicon dioxide layer 32 now formed is greater than 100 dusts for such as 50 dusts, 100 dusts, such as 300 dusts, 500 dusts etc.), 200 dusts, 300 dusts, 350 dusts etc.Namely by after this step process, in the silicon dioxide layer 32 formed in step S22, the silicon dioxide layer of segment thickness has been etched; The silicon dioxide layer of segment thickness is still retained, and covers low K dielectric layer 31.
Then, as illustrated in figure 3f, carving technology is performed back to described hard mask layer 33, form opening 300 (namely on the basis of initial openings 300 ', proceed PROCESS FOR TREATMENT, obtain final opening 300), the described sidewall of opening 300 and the included angle A of diapire are greater than 90 degree.Preferably, salpeter solution is utilized; The mixed liquor of sulfuric acid and hydrogen peroxide; The corrosive liquids such as the mixed liquor of hydrochloric acid and hydrogen peroxide perform back carving technology to described hard mask layer 33.
Concrete, the sidewall of described opening 300 comprises the first side wall 3001 and is positioned at the second sidewall 3002 on described the first side wall 3001, wherein, being made up of silicon dioxide layer 32 of described the first side wall, described second sidewall 3002 is made up of hard mask layer 33, at this, described the first side wall 3001 is greater than 90 degree with the angle α of diapire 3003, and described second sidewall 300 is vertical shape.Preferably, described the first side wall 3001 is 130 degree ~ 170 degree with the angle of diapire 3003, such as 140 degree, 150 degree, 160 degree etc.
At this, optimizing the shape of hard mask layer 33 etched surface (i.e. the second sidewall 3002) by returning carving technology further, making the etched surface of hard mask layer 33 be vertical shape.Simultaneously, because this step returns carving technology, make the etched surface (i.e. the first side wall 3001) of the silicon dioxide layer 32 (namely through the silicon dioxide layer of etching technics) of segment thickness in skewed, namely with the diapire of opening 300, there is the angle being greater than 90 degree.Thus, the structure (comprising hard mask layer 33 and the silicon dioxide layer 32 through etching technics) as mask has small outward extending structure in bottom, thus avoids the problem of hard mask layer 33 undercutting.Meanwhile, because this outward extending structure is very tiny, therefore, also can not have a negative impact to the reliability of technique.But owing to avoiding the problem of hard mask layer 33 undercutting, avoid the problem of hard mask layer 33 warpage, and improve the porefilling capability of subsequent copper electroplating technology, improve the reliability of follow-up formed rete, namely make follow-up formed rete can fit tightly with other rete, thus ensure quality of forming film.
Then, as shown in figure 3g, etch the silicon dioxide layer 32 in described opening 300 and low K dielectric layer 31, form hole slot 301.Described hole slot 301 comprises through hole and/or groove, and it can be formed through single Damascus technics, also can be formed through dual damascene process.When needs perform dual damascene process, can form a photoresist layer, described photoresist layer covers described opening 300 and hard mask layer 33; Then, graphical described photoresist layer is to form groove opening; Then the groove in etching groove opening; Then peel off described patterned photoresist layer, expose opening 300; Then silicon dioxide layer 32 in described opening 300 is etched and low K dielectric layer 31 forms through hole.
At this, described hole slot 301 near the cross-sectional width of hole slot notch than away from the cross-sectional width of hole slot notch, common, the distance between the two opposite side walls formed with hard mask layer 33 and silicon dioxide layer 22 is greater than the distance between the two opposite side walls that formed with low K dielectric layer 31.
Finally, as shown in Figure 4, after the described hole slot 301 of formation, just can fill described hole slot 301 and form metal interconnecting wires 302 (usually, utilizing copper electroplating technology to form copper interconnecting line).Concrete, first can form metal level, described metal level covers described hard mask layer 33, fills and overflows described hole slot 301; Then metal level described in planarization, removes partial metal layers that is on hard mask layer 33 and that overflow described hole slot 301, forms metal interconnecting wires.Wherein, the depositing operation such as chemical vapor deposition method, physical gas-phase deposition is usually utilized to form described metal level.
At this, because the hole slot 301 formed by the embodiment of the present invention has upper wider, that bottom is narrower characteristic, thus, be beneficial to very much the deposition of metal level, the better metal level of film quality can be formed into, the reliability of semiconductor device improving further semiconductor technology and formed.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (10)
1. form a method for hole slot in low K dielectric layer, it is characterized in that, comprising:
Semiconductor substrate is provided;
Form low K dielectric layer on the semiconductor substrate;
Described low K dielectric layer forms silicon dioxide layer;
Described silicon dioxide layer forms hard mask layer;
Etch the silicon dioxide layer of described hard mask layer and segment thickness, form initial openings;
Adopt wet etching to perform back carving technology to described initial openings, optimize the etched surface of hard mask layer, avoid hard mask layer undercutting, form opening, the sidewall of described opening and the angle of diapire are greater than 90 degree;
Etch the silicon dioxide layer in described opening and low K dielectric layer, form hole slot.
2. form the method for hole slot in low K dielectric layer as claimed in claim 1, it is characterized in that, described sidewall comprises the first side wall and is positioned at the second sidewall on described the first side wall, and wherein, the angle of the first side wall and diapire is greater than 90 degree, and the second sidewall is vertical shape.
3. form the method for hole slot in low K dielectric layer as claimed in claim 2, it is characterized in that, the angle of described the first side wall and diapire is 130 degree ~ 170 degree.
4. in low K dielectric layer as claimed in claim 1, form the method for hole slot, it is characterized in that, in the technique of silicon dioxide layer etching described hard mask layer and segment thickness, the silicon dioxide layer of the segment thickness of etching is 1/10 ~ 1/3 of the thickness of the silicon dioxide layer formed.
5. form the method for hole slot in low K dielectric layer as claimed in claim 1, it is characterized in that, utilize the silicon dioxide layer of hard mask layer described in dry etching and segment thickness.
6. form the method for hole slot in low K dielectric layer as claimed in claim 1, it is characterized in that, utilize the mixed liquor of the mixed liquor of salpeter solution or sulfuric acid and hydrogen peroxide or hydrochloric acid and hydrogen peroxide to perform back carving technology to described hard mask layer.
7. form the method for hole slot in the low K dielectric layer as described in any one in claim 1 to 6, it is characterized in that, utilize silester to form silicon dioxide layer on described low K dielectric layer.
8. form the method for hole slot in the low K dielectric layer as described in any one in claim 1 to 6, it is characterized in that, the material of described hard mask layer is metal or metallic compound.
9. form the method for hole slot in the low K dielectric layer as described in any one in claim 1 to 6, it is characterized in that, described hole slot is larger than the cross-sectional width away from hole slot notch near the cross-sectional width of hole slot notch.
10. form the method for hole slot in the low K dielectric layer as described in any one in claim 1 to 6, it is characterized in that, after formation hole slot, also comprise:
Form metal level, described metal level covers described hard mask layer, filling overflow described hole slot;
Metal level described in planarization, forms metal interconnecting wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210183531.XA CN103456680B (en) | 2012-06-05 | 2012-06-05 | The method of hole slot is formed in low K dielectric layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210183531.XA CN103456680B (en) | 2012-06-05 | 2012-06-05 | The method of hole slot is formed in low K dielectric layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103456680A CN103456680A (en) | 2013-12-18 |
| CN103456680B true CN103456680B (en) | 2015-11-25 |
Family
ID=49738909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210183531.XA Active CN103456680B (en) | 2012-06-05 | 2012-06-05 | The method of hole slot is formed in low K dielectric layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103456680B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979269A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| US10861705B2 (en) * | 2017-08-31 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of line wiggling |
| CN110211920A (en) * | 2018-02-28 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
| CN100477159C (en) * | 2005-11-28 | 2009-04-08 | 海力士半导体有限公司 | Method for forming storagenonode contact plug in semiconductor device |
| CN102194738A (en) * | 2010-03-15 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for making contact hole |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3585039B2 (en) * | 2002-03-25 | 2004-11-04 | 株式会社半導体先端テクノロジーズ | Hole forming method |
| JP2005109138A (en) * | 2003-09-30 | 2005-04-21 | Matsushita Electric Ind Co Ltd | Manufacturing method for semiconductor device |
-
2012
- 2012-06-05 CN CN201210183531.XA patent/CN103456680B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
| CN100477159C (en) * | 2005-11-28 | 2009-04-08 | 海力士半导体有限公司 | Method for forming storagenonode contact plug in semiconductor device |
| CN102194738A (en) * | 2010-03-15 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for making contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103456680A (en) | 2013-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10505018B2 (en) | Spacers with rectangular profile and methods of forming the same | |
| TW201349411A (en) | Semiconductor device and method of manufacturing the same | |
| CN105575887B (en) | The forming method of interconnection structure | |
| TWI713147B (en) | Method for manufacturing semiconductor device | |
| US20140084472A1 (en) | Compound dielectric anti-copper-diffusion barrier layer for copper connection and manufacturing method thereof | |
| CN102324400A (en) | Method for manufacturing copper interconnection structure | |
| US20080280436A1 (en) | Method for fabricating an inductor structure or a dual damascene structure | |
| CN104681403A (en) | Semiconductor and forming method thereof | |
| TW201941362A (en) | Method of fabricating integrated circuit device | |
| US9099445B2 (en) | Electronic device including interconnects with a cavity therebetween and a process of forming the same | |
| CN103456680B (en) | The method of hole slot is formed in low K dielectric layer | |
| JP5407340B2 (en) | Wiring formation method | |
| CN105448814A (en) | Method of forming semiconductor structure | |
| CN107680932B (en) | Interconnect structure and method of making the same | |
| JP2009176819A (en) | Semiconductor device and manufacturing method thereof | |
| WO2023000481A1 (en) | Semiconductor structure and method for forming same, and memory | |
| CN101996929B (en) | Forming method of dual-damascene structure and semiconductor structure | |
| KR20090036879A (en) | Method of manufacturing semiconductor device | |
| TW202303849A (en) | Integrated chip | |
| CN104979269A (en) | Manufacturing method for semiconductor device | |
| US7341955B2 (en) | Method for fabricating semiconductor device | |
| KR20140081168A (en) | Method of manufacturing a phase-change memory device | |
| JP2011119437A (en) | Method of dry-etching insulating film on molybdenum-based metal film, and method of manufacturing thin-film transistor panel | |
| WO2014115790A1 (en) | Semiconductor device and method for manufacturing same | |
| CN111446204B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |