CN103456642B - The method and apparatus manufacturing field-effect transistor - Google Patents

Abstract

The method and apparatus that the present invention relates to manufacture field-effect transistor.Describe a kind of method for manufacturing dual-epi FinFETs.The method includes adding the first epitaxial material to fin array.The method also includes using the first masking material cover at least Part I of fin array and remove the first epitaxial material from the uncovered part of fin array.The method includes that the fin in the uncovered part of fin array adds the second epitaxial material.The method also includes the Part II using the second masking material to cover fin array, and uses the first masking material and the second masking material to be oriented etching.Also illustrate equipment and computer program.

Description

The method and apparatus manufacturing field-effect transistor

Technical field

The exemplary embodiment of the present invention is usually directed to field-effect transistor (FET), more particularly, to double extensions FET.

Background technology

This part aims to provide background or context.Description herein can include being pursued but need not to be the most Through expecting or pursuing the concept arrived.Therefore, unless otherwise indicated herein, the content described in this part is not saying of the application Bright book and the prior art of claims and be not recognized as prior art owing to being included in this part.

Cost that semiconductor and IC chip constantly reduces due to it and the size of reduction in a lot of products Become universal.In the industry of microelectronics industry and other structure relating to microstructure (such as micro-machine, magnetoresistive head), Expectation always reduces architectural feature and the size of microelectronic component and/or provides more substantial circuit for given chip size. Generally, miniaturization allow have under lower power level and lower cost enhancing performance (per clock cycle more process with And produce less heat).Current technology is at or approximately at some micro element former of such as gate, FET and capacitor Sub-level yardstick.The circuit chip with several hundred million this device is not uncommon.Further size reduce seem close to trace and The physics limit of micro element, described trace and micro element are embedded in their Semiconductor substrate and are positioned at described substrate.

Summary of the invention

In an illustrative aspects, a kind of method includes adding the first epitaxial material to fin array.The method is also wrapped Include and use the first masking material cover at least Part I of fin array and remove from the uncovered part of fin array Remove the first epitaxial material.The method includes that the fin in the uncovered part of fin array adds the second extension material Material.The method also includes using the second masking material to cover the Part II of fin array, and use the first masking material and Second masking material is oriented etching.

In a further exemplary embodiment, a kind of equipment includes processor and the memorizer of storage programmed instruction.Described deposit Reservoir and programmed instruction are configured to together with processor make described equipment execution action.Described action includes adding to fin array Add the first epitaxial material.Described action also include using the first masking material cover fin array at least Part I and from The uncovered part of fin array removes the first epitaxial material.It is uncovered that described action includes to fin array Fin in part adds the second epitaxial material.Described action also includes use the second masking material to cover fin array second Part, and use the first masking material and the second masking material to be oriented etching.

In a further exemplary embodiment, a kind of computer program includes comprising on a tangible computer-readable medium Programmed instruction, the execution of described programmed instruction cause operation.Described operation includes adding the first epitaxial material to fin array. Described operation also include using the first masking material cover fin array at least Part I and from fin array not by The part covered removes the first epitaxial material.Described operation includes that the fin in the uncovered part of fin array adds Add the second epitaxial material.Described operation also includes the Part II using the second masking material to cover fin array, and uses First masking material and the second masking material are oriented etching.

In another illustrative aspects, a kind of equipment includes the dress for adding the first epitaxial material to fin array Put.This equipment also includes the device of at least Part I using the first masking material to cover fin array and for from fin The uncovered part of array removes the device of the first epitaxial material.It is uncovered that described equipment includes to fin array Part in fin add the device of the second epitaxial material.This equipment also includes using the second masking material to cover fin array The device of Part II, and use the first masking material and the second masking material to be oriented the device of etching.

Accompanying drawing explanation

When read in conjunction with the accompanying drawings, the aforementioned and other side detailed description below of exemplary embodiment becomes more Add it is clear that in the accompanying drawings:

Figure 1A and 1B being referred to as Fig. 1 shows the top view (figure of the fin FET manufactured according to an exemplary embodiment 1A) with sectional view (Figure 1B).

Fig. 2 A and 2B being referred to as Fig. 2 shows according to an exemplary embodiment described fin during the fabrication stage The top view (Fig. 2 A) of FET and sectional view (Fig. 2 B).

Be referred to as Fig. 3 A and 3B of Fig. 3 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 3 A) of fin FET and sectional view (Fig. 3 B).

Be referred to as Fig. 4 A and 4B of Fig. 4 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 4 A) of fin FET and sectional view (Fig. 4 B).

Be referred to as Fig. 5 A and 5B of Fig. 5 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 5 A) of fin FET and sectional view (Fig. 5 B).

Be referred to as Fig. 6 A and 6B of Fig. 6 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 6 A) of fin FET and sectional view (Fig. 6 B).

Be referred to as Fig. 7 A and 7B of Fig. 7 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 7 A) of fin FET and sectional view (Fig. 7 B).

Be referred to as Fig. 8 A and 8B of Fig. 8 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 8 A) of fin FET and sectional view (Fig. 8 B).

Be referred to as Fig. 9 A and 9B of Fig. 9 show according to an exemplary embodiment during another fabrication stage described The top view (Fig. 9 A) of fin FET and sectional view (Fig. 9 B).

Figure 10 shows the simplified block diagram of the exemplary electronic device being applicable to put into practice each exemplary embodiment.

Figure 11 show the operation of the illustrative methods according to each exemplary embodiment and be included in computer can The logical flow chart of the execution result of the computer program instructions in reading memorizer.

Figure 12 A and 12B being referred to as Figure 12 showed according to an exemplary embodiment alternative phase fabrication stage Between the top view (Fig. 3 A) of described fin FET and sectional view (Fig. 3 B).

Detailed description of the invention

Abbreviation below may finding in description and/or accompanying drawing is defined below:

The SiGe of B-SiGe boron-doping

CMOS complementary metal oxide semiconductors (CMOS)

Epi extension/extension

FET field-effect transistor

HCl hydrogen chloride

MOS metal-oxide semiconductor (MOS)

NFET n type FET

PFET p type FET

SIT sidewall image transfer

SOI silicon-on-insulator

Field-effect transistor (FET) is the transistor with source electrode, grid and drain electrode.Most load is depended in the behavior of FET Stream is along the flowing of the raceway groove between the source electrode and drain electrode of grid of passing through.Flow through the electric current of raceway groove between source electrode and drain electrode Can be controlled by the transverse electric field below grid.

As one of skill in the art will recognize, when gate terminal is in low or negative potential relative to source electrode, p-type FET(PFET) turn on thus allow electric current to flow to drain electrode from source electrode.When grid potential relative to source electrode be just or with source electrode at When identical electromotive force, p-type FET turns off and is not turned on electric current.On the other hand, it is in high relative to source electrode when gate terminal Or during positive potential, N-type FET(NFET) conducting thus allow electric current from source electrode flow to drain electrode.When grid potential relative to source electrode is When bearing or be in identical electromotive force with source electrode, N-type FET turns off and is not turned on electric current.Note, in such cases each In the case of Zhong, all there is the threshold voltage of the work for triggering FET in (such as, at gate terminal).

More than one grid (multiple-grid) can be used more effectively to control raceway groove.The length of grid determines the switch of FET How soon have, and can be roughly the same with the length of raceway groove (such as, the distance between source electrode and drain electrode).Multiple-grid FET is considered It it is the candidate likely of the size reducing complementary metal oxide semiconductors (CMOS) (CMOS) FET technology.But, the least chi Degree needs such as short-channel effect, break-through, metal-oxide (MOS) leakage current and the dead resistance being present in multiple-grid FET Performance issue better control over.

By using one or more fin shape raceway grooves to be successfully reduced the size of FET.Use this raceway groove FET is properly termed as fin FET.In the past, in addition to the FET grid being arranged on raceway groove top, cmos device serves as a contrast along quasiconductor The surface at the end is substantially smooth.Fin makes to be exposed to the largest surface area of the raceway groove of grid by using vertical channel structure Change, broken this example.Grid controls raceway groove more strongly, this is because grid prolongs on more than side (surface) of raceway groove Stretch.Such as, grid can be around on the three of three dimension channel surface rather than the top surface being arranged only at conventional planar raceway groove.

Affect threshold voltage (such as, to increase threshold voltage, different grid lengths promotes more constant threshold value electricity Pressure) a kind of technology be to use, under (one or more) gate edge, the adulterant being locally implanted.This is referred to as " halo (halo) " inject.As limiting examples, halo injects can include arsenic, phosphorus, boron and/or indium.

Silicon-on-insulator (SOI) wafer has been used for developing the monocrystal silicon improving quality, and therefore described monocrystal silicon formed The active layer that body silicon " processes " on the insulator on substrate provides.At other semi-conducting material and the similar structures of alloy thereof In can develop similar attribute.The quality of the improvement of the semi-conducting material of active layer allows transistor and other device to zoom to Minimum size has the good concordance of electrical properties simultaneously.

One exemplary embodiment is to realize last cutting (cut-very-last) place of double extension for fin FET Reason stream.If controlling to be used for NFET and PFET by independent extension, the extension of the fin in source/drain (S/D) region is closed And it is the most challenging.Additionally, the most independent extension controls to need to alleviate any harmful extension between device Short circuit.Contrastingly, this new handling process is that by single mask version of double extension, and solve may be at each device Any extension short circuit occurred between part.

In the process stream of last cutting, illusory fin retains until device manufacture terminates and device manufacture last Stage is cut (after source/drain is formed).But, in conventional fin FET technique, fin is turned by side wall image Move (SIT) to define, and cutting (removing) undesired illusory fin immediately after SIT.Then shape after fin cuts Become the device manufacture of such as grid, spacer, source/drain.

Figure 1A and 1B shows the limiting examples of the fin FET manufactured according to an exemplary embodiment.At Figure 1A Top view in, NFET110 be shown to have P adulterate Si115.PFET120 has BSiGe125.Grid 102 is layered in fin On FET110,120 tops.

Shown in Figure 1B (sectional view), fin FET 110,120 is positioned on substrate 140.Each fin FET includes cap layers 128. Fin FET 110,120 is regularly spaced apart, wherein PFET120 be adjacent fin FET (or another PFET120 or NFET110) between distance 135 be the distance between fin pitch 130(or the adjacent fin of NFET110) twice.

Fig. 2 A and 2B shows according to exemplary embodiment fin FET 110,120 during a fabrication stage. In this stage, fin 104(will become fin FET 110,120) array be positioned on substrate 140.Grid reactive ion etches (RIE) can be used for guaranteeing that the array of fin 104 is not harmful to chip.Noting, for the regular array of fin 104, fin 104 is equal The even distance (or fin pitch) 130 being spaced apart such that between adjacent fin is all identical for all fins 104.

Fig. 3 A and 3B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.In this stage, add the first epitaxial material (BSiGe125) to merge all fins 104.

Fig. 4 A and 4B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.Herein, the nitride deposition thing 410 of laminated thin on fin 104 and BSiGe125.This can use in situ (in-situ) Molecule assistant depositing (iRAD) is carried out.

Fig. 5 A and 5B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.In this stage, expose NFET110 region by removing the nitride deposition thing 410 covering these regions.

Fig. 6 A and 6B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.During this stage, remove BSiGe125 from the NFET110 region exposed.As a non-limiting example, BSiGe125 HCl etching can be used to remove.

Fig. 7 A and 7B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.Now, the second epitaxial material (Si-115 of P doping) is added to merge NFET110 fin 104.It is noted that Yangjing outside The stage shown in Fig. 6 and 7 is carried out with single step on platform.

Fig. 8 A and 8B show according to exemplary embodiment fin FET 110 during another fabrication stage, 120.Defining source region by adding masking material 810, masking material 810 by some fins of protection, do not protect and be not desired to by this mask The illusory fin wanted.

Fig. 9 shows according to exemplary embodiment fin FET 110,120 during another fabrication stage.? In this stage, use shown in masking material 810(Fig. 8 A and 8B) and nitride deposition thing 410 be oriented as masking material Etching (cutting).So remove the Si115 of BSiGe125, P doping of non-active and fin 104 that some are the most masked.Should Etching also removes masking material 810 and the most masked nitride deposition thing 410.This cutting can also (or can not) remove A part for substrate 140.

Note, in a further exemplary embodiment, fin FET 110,120 may be configured so that PFET120 position and The position switching of NFET110.Correspondingly, epitaxial material (Si115 of such as BSiGe125 and P doping) can also switch, and shelters Material (masking material 810 and nitride deposition thing 410) also has adjoint change.

The epitaxial material Si115 of doping (BSiGe125 and P) can be suitable for local technical environment any kind of outside Prolong material, and any suitable technology implementation can be used.Similarly, masking material (masking material 810 and nitride deposition Thing 410) can be any kind of masking material being suitable for local technical environment, and any suitable technology can be used real Execute.

Figure 12 A and 12B shows according to exemplary embodiment fin during an alternative fabrication stage FET110、120.This stage, by replacing the stage shown in Fig. 3 A and 3B, in this stage, adds the first epitaxial material to fin 104 (BSiGe125).Although epitaxial growth be enough on fin carry out, but this epitaxial material the most physically merges fin.

In another embodiment, additional spacer material can be added with the grid covered and isolation retains after dicing " illusory " raceway groove below pole.These raceway groove undoped p and invisible from parasitic angle.

By performing cutting finally, this achieves the consistent gate profile (profile) on all fins and extends. Correspondingly, the voltage threshold (Vt) dependency to width is improved.

Exemplary last cutting technique solves the undesirable extension short circuit between device and grid line end (line-end) winding, especially SRAM.This last cutting method uses illusory/sacrifice fin.These illusory fins are arranged Transition position (border between N-FET and P-FET) at each N to P.Therefore, (PU), going down are pulled up in sram (pass-down) interval and between transmission gate (pass-gate) device is 2 × fin pitch.

Si115 for Si, the P doping of NFET extension area/P doping can be thick；But, horizontal HCl etching provides Small end-component influences.Additionally, the total spacer increase for S/D is probably reason.

The simplification frame of various electronic installations and the equipment being applicable to practical example embodiment is shown with reference to Figure 10, Figure 10 Figure.Such as, computer 1010 can be used for controlling photoetching process according to exemplary embodiment.

Computer 1010 includes that such as computer or the controller 1014 of data processor (DP) and storage computer refer to Make the computer-readable recording medium 1016 being presented as memorizer (MEM) of program (PROG) 1018.

Assuming that PROG1018 includes such programmed instruction, this programmed instruction is when being performed by the DP1014 that is associated so that This equipment works according to exemplary embodiment, and this will be described in more detail below.

That is, each exemplary embodiment can be at least partially by the computer that can be performed by the DP1014 of computer 1010 Software, implement by hardware or by the combination (and firmware) of software and hardware.

Computer 1010 can also include application specific processor, such as photoetching controller 1015.

Computer-readable MEM1016 can be adapted for any type of local technical environment and can use any suitably Data storage technology realize, described data storage technology e.g. based on quasiconductor storage device, flash memory, magnetic storage fill Put and system, optical storage and system, read-only storage and detachable memory.DP1014 can be adapted for local skill Any type of art environment, and the general purpose computer as limiting examples, special-purpose computer, micro-process can be included One or more in device, digital signal processor (DSP) and processor based on polycaryon processor framework.

Described herein and especially with respect to the exemplary embodiment described by illustrative methods, can be in conjunction with can The program storage device (such as, at least one memorizer) read by machine is implemented, described machine visibly embody can by with In the instruction repertorie (such as, program or computer program) that the machine performing operation performs.Described operation includes showing described in utilization The step of example embodiment or the step of described method.

Based on description above, it should it is evident that each exemplary embodiment provides the double extension fin of manufacture The method of FET, equipment and (one or more) computer program.

Figure 11 shows the operation of the method according to exemplary embodiment and computer program instructions (such as The logical flow chart of execution result RPOG1018).According to these exemplary embodiments, method performs outside first at frame 1110 Prolong material and add the step of fin array to.The method performs to use the first masking material to cover described fin array at frame 1120 The step of at least Part I.The uncovered part that the method performs from fin array at frame 1130 removes the first extension The step of material.At frame 1140, the method performs to add the second extension to fin in the uncovered part of fin array The step of material.The method performs to use the step of the Part II of the second masking material described fin array of covering at frame 1150 Suddenly.The method performs the step using the first masking material and the second mask to be oriented etching at frame 1160.

Each frame shown in Figure 11 can be considered as method step and/or be considered as the operation of computer program code and cause Operation and/or be considered as be configured to perform the logic circuit component of multiple couplings of relevant (one or more) function.

Exemplary embodiment provides the method for manufacturing dual-epi FinFETs.The method includes adding to fin array Add the first epitaxial material.The method also includes using the first masking material to cover at least Part I of fin array and from fin The uncovered part of chip arrays removes the first epitaxial material.The method includes the uncovered part to fin array In fin add the second epitaxial material.The method also includes the Part II using the second masking material to cover fin array, And use the first masking material and the second masking material to be oriented etching.

In another exemplary embodiment of said method, the method also includes performing reactive ion etching.

In the above-mentioned methods in the another exemplary embodiment of any one method, the first epitaxial material is that SiGe, in situ B mix Miscellaneous (ISBD) SiGe and/or the SiGe of indium doping.

In the above-mentioned methods in the further example embodiment of any one method, the second epitaxial material be p doping Si or Unadulterated silicon.If using unadulterated silicon, then can the most such as use arsenic that it is doped.

In the above-mentioned methods in the another exemplary embodiment of any one method, the first masking material is nitride deposition Thing, sull, nitrogen oxides (oxy-nitride) film or containing silicon carbonitride film.

In the above-mentioned methods in the further example embodiment of any one method, the second masking material is resist film, has Machine complanation layer, containing ARC and the silicon layer of resist and/or the lamination of multilamellar.

In the above-mentioned methods in the another exemplary embodiment of any one method, the method also includes in response to using first Masking material covers at least Part I of the fin array merged, and removes first from the Part II of the fin array merged and covers Cover material.

In the above-mentioned methods in the further example embodiment of any one method, remove the first epitaxial material and include using HCl etching removes the first extension.

In the above-mentioned methods in the another exemplary embodiment of any one method, hold in a single step on the platform of Yangjing outside Row removes the first epitaxial material and adds the second epitaxial material.

In the above-mentioned methods in the further example embodiment of any one method, perform directional etch and remove in fin array At least one fin.

Another exemplary embodiment provides the equipment for manufacturing dual-epi FinFETs.This equipment includes processor Memorizer with storage programmed instruction.Described memorizer and programmed instruction are configured to together with processor described equipment is performed Action.Described action includes adding the first epitaxial material to fin array.Described action also includes using the first masking material to cover At least Part I of lid fin array and remove the first epitaxial material from the uncovered part of fin array.Described dynamic Work includes that the fin in the uncovered part of fin array adds the second epitaxial material.Described action also includes using Second masking material covers the Part II of fin array, and uses the first masking material and the second masking material to be oriented Etching.

In another exemplary embodiment of the said equipment, described action also includes performing reactive ion etching.

In the said equipment in the another exemplary embodiment of any one equipment, the first epitaxial material is that SiGe, in situ B mix Miscellaneous (ISBD) SiGe and/or the SiGe of indium doping.

In the said equipment in the further example embodiment of any one equipment, the second epitaxial material be p doping Si or Unadulterated silicon.If using unadulterated silicon, then can the most such as use arsenic that it is doped.

In the said equipment in the another exemplary embodiment of any one equipment, the first masking material is nitride deposition Thing, sull, oxynitride film or containing silicon carbonitride film.

In the said equipment in the further example embodiment of any one equipment, the second masking material is resist film, has Machine complanation layer, containing ARC and the silicon layer of resist and/or the lamination of multilamellar.

In the said equipment in the another exemplary embodiment of any one equipment, described action also includes in response to using the One masking material covers at least Part I of the fin array merged, and removes first from the Part II of the fin array merged Masking material.

In the said equipment in the further example embodiment of any one equipment, remove the first epitaxial material and include using HCl etching removes the first extension.

In the said equipment in the another exemplary embodiment of any one equipment, hold in a single step on the platform of Yangjing outside Row removes the first epitaxial material and adds the second epitaxial material.

In the said equipment in the further example embodiment of any one equipment, perform directional etch and remove in fin array At least one fin.

In the said equipment in the another exemplary embodiment of any one equipment, this equipment is included in the integrated electricity of special-purpose Lu Zhong.

In the said equipment in the further example embodiment of any one equipment, this equipment comprises in integrated circuits.

Another exemplary embodiment provides the computer program for manufacturing dual-epi FinFETs.This computer Program product includes the programmed instruction comprised on a tangible computer-readable medium, and the execution of described programmed instruction causes operation. Described operation includes adding the first epitaxial material to fin array.Described operation also includes using the first masking material to cover fin At least Part I of array and remove the first epitaxial material from the uncovered part of fin array.Described operation is wrapped Include the fin in the uncovered part of fin array and add the second epitaxial material.Described operation also includes using second to cover Cover material and cover the Part II of fin array, and use the first masking material and the second masking material to be oriented etching.

In another exemplary embodiment of above computer program product, described operation also includes performing reactive ion Etching.

In the another exemplary embodiment of any one of above computer program product, the first epitaxial material is (ISBD) SiGe and/or the SiGe of indium doping of SiGe, in situ B doping.

In the further example embodiment of any one of above computer program product, the second epitaxial material is p Si or the unadulterated silicon of doping.If using unadulterated silicon, then can the most such as use arsenic that it is mixed Miscellaneous.

In the another exemplary embodiment of any one of above computer program product, the first masking material is nitrogen Compound deposit, sull, oxynitride film or containing silicon carbonitride film.

In the further example embodiment of any one of above computer program product, the second masking material is anti- Lose agent film, Organic planarisation layer, comprise ARC and the silicon layer of resist and/or the stacking of multilamellar.

In the another exemplary embodiment of any one of above computer program product, described operation also includes ringing Should be at least Part I using the first masking material to cover the fin array merged, from second of the fin array merged Divide and remove the first masking material.

In the further example embodiment of any one of above computer program product, remove the first epitaxial material The first extension is removed including using HCl etching.

In the another exemplary embodiment of any one of above computer program product, outside at list on the platform of Yangjing Individual step performs remove the first epitaxial material and add the second epitaxial material.

In the further example embodiment of any one of above computer program product, perform directional etch and remove At least one fin in fin array.

In the another exemplary embodiment of any one of above computer program product, computer-readable medium is Non-emporary computer-readable medium (such as, CD-ROM, RAM, flash memory etc.).

In the further example embodiment of any one of above computer program product, computer-readable medium is Storage medium.

Another exemplary embodiment provides the equipment for manufacturing dual-epi FinFETs.This equipment includes to fin Array adds the device of the first epitaxial material.This equipment also includes use the first masking material to cover fin array at least the first The device of part and for removing the device of the first epitaxial material from the uncovered part of fin array.In described equipment The device of the second epitaxial material is added including the fin in the uncovered part to fin array.This equipment also includes using Second masking material covers the device of the Part II of fin array, and uses the first masking material and the second masking material to enter The device of row directional etch.

In another exemplary embodiment of the said equipment, described equipment also includes the dress performing reactive ion etching Put.

In the said equipment in the another exemplary embodiment of any one equipment, the first epitaxial material is that SiGe, in situ B mix Miscellaneous (ISBD) SiGe and/or indium-doped SiGe.

In the said equipment in the further example embodiment of any one equipment, the second epitaxial material be p doping Si or Unadulterated silicon.If using unadulterated silicon, then can the most such as use arsenic that it is doped.

In the said equipment in the another exemplary embodiment of any one equipment, the first masking material is nitride deposition Thing, sull, oxynitride film or containing silicon carbonitride film.

In the said equipment in the further example embodiment of any one equipment, the second masking material is resist film, has Machine complanation layer, comprise ARC and the silicon layer of resist and/or the lamination of multilamellar.

In the said equipment in the another exemplary embodiment of any one equipment, this equipment also includes in response to using first Masking material covers at least Part I of the fin array merged, covers from the Part II removing first of the fin array merged Cover the device of material.

In the said equipment in the further example embodiment of any one equipment, for removing the device of the first epitaxial material Including the device using HCl etching to remove the first extension.

In the said equipment in the another exemplary embodiment of any one equipment, wherein for removing the first epitaxial material Device and be configured to operate in a single step on the platform of Yangjing outside for adding the device of the second epitaxial material.

In the said equipment in the further example embodiment of any one equipment, perform directional etch and remove in fin array At least one fin.

Any use of term " connection ", " coupling " or its modification it should be understood that between identified element Any this connection or coupling, directly or indirectly.As limiting examples, one or more intermediary element is permissible It is present between " coupling " element.As limiting examples, the element identified according to described exemplary embodiment Between connection or coupling can be physics, electricity, magnetic, logic or they any appropriately combined.As non- Limitative examples, described connection or coupling can include one or more printing electrical connection, wiring, cable, medium or it is any Suitable combination.

Generally, each exemplary embodiment can different medium (such as software, hardware, logic, special circuit or its Any combination) middle enforcement.As limiting examples, some aspects can be real with the software that can run on the computing device Execute, and other aspects can be implemented with hardware.

Description above by exemplary non-limiting example provide that inventor is presently contemplated that each for performing Plant the best approach of exemplary embodiment and the complete of equipment and the description of abundant information.But, when combining accompanying drawing and appended power When profit claim is read, it is contemplated that description above, various amendments and adjustment may for those skilled in the relevant art It is apparent from.But, all this and similar amendments will fall in the range of the teaching of exemplary embodiment.

Furthermore, it is possible to be advantageously employed some features of preferred embodiment and use further feature the most accordingly.Therefore, front The description in face should be understood to only to the explanation of principle rather than limitation ot it.

Claims (19)

1. the method manufacturing field-effect transistor, including:

The first epitaxial material is added to fin array；

The first masking material is used to cover at least Part I of described fin array；

Described first epitaxial material is removed from the uncovered part of described fin array；

Fin in the described uncovered part of described fin array adds the second epitaxial material；

The second masking material is used to cover the Part II of described fin array；And

Described first masking material and described second masking material is used to be oriented etching.

Method the most according to claim 1, farther includes to perform reactive ion etching.

Method the most according to claim 1, wherein said first epitaxial material is that one of following material: SiGe, in situ B mix Miscellaneous SiGe and the SiGe of indium doping.

Method the most according to claim 1, wherein said second epitaxial material be p doping Si or unadulterated silicon it One.

Method the most according to claim 1, wherein said second epitaxial material is unadulterated silicon, and described method is entered One step includes: in response to carrying out described directional etch, is doped described unadulterated silicon.

Method the most according to claim 1, wherein said first masking material is one of following material: nitride deposition Thing, sull, oxynitride film and containing silicon carbonitride film.

Method the most according to claim 1, wherein said second masking material is one of following material: resist film, have Machine complanation layer, comprise ARC and the silicon layer of resist and the lamination of multilamellar.

Method the most according to claim 1, farther includes in response to using described first masking material to cover described fin The most described Part I of chip arrays, removes described first masking material from the Part II of described fin array.

Method the most according to claim 1, wherein removes described first epitaxial material and includes using HCl etching removing described First epitaxial material.

Method the most according to claim 1, performs on the platform of Yangjing to remove outside described first the most outside in a single step Prolong material and add described second epitaxial material.

11. 1 kinds of equipment manufacturing field-effect transistor, including:

It is configured to add the module of the first epitaxial material to fin array；

It is configured to use the module of at least Part I of the first masking material described fin array of covering；

It is configured to the uncovered part from described fin array and removes the module of described first epitaxial material；

The described fin being configured in the uncovered part of described fin array adds the module of the second epitaxial material；

It is configured to use the module of the Part II of the second masking material described fin array of covering；And

It is configured to the module using described first masking material and described second masking material to be oriented etching.

12. equipment according to claim 11, wherein said equipment farther includes the mould being configured to perform reactive ion etching Block.

13. equipment according to claim 11, wherein said first epitaxial material is one of following material: SiGe, in situ B The SiGe and the SiGe of indium doping of doping.

14. equipment according to claim 11, wherein said second epitaxial material be p doping Si or unadulterated silicon it One.

15. equipment according to claim 11, wherein said first masking material is one of following material: nitride deposition Thing, sull, oxynitride film and containing silicon carbonitride film.

16. equipment according to claim 11, wherein said second masking material is one of following material: resist film, Organic planarisation layer, comprise ARC and the silicon layer of resist and the lamination of multilamellar.

17. equipment according to claim 11, wherein said equipment farther includes: be configured to use described One masking material covers the most described Part I of described fin array, removes described from the Part II of described fin array The module of the first masking material.

18. equipment according to claim 11, the module being wherein configured to remove described first epitaxial material includes configuration Become to use HCl etching to remove the module of described first epitaxial material.

19. equipment according to claim 11, are wherein configured to remove module and the configuration of described first epitaxial material The module becoming to add described second epitaxial material is configured to perform in a single step on the platform of Yangjing outside.