CN103430310A - 具有提高的切换速度及提高的交叉控制及增加的输出电压的互补达林顿射极跟随器 - Google Patents

具有提高的切换速度及提高的交叉控制及增加的输出电压的互补达林顿射极跟随器 Download PDF

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CN103430310A
CN103430310A CN2011800614027A CN201180061402A CN103430310A CN 103430310 A CN103430310 A CN 103430310A CN 2011800614027 A CN2011800614027 A CN 2011800614027A CN 201180061402 A CN201180061402 A CN 201180061402A CN 103430310 A CN103430310 A CN 103430310A
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大卫·尼尔·凯西
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Abstract

在一个实施例中，一种设备包括第一晶体管，其中所述第一晶体管的基极耦合到输入端子。提供第二晶体管，其中所述第一晶体管的射极耦合到所述第二晶体管的基极且所述第二晶体管的射极耦合到输出节点。提供第三晶体管，其中所述第三晶体管的基极耦合到输入节点。提供第四晶体管，其中所述第三晶体管的射极耦合到所述第四晶体管的基极且所述第四晶体管的射极耦合到所述输出节点且所述第二晶体管的基极耦合到所述第四晶体管的基极。所述第二晶体管的基极通过短路连结耦合到所述第四晶体管的基极。

Description

具有提高的切换速度及提高的交叉控制及增加的输出电压的互补达林顿射极跟随器
相关申请案的交叉参考
本申请案主张于2010年12月20日申请的"具有中间基极接触的达林顿(Darlingtonwith Intermediate Base Contact)"的第61/424，956号美国临时申请案的优先权，所述案的内容以引用的方式全部并入本文中。
技术领域
背景技术
特定实施例大体上涉及达林顿晶体管配置。
使用呈射极跟随器配置的互补达林顿对具有许多已知限制。具体来说，存储在输出晶体管的基极中的电荷归因于以下事实而限制切换速度:不存在可沿着其迅速移除电荷的低阻抗选路。此外，两个输出晶体管的基极不由低阻抗连结连接，这意味着当一个晶体管基极的状态从"断开"状态改变到"接通"状态时，互补输出晶体管的基极不能保证处于且实际上将不处于相同电势(即，将不同时从其先前存在的"接通"状态改变到"断开"状态)。因此，在交叉时期期间使两个晶体管都接通。这导致从电源流向接地的较高的非所要"贯通"传导电流，从而使效率降级。此外，最大输出电压摆幅不能紧密地接近单一晶体管互补对的最大输出电压摆幅，这是因为每一达林顿在接通时不能具有穿过其集极射极的小于VBE(约0.9V)加上VCESAT(约0.2V)的电压。
发明内容
在一个实施例中，一种设备包括第一晶体管，所述第一晶体管具有基极、射极及集极，其中所述第一晶体管的基极耦合到输入节点。提供第二晶体管，所述第二晶体管具有基极、射极及集极，其中所述第一晶体管的射极耦合到所述第二晶体管的基极且所述第二晶体管的射极耦合到输出节点。提供第三晶体管，所述第三晶体管具有基极、射极及集极，其中所述第三晶体管的基极耦合到输入节点。提供第四晶体管，所述第四晶体管具有基极、射极及集极，其中所述第三晶体管的射极耦合到所述第四具体的基极且所述第四晶体管的射极耦合到输出节点且所述第四晶体管的射极耦合到输出节点且所述第二晶体管的基极耦合到所述第四晶体管的基极。所述第二晶体管的基极通过短路连结耦合到所述第四晶体管的基极。
在一个实施例中，一种方法包括:将第一晶体管耦合到输入节点;将所述第一晶体管耦合到第二晶体管的基极;将所述第二晶体管耦合到输出节点;将第三晶体管耦合到所述输入节点;将所述第三晶体管耦合到第四晶体管的基极;及将所述第四晶体管耦合到输出节点，其中所述第二晶体管的基极通过短路连结耦合到所述第四晶体管的基极。
下列详细描述及附图提供本发明的本质及优势的更好理解。
附图说明
图1描绘根据一个实施例的达林顿晶体管配置的电路。
具体实施方式
本文描述用于达林顿晶体管配置的技术。在下列描述中，出于解释的目的，阐释数种实例及具体细节以提供本发明的实施例的全面理解。如通过所附权利要求书界定的特定实施例可单独包含这些实例中的一些特征或所有特征或结合下文所描述的其它特征，且可进一步包含本文所描述的特征及概念的修改及等效物。
图1描绘根据一个实施例的达林顿晶体管配置的电路100。在一个实施例中，所述达林顿晶体管配置为互补型达林顿射极跟随器对。电路100可用于以高电流增益驱动MOSFET及绝缘栅极双极性晶体管(IGBT)栅极。如展示，电路100包含可视为第一达林顿的第一晶体管Q11IN及第二晶体管Q11OUT。互补型达林顿或射极跟随器可包含晶体管Q12IN及晶体管Q12OUT。在一个实施例中，电路100可为单片达林顿配置。所述单片配置意味着晶体管Q11IN及晶体管Q11OUT可包含于单一裸片中且晶体管Q12IN及晶体管Q12OUT可包含于单一裸片中。两个裸片可包含于单一装置中。此外，应理解，即使描述达林顿配置，但也可使用其它类似配置，例如，三重达林顿或呈达林顿配置的其它多重晶体管配置。此外，达林顿晶体管配置的NPN及PNP变化可改变。
在电路100中，输入耦合到晶体管Q11IN的基极及晶体管Q12IN的基极。此外，输出耦合到晶体管Q11OUT的射极及晶体管Q12OUT的射极。晶体管Q11OUT的射极及晶体管Q12OUT的射极可连接在一起(短接)或保持未经连接(在此情况下存在两个输出节点)。特定实施例在晶体管Q11OUT的基极与晶体管Q12OUT的基极之间添加连结。添加的连结可为提供短路的电线。添加所述连结消除或减少在交叉处浪费的极大的贯通电流。在切换循环的点处(其中晶体管Q11OUT状态正从导通改变成非导通且晶体管Q12OUT正从非导通改变成导通)，晶体管Q11OUT应恰好在晶体管Q12OUT接通的同时断开。然而，由于存储于晶体管Q11OUT的基极中的电荷，晶体管Q11OUT在有限时间内保持为"接通"，在所述有限时间期间晶体管Q12OUT及晶体管Q11OUT两者同时为接通且呈现到接地的非常低电阻路径。在此时间期间，极大的贯通电流从电源流到接地。这些电流浪费能量且降低电路的效率。提供从晶体管Q11OUT的基极到晶体管Q12OUT的射极的短路抑制同时接通两个晶体管的趋势。此外，其提供了用于移除所存储的电荷的非常有效的选路且因此进一步抑制晶体管Q11OUT长时间保持接通而足以允许贯通电流流动的可能性。当晶体管Q12OUT正断开且晶体管Q11OUT正接通时存在相同状况。
此外，电路100提供最高可能切换速度及最高可能轨对轨偏移。所述最高切换速度是由于能用添加的连结使晶体管Q11OUT或晶体管Q12OUT快速放电而引起。此外，断开电压被降低到约0.5V，且此外接通电压在电源Vcc的0.5V之内。断开电压或接通电压常规上将不低于VBE+VCESAT(约0.9V)，其中VBE为基极-射极电压且VCESAT为饱和时的集极-射极电压。这是因为输出晶体管Q11OUT或晶体管Q12OUT的基极需要高于其射极电压约0.7V以使基极电流流动以在其射极-集极电路中产生电流流动。此外，此基极电流是通过输入晶体管Q12IN经由其射极-集极电路供应。在单片或离散的达林顿配置中，输入晶体管Q12IN的集极连接到输出晶体管Q12OUT的集极。因此，晶体管Q12IN的射极(其也为晶体管Q12OUT的基极)与其集极之间的电压差不可小于晶体管Q12IN的VCESAT(比如，0.2V)，否则晶体管Q12IN将无法将所需基极电流传导到晶体管Q12OUT的基极中。鉴于晶体管Q12OUT的射极必须为低于其基极约0.7V且其基极必须为低于其集极0.2V，所以晶体管Q12OUT的集极射极电压在导通时不可小于约0.7V加0.2V，即，(晶体管Q12OUT的)VBESAT加上(晶体管Q12IN的)VCESAT。
可使用电线以将晶体管Q11OUT的基极与晶体管Q12OUT的基极耦合在一起。如需要，所述电线允许修改达林顿的特性。除了所述电线外的额外组件也可与所述电线一起添加或代替所述电线使用。
此外，当使用单片达林顿设计时可提供额外垫使得可添加电线以连结晶体管Q11OUT及晶体管Q12OUT。如果使用单片达林顿设计，那么所述额外垫可不为必需的。所述达林顿可为串接的，其中可提供或可不提供额外垫，使得每一中间基极可连接到或可不连接到额外组件。
在未使用添加的连结的情况下，晶体管Q11OUT及Q12OUT可同时接通。这是因为晶体管Q11OUT的基极及晶体管Q12OUT的基极不具有低电阻选路(通过所述低电阻选路可迅速移除存储于其基极中的电荷)。无论哪个晶体管"接通"均含有大量存储电荷，在其电压将开始改变之前必须移除所述电荷。如果基极偏压差达到1.2V左右，那么两个晶体管Q11OUT及Q12OUT均接通。这引起电流穿过晶体管Q11OUT及Q12OUT从电源Vcc流到接地。这为高寄生电流，其浪费电力。
所述连结引起晶体管Q11OUT的基极及Q12OUT的基极处于相同电压且提供用于迅速移除所存储的基极电荷的选路。因此，晶体管Q11OUT及晶体管Q12OUT未同时接通。因此，极大的寄生电流未从电源Vcc流到接地。
添加的连结也允许达林顿晶体管的切换性能为快速的。所述切换性能可取决于存储于晶体管Q11OUT的基极区域中的电荷。如果晶体管Q11OUT的基极区域为浮动的，那么电荷可消散的时间可限制从接通状态断开晶体管Q11OUT的切换时间。然而，添加的连结允许电荷从基极区域较快消散以断开晶体管Q11OUT。例如，晶体管Q12IN接通，且将晶体管Q11OUT的基极耦合到接地。这使晶体管Q11OUT的基极处的电荷消散以减少断开晶体管Q11OUT的切换时间。透过晶体管Q11IN但在相反方向上对晶体管Q12OUT执行放电。
如本文的描述及遍及所附的权利要求中所使用，除非上下文另外明确指示，否则"一(a)"、"一(an)"及"所述(the)"包含复数参考。此外，如本文的描述及遍及所附的权利要求书中所使用，除非上下文另外明确指示，否则"在...中(in)"的意义包含"在...中(in)"及"在...上(on)"。
上文的描述说明本发明的各种实施例及可如何实施本发明的方面的实例。上文的实例及实施例不应视为唯一实施例，且经呈现以说明如由所附权利要求书界定的本发明的灵活性及优点。基于上文的揭示内容及所附权利要求书，可在不脱离如由权利要求书界定的本发明的范围的情况下使用其它布置、实施例、实施方案及等效物。

Claims (19)

1.一种设备，其包含:
第一晶体管，其具有基极、射极及集极，其中所述第一晶体管耦合到输入节点;
第二晶体管，其具有基极、射极及集极，其中所述第一晶体管耦合到所述第二晶体管的所述基极且所述第二晶体管耦合到输出节点;
第三晶体管，其具有基极、射极端及集极，其中所述第三晶体管耦合到所述输入节点;及
第四晶体管，其具有基极、射极及集极，其中所述第三晶体管耦合到所述第四晶体管的所述基极且所述第四晶体管耦合到所述输出节点，其中所述第二晶体管的所述基极通过短路连结耦合到所述第四晶体管的所述基极。
2.根据权利要求1所述的设备，其中:
所述第一晶体管的所述基极耦合到所述输入节点;
所述第一晶体管的所述射极耦合到所述第二晶体管的所述基极且所述第二晶体管的所述射极耦合到所述输出节点;
所述第三晶体管的所述基极耦合到所述输入节点;且
所述第三晶体管的所述射极耦合到所述第四晶体管的所述基极且所述第四晶体管的所述射极耦合到所述输出。
3.根据权利要求1所述的设备，其中所述短路连结移除存储在第二晶体管或所述第四晶体管的所述基极中的电荷。
4.根据权利要求1所述的设备，其中移除所述电荷致使所述第二晶体管在所述第四晶体管接通时"断开"。
5.根据权利要求1所述的设备，其中当所述第二晶体管或所述第四晶体管断开时所述短路连结使所述第二晶体管或所述第四晶体管放电。
6.根据权利要求1所述的设备，其中所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管为互补达林顿射极跟随器对。
7.根据权利要求1所述的设备，其中所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管以单片达林顿配置形成。
8.根据权利要求7所述的设备，其中所述第一晶体管及所述第二晶体管包括在第一裸片中且所述第三晶体管及所述第四晶体管包括在第二裸片中。
9.根据权利要求1所述的设备，其中所述第一裸片及所述第二裸片包括在单一装置中。
10.根据权利要求1所述的设备，其中所述连结包含电线。
11.根据权利要求1所述的设备，其中所述短路连结包含耦合到额外组件的电线。
12.根据权利要求1所述的设备，其中第二及所述第四晶体管的所述基极归因于所述短路电线而处于相同电压。
13.一种方法，其包含:
将第一晶体管耦合到输入节点;
将所述第一晶体管耦合到第二晶体管的基极;
将所述第二晶体管耦合到输出节点;
将第三晶体管耦合到所述输入节点;
将所述第三晶体管耦合到第四晶体管的基极;及
将所述第四晶体管耦合到输出节点，其中所述第二晶体管的所述基极通过短路连结耦合到所述第四晶体管的所述基极。
14.根据权利要求13所述的方法，其进一步包含:
将所述第一晶体管的所述基极耦合到所述输入节点;
将所述第一晶体管的所述射极耦合到所述第二晶体管的所述基极且将所述第二晶体管的所述射极耦合到所述输出节点;
将所述第三晶体管的所述基极耦合到所述输入节点;及
将所述第三晶体管的所述射极耦合到所述第四晶体管的所述基极且将所述第四晶体管的所述射极耦合到所述输出。
15.根据权利要求13所述的方法，其中其进一步包含移除电荷从而致使所述第二晶体管在所述第四晶体管接通时"断开"。
16.根据权利要求13所述的方法，其中当所述第二或所述第四晶体管断开时所述短路连结使所述第二晶体管或所述第四晶体管放电。
17.根据权利要求13所述的方法，其中所述短路连结包含电线。
18.根据权利要求13所述的方法，其中所述短路连结包含耦合到额外组件的电线。
19.根据权利要求13所述的方法，其中第二及所述第二晶体管的所述基极归因于所述短路电线而处于相同电压。
CN2011800614027A 2010-12-20 2011-12-19 具有提高的切换速度及提高的交叉控制及增加的输出电压的互补达林顿射极跟随器 Pending CN103430310A (zh)

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