CN103414452A - Clock data recovery device and electronic device - Google Patents
Clock data recovery device and electronic device Download PDFInfo
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- CN103414452A CN103414452A CN2013103122294A CN201310312229A CN103414452A CN 103414452 A CN103414452 A CN 103414452A CN 2013103122294 A CN2013103122294 A CN 2013103122294A CN 201310312229 A CN201310312229 A CN 201310312229A CN 103414452 A CN103414452 A CN 103414452A
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Abstract
The embodiment of the invention discloses a clock data recovery device and an electronic device provided with the clock data recovery device, and belongs to the technical field of communication. The technical problem that an existing clock data recovery module is large in output shaking is solved. The clock data recovery device comprises a clock data recovery unit, a numerical control oscillating unit and a first in first out unit. The clock data recovery unit is used for recovering clock data on a data input signal through a first input clock signal to generate a preliminary clock signal and a preliminary data signal. The numerical control oscillating unit is used for carrying out frequency demultiplication on a second input clock signal with a definite frequency demultiplication coefficient to generate and send out a recovered clock signal, and used for comparing the preliminary clock signal with the recovered clock signal. If the preliminary clock signal is ahead of or lags behind the recovered clock signal, 1 is subtracted from or added to the frequency demultiplication coefficient correspondingly. The clock data recovery device is used for processing received data and sent data in the electronic device.
Description
Technical field
The invention belongs to communication technical field, the electronic equipment that is specifically related to a kind of clock data recovery device and is provided with this clock data recovery device.
Background technology
Along with the development of electronic technology, the frame format clock interface of E1 or T1 agreement has been widely used in various electronic equipments, and clock and data recovery module (Clock and Data Recovery, CDR) is one of them important component part.Existing CDR module has good service behaviour under the condition of input non-jitter, but when shake appearred in input, the outer time recovered also there will be shake.
As shown in Figure 1, the external clock of E1 agreement of take is example, and existing CDR module mainly comprises testing circuit, clock synchronization circuit and data sampling circuit, and external clock signal clk1 is 32.768MHz, and the frequency of external data input signal is 2MHz.When data input signal rpi, the rni of outside positive polarity and negative polarity and detection signal alose input CDR, testing circuit 11 is for receiving and detect rpi, rni, when the rising edge of data input signal being detected, just export a synchronization pulse sync.Critical piece in clock synchronization circuit 12 is the state machine with 16 states normally, with the frequency cycling jump of 32.768MHz, when receiving the sync that testing circuit 11 sends, jump to initial condition, while jumping to again the 9th state, the rising edge of output recovered clock signal clk_ex.Data sampling circuit 13 can adopt d type flip flop usually, for recovery data-signal rpo, the rno according to clk_ex output cathode and negative polarity, exports rpo and rno after namely rpi and rni being synchronized to the clock zone of clk_ex.
The inventor finds in realizing process of the present invention, there is following problem at least in prior art: because receive after sync jumps to initial condition at clock synchronization circuit 12, while jumping to the 9th state, the rising edge of output clk_ex, so the rising edge of clk_ex postpones the cycle of 8 32.786MHz all the time than sync, but when shake appearred in data input signal, the recovered clock signal of output also can produce the shake of formed objects, therefore there is the technical problem that output jitter is larger.
Summary of the invention
The electronic equipment that the embodiment of the present invention provides a kind of clock data recovery device and has been provided with this clock data recovery device, solved existing clock and data recovery module and had the technical problem that output jitter is larger.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of clock data recovery device, comprised clock and data recovery unit, numerical control oscillating unit and first-in first-out unit;
The clock signal input terminal of described clock and data recovery unit receives the first outside input clock signal, the data-signal input of described clock and data recovery unit receives outside data input signal, the clock signal output terminal of described clock and data recovery unit connects the first input end of numerical control oscillating unit and the first clock signal input terminal of described first-in first-out unit, and the data-signal output of described clock and data recovery unit connects the data-signal input of described first-in first-out unit;
The second input of described numerical control oscillating unit receives the second outside input clock signal, and the output of described numerical control oscillating unit connects the second clock signal input part of described first-in first-out unit and to outside, sends the recovered clock signal;
The data-signal output of described first-in first-out unit sends to outside and recovers data-signal;
Described clock and data recovery unit is for carrying out clock and data recovery by described the first input clock signal to described data input signal, generate just step clock signal and preliminary data signal, and to described numerical control oscillating unit and the described just step clock signal of described first-in first-out unit output, to the described preliminary data signal of described first-in first-out unit output, wherein, the frequency of described the first input clock signal is n times of the described just frequency of step clock signal, and n is the integer more than 2;
Described numerical control oscillating unit is for carrying out frequency division with certain divide ratio to described the second input clock signal, generate and send to outside the recovered clock signal, also described just step clock signal and described recovered clock signal are compared, if described just step clock signal is ahead of described recovered clock signal, described divide ratio is subtracted to 1, if described just step clock signal lags behind described recovered clock signal, described divide ratio is added to 1, wherein, described just step clock signal equates with the frequency of described recovered clock signal, the frequency of described the second input clock signal be described the first input clock signal frequency m doubly, m is the integer more than 2,
Described first-in first-out unit is used for receiving described preliminary data signal according to described just step clock signal, and to outside, sends described recovery data-signal according to described recovered clock signal.
In the possible implementation of the first, described numerical control oscillating unit comprises frequency divider, the first counter, the second counter and comparator;
Described frequency divider, for certain divide ratio, described the second input clock signal being carried out to frequency division, generates and sends to outside the recovered clock signal;
Described the first counter is for recording the described just number of pulses of step clock signal;
Described the second counter is for recording the number of pulses of described recovered clock signal;
Described comparator compares for the count results to described the first counter and described the second counter within each unit interval, and regulate the divide ratio in described frequency divider according to comparative result, if the count results of described the first counter is greater than the count results of described the second counter, described divide ratio is subtracted to 1, if the count results of described the first counter is less than the count results of described the second counter, described divide ratio is added to 1.
In conjunction with the possible implementation of the first, in the possible implementation of the second, described clock and data recovery unit comprises testing circuit, clock synchronization circuit and data sampling circuit;
Described testing circuit, for detection of described data input signal, when the rising edge of described data input signal being detected, is exported a synchronization pulse;
Described clock synchronization circuit is for the frequency with described the first input clock signal, cycling jump in n state, when receiving described synchronization pulse, jump to the initial condition in a described n state, during i state in jumping to a described n state, export the described just rising edge of step clock signal, wherein, 1<i<n;
Described data sampling circuit is for exporting described preliminary data signal according to described just step clock signal.
In conjunction with the possible implementation of the second, in the third possible implementation, the frequency of described the first input clock signal is 32.768MHz, n=16, i=9.
In conjunction with above-mentioned any one possible implementation, in the 4th kind of possible implementation, the frequency of described the second input clock signal is 131.072MHz, and the initial value of described divide ratio is 64.
On the other hand, also provide a kind of electronic equipment, comprised R-T unit and the described clock data recovery device of above-mentioned any implementation, described clock data recovery device is for carrying out clock and data recovery to the data that receive and send.
Compared with prior art, technique scheme provided by the present invention has following advantage: the numerical control oscillating unit carries out frequency division with certain divide ratio to the second input clock signal, generate the recovered clock signal equated with preliminary clock signal frequency, and first step clock signal and recovered clock signal are compared, when the shake of leading or hysteresis appears in data input signal, the first step clock signal of clock and data recovery unit output also there will be the shake of formed objects, now the numerical control oscillating unit subtracts divide ratio 1 or add 1 and adjust accordingly, be equivalent to the recovered clock signal of output is reduced or increased the cycle of second input clock signal.Because the frequency of the second input clock signal be the first input clock signal frequency m doubly, the frequency of the first input clock signal is n times of the just frequency of step clock signal, so the frequency of the second input clock signal is m * n times of the just frequency of step clock signal (data input signal), the shake size of adjusting on the recovered clock signal of exporting after divide ratio is only the cycle of second input clock signal, the m * n/of the shake size of data input signal, thereby by the mode of regulating divide ratio, shake larger on data input signal is shared in a plurality of recovered clock signals, therefore the first-in first-out unit has obtained significantly reducing to the shake on the recovery data-signal of outside transmission according to this recovered clock signal, solved and in the prior art, had the technical problem that output jitter is larger.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described.
Fig. 1 is the schematic diagram of existing clock and data recovery module;
The clock data recovery device that Fig. 2 provides for embodiments of the invention schematic diagram;
The schematic diagram of numerical control oscillating unit in the clock data recovery device that Fig. 3 provides for embodiments of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out to clear, complete description.
As shown in Figure 2, the clock data recovery device that the embodiment of the present invention provides, comprise clock and data recovery unit 1(Clock and Data Recovery, CDR), numerical control oscillating unit 2(Digitally Controlled Oscillator, DCO) and first-in first-out unit 3(First Input First Output, FIFO).
The clock signal input terminal of clock and data recovery unit 1 receives the first outside input clock signal clk1, the data-signal input of clock and data recovery unit 1 receives outside data input signal, this data input signal specifically comprises the two paths of data input signal rpi of positive polarity and negative polarity, rni, the clock signal output terminal of clock and data recovery unit 1 connects the first input end of numerical control oscillating unit 2 and the first clock signal input terminal of first-in first-out unit 3, the data-signal output of clock and data recovery unit 1 connects the data-signal input of first-in first-out unit 3.
The second input of numerical control oscillating unit 2 receives the second outside input clock signal clk2, and the output of numerical control oscillating unit 2 connects the second clock signal input part of first-in first-out unit 3 and to outside, sends recovered clock signal clk_ex.
The data-signal output of first-in first-out unit 3 sends to outside and recovers data-signal, and this recovery data-signal also comprises that the two-way of positive polarity and negative polarity recovers data-signal rpo, rno.
Clock and data recovery unit 1 is for carrying out clock and data recovery by clk1 to rpi and rni, generate just step clock signal clk_cdr and preliminary data signal, this preliminary data signal also comprises two-way preliminary data signal rp_cdr, the rn_cdr of positive polarity and negative polarity, and clock and data recovery unit 1 is also to numerical control oscillating unit 2 and first-in first-out unit 3 output clk_cdr, 3 output rp_cdr and the rn_cdr to the first-in first-out unit.Wherein, the frequency of clk1 be clk_cdr frequency n doubly, n is the integer more than 2.
Numerical control oscillating unit 2 carries out frequency division for the divide ratio a with certain to clk2, generates and to outside, sends recovered clock signal clk_ex, also for clk_cdr and clk_ex are compared.If clk_cdr is ahead of clk_ex, divide ratio is subtracted to 1, become a-1; If clk_cdr lags behind clk_ex, divide ratio is added to 1, become a+1.Wherein, clk_cdr equates with the frequency of clk_ex, the frequency of clk2 be clk1 frequency m doubly, m is the integer more than 2.
First-in first-out unit 3 is for according to clk_cdr, receiving rp_cdr and rn_cdr, and according to clk_ex, sends rpo and rno to outside, exports rpo and rno after namely rp_cdr and rn_cdr being synchronized to the clock zone of clk_ex.
In the clock data recovery device that the embodiment of the present invention provides, numerical control oscillating unit 2 carries out frequency division with certain divide ratio a to clk2, generate the clk_ex equated with the clk_cdr frequency, and clk_cdr and clk_ex are compared, when the shake of leading or hysteresis appears in rpi, rni, the clk_cdr of clock and data recovery unit 1 output also there will be the shake of formed objects, now numerical control oscillating unit 2 subtracts divide ratio a 1 or add 1 and adjust accordingly, is equivalent to the clk_ex of output is reduced or increased the cycle of a clk2.Because the frequency of clk2 be clk1 frequency m doubly, the frequency of clk1 be clk_cdr frequency n doubly, so the frequency of clk2 is clk_cdr(rpi, m * the n of frequency rni) doubly, the shake size of adjusting on the clk_ex exported after divide ratio a is only the cycle of a clk2, rpi, m * the n of the shake size of rni/mono-, thereby pass through to regulate the mode of divide ratio a by rpi, on rni, larger shake is shared in a plurality of clk_ex, therefore first-in first-out unit 3 is according to the rpo of this clk_ex to the outside transmission, the upper shake of rno has obtained significantly reducing, solved and in the prior art, had the technical problem that output jitter is larger.
As shown in Figure 3, in the embodiment of the present invention, numerical control oscillating unit 2 specifically comprises frequency divider 23, the first counter 21, the second counter 22 and comparator 24.
The first counter 21 is be used to recording the number of pulses of clk_cdr, and the second counter 22 is be used to recording the number of pulses of clk_ex, and the first counter 21 and the second counter 22 can be counted by the mode of tracer signal rising edge.
Clock and data recovery unit 1 in the embodiment of the present invention can adopt existing clock and data recovery module, as shown in Figure 1, comprises testing circuit 11, clock synchronization circuit 12 and data sampling circuit 13.
Testing circuit 11, for detection of rpi and rni, when the rising edge of rpi or rni being detected, is exported a synchronization pulse sync.
Critical piece in clock synchronization circuit 12 is a state machine normally, for the frequency with clk1, cycling jump in n state, when receiving sync, jump to n the initial condition in state, when jumping to n i state in state, the rising edge of output clk_cdr, wherein, 1<i<n.As a preferred version, the frequency of clk1 adopts 32.768MHz usually, and described state machine has 16 states, when receiving sync, jumps to initial condition, when jumping to the 9th state, and the rising edge of output clk_cdr, i.e. n=16, i=9.Because the frequency of rpi and rni is 2MHz, and, every clk_cdr of the cycle of 16 clk1 output, so the frequency of clk_cdr is also 2MHz, equate with the frequency of clk_ex.
In addition, because the frequency of the clk2 in the present embodiment is 131.072MHz, so the frequency of clk2 is 4 times of frequency of clk1, i.e. m=4.Certainly, the value of m also can be replaced by other numerical value in the integer range more than 2.
In the clock data recovery device that the embodiment of the present invention provides, numerical control oscillating unit 2 be take 64 pairs of frequencies of certain divide ratio and is carried out frequency division as the clk2 of 131.072MHz, generated frequency is the clk_ex of 2MHz, and clk_cdr and clk_ex are compared, when the shake of leading or hysteresis appears in rpi, rni, the clk_cdr of clock and data recovery unit 1 output also there will be the shake of formed objects, now numerical control oscillating unit 2 changes divide ratio into 63 or 65 accordingly, is equivalent to the clk_ex of output is reduced or increased the cycle of a clk2.Because clk_cdr(rpi, rni) frequency be 2MHz, and the shake size on the clk_ex exported after the adjustment divide ratio is only the cycle of a clk2, so the shake size on clk_ex be only rpi, rni the shake size 1/64th, thereby by the mode of regulating divide ratio, shake larger on rpi, rni is shared in a plurality of clk_ex, therefore first-in first-out unit 3 has obtained significantly reducing to the upper shake of rpo, the rno of outside transmission according to this clk_ex, has solved and in the prior art, has had the technical problem that output jitter is larger.
In addition, because the shake of rpi, rni is rare, so usually by enough a plurality of clk_ex, be used for sharing the shake on rpi, rni, for more smooth being split in clk_ex of the shake that makes rpi, rni, can divide into groups to clk_ex, using continuous several clk_ex as one group of signal, only regulate the divide ratio of a clk_ex in one group of signal, namely the shake of rpi, rni is shared in continuous many groups signal, and only have a clk_ex with shake in each group signal.The quantity of the clk_ex that every group of signal comprises can arrange according to practical situations.
The embodiment of the present invention also provides a kind of electronic equipment, comprises the clock data recovery device in R-T unit and above-described embodiment, and described clock data recovery device is for carrying out clock and data recovery to the data that receive and send.
The electronic equipment provided due to the embodiment of the present invention has identical technical characterictic with the clock data recovery device that the invention described above embodiment provides, so also can produce identical technique effect, solves identical technical problem.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (6)
1. a clock data recovery device, is characterized in that: comprise clock and data recovery unit, numerical control oscillating unit and first-in first-out unit;
The clock signal input terminal of described clock and data recovery unit receives the first outside input clock signal, the data-signal input of described clock and data recovery unit receives outside data input signal, the clock signal output terminal of described clock and data recovery unit connects the first input end of numerical control oscillating unit and the first clock signal input terminal of described first-in first-out unit, and the data-signal output of described clock and data recovery unit connects the data-signal input of described first-in first-out unit;
The second input of described numerical control oscillating unit receives the second outside input clock signal, and the output of described numerical control oscillating unit connects the second clock signal input part of described first-in first-out unit and to outside, sends the recovered clock signal;
The data-signal output of described first-in first-out unit sends to outside and recovers data-signal;
Described clock and data recovery unit is for carrying out clock and data recovery by described the first input clock signal to described data input signal, generate just step clock signal and preliminary data signal, and to described numerical control oscillating unit and the described just step clock signal of described first-in first-out unit output, to the described preliminary data signal of described first-in first-out unit output, wherein, the frequency of described the first input clock signal is n times of the described just frequency of step clock signal, and n is the integer more than 2;
Described numerical control oscillating unit is for carrying out frequency division with certain divide ratio to described the second input clock signal, generate and send to outside the recovered clock signal, also described just step clock signal and described recovered clock signal are compared, if described just step clock signal is ahead of described recovered clock signal, described divide ratio is subtracted to 1, if described just step clock signal lags behind described recovered clock signal, described divide ratio is added to 1, wherein, described just step clock signal equates with the frequency of described recovered clock signal, the frequency of described the second input clock signal be described the first input clock signal frequency m doubly, m is the integer more than 2,
Described first-in first-out unit is used for receiving described preliminary data signal according to described just step clock signal, and to outside, sends described recovery data-signal according to described recovered clock signal.
2. clock data recovery device according to claim 1, it is characterized in that: described numerical control oscillating unit comprises frequency divider, the first counter, the second counter and comparator;
Described frequency divider, for certain divide ratio, described the second input clock signal being carried out to frequency division, generates and sends to outside the recovered clock signal;
Described the first counter is for recording the described just number of pulses of step clock signal;
Described the second counter is for recording the number of pulses of described recovered clock signal;
Described comparator compares for the count results to described the first counter and described the second counter within each unit interval, and regulate the divide ratio in described frequency divider according to comparative result, if the count results of described the first counter is greater than the count results of described the second counter, described divide ratio is subtracted to 1, if the count results of described the first counter is less than the count results of described the second counter, described divide ratio is added to 1.
3. clock data recovery device according to claim 1, it is characterized in that: described clock and data recovery unit comprises testing circuit, clock synchronization circuit and data sampling circuit;
Described testing circuit, for detection of described data input signal, when the rising edge of described data input signal being detected, is exported a synchronization pulse;
Described clock synchronization circuit is for the frequency with described the first input clock signal, cycling jump in n state, when receiving described synchronization pulse, jump to the initial condition in a described n state, during i state in jumping to a described n state, export the described just rising edge of step clock signal, wherein, 1<i<n;
Described data sampling circuit is for exporting described preliminary data signal according to described just step clock signal.
4. clock data recovery device according to claim 3, it is characterized in that: the frequency of described the first input clock signal is 32.768MHz, n=16, i=9.
5. according to the described clock data recovery device of claim 1 to 4 any one, it is characterized in that: the frequency of described the second input clock signal is 131.072MHz, and the initial value of described divide ratio is 64.
6. electronic equipment is characterized in that: comprise R-T unit and the described clock data recovery device of claim 1 to 5 any one, described clock data recovery device is for carrying out clock and data recovery to the data that receive and send.
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| CN106533433A (en) * | 2015-09-09 | 2017-03-22 | 晨星半导体股份有限公司 | Clock pulse data replying device, clock pulse data replying method and phase detector |
| CN106656168A (en) * | 2016-12-30 | 2017-05-10 | 北京集创北方科技股份有限公司 | Clock data restoration device and method |
| CN112491528A (en) * | 2020-11-20 | 2021-03-12 | 武汉光迅信息技术有限公司 | Method and device for synchronous recovery of communication clock |
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