CN103401455A - Modulation method for active neutral-point clamp type tri-level inverter - Google Patents
Modulation method for active neutral-point clamp type tri-level inverter Download PDFInfo
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Abstract
The invention relates to a modulation method for an active neutral-point clamp type tri-level inverter. Based on a tri-level sine pulse-width modulation method, the modulation method of the invention obtains required pulse-width modulation signals by defining level switching manners of the active neutral-point clamp type tri-level voltage-source inverter, and designing conduction sequence of different switching elements according to different influences of the two switching manners on power consumption of the switching elements. The pulse-width modulation signals are used to control switching on/off of each switching element of the active neutral-point clamp type tri-level inverter, so that dc is converted into ac, and ac is provided for a load. The modulation method is suitable for large-power tri-level voltage-source inverters.
Description
Technical field
The present invention relates to a kind of three-level inverter modulator approach.
Background technology
The voltage with multiple levels source inventer can make its situation in transless or the series connection of synchro switch device be issued to higher voltage levvl.It can produce the output voltage of near sinusoidal, is applicable to the high-power application scenario.
Many level topological structure is the earliest proposed in 1975 by people such as Baker, and this many level topological structure, by the independently-powered single-phase full-bridge inverter unit of DC power supply separately, has formed cascaded inverter by series connection.The people such as Nabae in 1980 have proposed the three-level inverter circuit structure of neutral point clamper type.Basic thought is to obtain multistage staircase waveform by certain main circuit topological structure to export equivalent sine wave.
This three level neutral point clamped inverter topologys have solved the little and low problem of output voltage of two level voltage source inventer power outputs.Compare with two-level inverter, the main advantage of three level neutral point clamped inverters has: the ceiling voltage that can bear in (1) each switching tube course of work only has half of two level, greatly reduce the voltage stress of switching device, meet the requirement of high pressure unsteady flow; (2) when there is no in two-level inverter the series connection device conducting with turn-off simultaneously problem, the dynamic property of device is required low, system reliability is improved; (3) three-level inverter output phase voltage is three level staircase waveforms, line voltage is five level staircase waveforms, under same switching frequency, harmonic ratio two level are much lower, solved the high-voltage large-capacity inverter due to the problem switching frequency of switching loss and device performance can not be too high problem.
Nowadays, three level neutral point clamped inverters are used widely at aspects such as MW class large power industrial drives (as steel rolling, water pump, air blast, conveyer etc.), boats and ships industry, mining industry, locomotive tractions.
The deficiency of neutral point clamp inverter maximum is the imbalance that the semiconductor loss distributes.Because in each inverter, the switching device that bears maximum loss has determined switching frequency and the power output of whole inverter, in the neutral point clamp inverter, the part device loss is excessive, and heating is serious, has limited to a great extent the lifting of inverter switching frequency and power output.
Calendar year 2001, the T.Bruckner of Germany proposed the topological structure of active neutral point clamp inverter first.Active neutral point clamp inverter is to propose on the basis of neutral point clamp inverter, the clamper diode that adopts switching device to replace in traditional neutral point clamp inverter topology can produce the redundancy zero-voltage state, loss by the reasonable switching capable of regulating power device to these redundancy zero-voltage states in commutation course distributes, and solves the loss distribution imbalance problem of power device.
Active neutral point clamp inverter modulator approach is less, and existing method calculation of complex, can not utilize the redundancy zero-voltage state preferably, the loss distribution equilibrium of the power device space that also improves a lot.Take document " Feedforward loss control of three-level active NPC converters " as representative, these class methods propose junction temperature balance feed forward control method, the junction temperature that adopts Computer Simulation to draw power device under different modulating degree and load impedance angle distributes, determine zero-voltage state by the form of tabling look-up again, this method precision is relatively low, need to just can complete by emulation simultaneously.Take document " Three-level active NPC converter:PWM strategies and loss distribution " as representative, utilize the pulse-width modulation strategy to propose a kind of loss balancing method, but, owing to simply utilizing two kinds of on-off modes to switch mutually, can not obtain better power device loss balancing.
Summary of the invention
The objective of the invention is to overcome existing sinusoidal pulse width modulation method and control active neutral point clamp inverter, the poor problem of each switching device loss distribution equilibrium of inverter, propose a kind of active neutral point clamp three-level inverter modulator approach.The present invention can more effectively utilize redundancy zero-voltage state and the switching mode of active neutral point clamp inverter, apply the pulse-width signal that level switching sequence of the present invention forms, can reduce the maximum power loss of switching device, improve each switching device loss distribution equilibrium of inverter.
The present invention is based on three level sinusoidal pulse width modulation methods, by defining two kinds of level switching modes of active neutral point clamp three-level voltage source inverter, according to the power loss Different Effects of two kinds of switching modes for switching device, design the conducting sequential of each switching device, thereby obtain needed pulse-width signal, adopt described pulse-width signal to control the break-make of active each switching device of neutral point clamp inverter, converting direct-current power into alternating-current power is offered load.
Pulse duration modulation method of the present invention comprises the following steps:
(1) definition three level active neutral point clamp inverter output level state and level switching modes;
The active neutral point clamp inverter of three-phase tri-level is a kind of device that direct current is transformed into sinusoidal ac, comprises DC power supply Udc, two dividing potential drop electric capacity that parameter is identical, and a, b, c three-phase brachium pontis.every phase brachium pontis is comprised of 6 switching tubes, each switching tube has the diode of reverse parallel connection, wherein a phase brachium pontis is by the first switching tube, the second switch pipe, the 3rd switching tube and the 4th switching tube are composed in series, the anodic bonding of the first switching tube is to dc power anode, the negative electrode of the first switching tube connects the anode of second switch pipe, the negative electrode of second switch pipe connects the output of a cross streams electricity and the anode of the 3rd switching tube, the negative electrode of the 3rd switching tube connects the anode of the 4th switching tube, the negative electrode of the 4th switching tube connects the negative pole of DC power supply, what connect between the first switching tube and second switch pipe is the anode of the 5th switching tube, the negative electrode of the 5th switching tube is connected to the anode of midpoint potential O and the 6th switching tube, the negative electrode of the 6th switching tube is connected between the 3rd switching tube and the 4th switching tube.b phase brachium pontis is by the 7th switching tube, the 8th switching tube, the 9th switching tube and the tenth switching tube are composed in series, the anodic bonding of the 7th switching tube is to dc power anode P, the negative electrode of the 7th switching tube connects the anode of the 8th switching tube, the negative electrode of the 8th switching tube connects the output of b cross streams electricity and the anode of the 9th switching tube, the negative electrode of the 9th switching tube connects the anode of the tenth switching tube, the negative electrode of the tenth switching tube connects the negative pole N of DC power supply, what connect between the 7th switching tube and the 8th switching tube is the anode of the 11 switching tube, the negative electrode of the 11 switching tube is connected to the anode of midpoint potential O and twelvemo pass pipe, the negative electrode that twelvemo is closed pipe is connected between the 9th switching tube and the tenth switching tube.c phase brachium pontis is by the 13 switching tube, the 14 switching tube, the 15 switching tube, sixteenmo closes pipe and is composed in series, the anodic bonding of the 13 switching tube is to dc power anode P, the negative electrode of the 13 switching tube connects the anode of the 14 switching tube, the negative electrode of the 14 switching tube connects the output of c cross streams electricity and the anode of the 15 switching tube, the negative electrode of the 15 switching tube connects sixteenmo and closes the anode of pipe, sixteenmo closes the negative pole N of the negative electrode connection DC power supply of pipe, what connect between the 13 switching tube and the 14 switching tube is the anode of the 17 switching tube, the negative electrode of the 17 switching tube is connected to the anode of midpoint potential O and eighteenmo pass pipe, the negative electrode that eighteenmo closes pipe is connected between the 13 switching tube and the 14 switching tube.
, mutually as example, illustrate that the operation principle of three level active neutral point clamp inverters is as follows take a:
The 5th switching tube and the 6th switching tube are used for the active-clamp of voltage, the first dividing potential drop electric capacity and the second dividing potential drop electric capacity for inverter provide Udc/2 and-direct voltage of Udc/2.The basic principle of three level neutral point clamped inverter pulse duration modulation methods is by controlling the break-make of each switching tube, each export mutually Udc/2,0 and-three kinds of level of Udc/2, three level active neutral point clamp inverters export equally Udc/2,0 and-three kinds of level of Udc/2, different from three level neutral point clamped inverters is the four kinds of zero level producing methods that have of three level active neutral point clamp inverters, and output level corresponding to the break-make of each switching tube done following explanation:
The first switching tube, second switch pipe and the 6th switching tube are open-minded, the 3rd switching tube, the 4th switching tube and the 5th switching tube turn-off, the sense of current is timing, electric current flow through the first switching tube and second switch pipe, when the sense of current is negative, electric current flow through the first diode and the second diode, a phase output terminal voltage is Udc/2.Open the 6th switching tube, the purpose of turn-offing the 5th switching tube is the balance of voltage that guarantees between the 3rd switching tube and the 4th switching tube.
The first switching tube, second switch pipe and the 6th switching tube turn-off, when the 3rd switching tube, the 4th switching tube and the 5th switching tube are opened, the sense of current is timing, electric current flow through the 3rd diode and the 4th diode, when the sense of current is negative, electric current flow through the 3rd switching tube and the 4th switching tube, a phase output terminal voltage is-Udc/2.Turn-off the 6th switching tube, the purpose of opening the 5th switching tube is the balance of voltage that guarantees between the first switching tube and second switch pipe.
Second switch pipe and the 5th switching tube are open-minded, when the first switching tube, the 3rd switching tube, the 4th switching tube and the 6th switching tube turn-off, the sense of current is timing, electric current flow through second switch pipe and the 5th diode, when the sense of current is negative, electric current flow through the second diode and the 5th switching tube, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OU2 ";
Second switch pipe, the 4th switching tube and the 5th switching tube are open-minded, when the first switching tube, the 3rd switching tube and the 6th switching tube turn-off, the sense of current is timing, electric current flow through second switch pipe and the 5th diode, when the sense of current is negative, electric current flow through the second diode and the 5th switching tube, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OU1 ";
The first switching tube, the 3rd switching tube and the 6th switching tube are open-minded, when second switch pipe, the 4th switching tube and the 5th switching tube turn-off, the sense of current is timing, electric current flow through the 3rd diode and the 6th switching tube, when the sense of current is negative, electric current flow through the 3rd switching tube and the 6th diode, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OL1 ";
The 3rd switching tube and the 6th switching tube are open-minded, when the first switching tube, second switch pipe, the 4th switching tube and the 5th switching tube turn-off, the sense of current is timing, electric current flow through the 3rd diode and the 6th switching tube, when the sense of current is negative, electric current flow through the 3rd switching tube and the 6th diode, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OL2 ";
Three level active neutral point clamp inverter output level state and switch combination such as following tables, " 1 " expression is open-minded, and " 0 " expression is turn-offed:
Definition a phase level switching mode is as follows:
Electric current flows to or flows out on off state " 0U1 ", " 0U2 ", " 0L1 ", " 0L2 " and determined the distribution situation of switching loss.All guiding paths are all through a switching tube and a diode, even plural switching device conducting, only have a switching tube and a diode to have switching loss, remaining all switching device can not bear blocking voltage and On current simultaneously.
The present invention adopts sinusoidal pulse width modulation method, modulating wave and triangular carrier need to be compared.Definition for this reason:
When the value of modulating wave greater than zero the time,
For switching mode 1, the switching mutually between zero level state OU2 and level state Udc/2 of expression brachium pontis output level;
For switching mode 2, the switching mutually between zero level state OL1 and level state Udc/2 of expression brachium pontis output level;
When the value of modulating wave less than zero the time,
For switching mode 1, the switching mutually between zero level state OU1 and level state-Udc/2 of expression brachium pontis output level;
Switching mode 2, the switching mutually between zero level state OL2 and level state-Udc/2 of expression brachium pontis output level.
(2) judge the loss distribution situation of active each switching device of neutral point clamp inverter under each switching mode;
For traditional three level neutral point clamped inverters, suppose that electric current and voltage are all forward, the level switching mode is Udc/2 → 0, when namely the brachium pontis output level is switched to the zero level state from Udc/2: turn-off the first switching tube, through a Dead Time, open the 3rd switching tube, electric current no longer flow through ground one switching tube, change the 5th diode of flowing through into, the second switch pipe is in opening state all the time, the 4th switching tube is in closed condition all the time, and the first switching tube bears maximum switching loss.the level switching mode is-Udc/2 → 0, be the brachium pontis output level from-when Udc/2 is switched to the zero level state, the 4th switching tube bears maximum switching loss, when electric current is negative sense, the first diode and the 4th diode bear maximum switching loss, just cause traditional three level neutral point clamped inverter outer switch devices: the first switching tube, the first diode, the 4th switching tube, the 4th diode is than inner switch device: the second switch pipe, the second diode, the 3rd switching tube, the switching loss that the 3rd diode bears is large, the imbalance that causes the switching tube loss, bear the highest device of switching loss and limited the raising of inverter power and the raising of switching tube frequency, affected simultaneously the harmonic characterisitic of output waveform.
For active neutral point clamp inverter, following several situation is arranged:
When active neutral point clamp inverter is in switching mode 1,
1) as Udc/2 → 0U2, the brachium pontis output level is switched to zero level state 0U2 from Udc/2, the flow through upper brachium pontis of mid point of phase current, at first turn-off the 6th switching tube, then turn-off the first switching tube, after a Dead Time, open the 5th switching tube, the first switching tube bears maximum switching loss.
2) as 0U2 → Udc/2, the brachium pontis output level is switched to Udc/2 from zero level state 0U2, at first turn-off the 5th switching tube, then open the first switching tube, open finally the 6th switching tube, identical with traditional neutral point clamp inverter, be also that the first switching tube and the 5th diode produce main switching loss.
When active neutral point clamp inverter is in switching mode 2,
1) as Udc/2 → 0L1, the brachium pontis output level is switched to zero level state 0L1 from Udc/2, at first turn-off the second switch pipe, the first switching tube still is in opening state, after a Dead Time, open the 3rd switching tube, the phase current lower brachium pontis of directly flowing through, the second switch pipe produces maximum turn-off power loss.
2) as 0L1 → Udc/2, the brachium pontis output level is switched to Udc/2 from zero level state 0L1, at first turn-offs the 3rd switching tube, then opens the second switch pipe, and second switch pipe and the 3rd diode produce main switching loss.
When above-mentioned active neutral point clamp inverter was in two kinds of switching modes, the loss analysis of its switching tube and diode was as follows:
1) when the value of modulating wave greater than zero the time:
When active neutral point clamp inverter is in switching mode 1, the brachium pontis output level is switching mutually between zero level state OU2 and level state Udc/2,
The first switching tube, the first diode, the 5th switching tube, the 5th diode bear maximum switching loss at this moment;
When active neutral point clamp inverter is in switching mode 2, the brachium pontis output level is switching mutually between zero level state OL1 and level state Udc/2,
Second switch pipe, the second diode, the 3rd switching tube, the 3rd diode bear maximum switching loss at this moment;
2) when the value of modulating wave less than zero the time:
When active neutral point clamp inverter is in switching mode 1, the brachium pontis output level is switching mutually between zero level state OL2 and level state-Udc/2,
The 4th switching tube, the 4th diode, the 6th switching tube, the 6th diode bear maximum switching loss at this moment;
When active neutral point clamp inverter is in switching mode 2, the brachium pontis output level is switching mutually between zero level state OU1 and level state-Udc/2,
Second switch pipe, the second diode, the 3rd switching tube, the 3rd diode bear maximum switching loss at this moment.
(3) choose reasonable level switching mode, control the active neutral point clamp inverter a break-make of each switching device mutually, obtains needed pulse-width signal;
The inverter switch device loss distribution situation that obtains according to level switching mode and step (2) analysis of step (1) definition realizes pulse-width modulation.The present invention can adopt carrier wave sinusoidal pulse width modulation method and the reverse sinusoidal pulse width modulation method of carrier wave in the same way, in three-level inverter, the carrier wave sinusoidal pulse width modulation method in the same way sinusoidal pulse width modulation method total harmonic distortion more reverse than carrier wave is low, so the present invention selects carrier wave pulse duration modulation method in the same way.Carrier wave consists of upper strata triangular carrier, lower floor's triangular carrier, and modulating wave is sinusoidal modulation wave, also can adopt the modulating wave of sine-wave superimposed triple-frequency harmonics or adopt the staircase modulation ripple to improve modulation ratio.Upper strata triangular carrier and lower floor's triangular carrier are isosceles triangle wave, the value of upper strata triangular wave from 0 to 1, and the value of lower floor's triangular wave from-1 to 0, upper strata triangular carrier and lower floor's triangular carrier are in vertical direction in the same way.The value of modulating wave is limited between-1 to 1, the triangle wave frequency is greater than the modulation wave frequency, therefore within the cycle of each triangular carrier, the value of triangular carrier has intersection point with the value of modulating wave at the place of equating, if between two intersection points, modulating wave is on triangular carrier, represent modulating wave greater than triangular carrier, if modulating wave under triangular carrier, represents that modulating wave is less than triangular carrier.Greater than zero the time, the value of modulating wave and upper strata triangular carrier are compared at modulating wave, output positive half period pulse width modulated wave, and less than zero the time, the value of modulating wave and lower floor's triangular carrier are compared, output negative half-cycle pulse width modulated wave in modulation.
Greater than zero, and the value of modulating wave is during greater than the upper strata triangular carrier when the value of modulating wave, and a phase brachium pontis output voltage is Udc/2, first and second, six switching tube triggering signals are high level, third and fourth, five switching tube triggering signals are low level; When the value of modulating wave during less than first cycle of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second, five switching tube triggering signals are high level, first and third, four, six switching tube triggering signals are low level; When the value of modulating wave during less than the second period of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second, five switching tube triggering signals are high level, first and third, four, six switching tube triggering signals are low level; When the value of modulating wave during less than the 3rd cycle of upper strata triangular carrier, a phase brachium pontis output zero level OL1, first and third, six switching tube triggering signals are high level, second, four, five switching tube triggering signals are low level; When the value of modulating wave was less than the upper strata triangular carrier afterwards, six switching tubes were equally according to twice zero level OU2 of continuous employing, and one time the OL1 zero level produces pulse signal.
Less than zero, and the value of modulating wave is during less than lower floor's triangular carrier when the value of modulating wave, and a phase brachium pontis output voltage is-Udc/2, first and second, six switching tube triggering signals are low level, third and fourth, five switching tube triggering signals are high level; When the value of modulating wave during greater than first cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd, six switching tube triggering signals are high level, first and second, four, five switching tube triggering signals are low level; When the value of modulating wave during greater than the second period of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd, six switching tube triggering signals are high level, first and second, four, five switching tube triggering signals are low level; When the value of modulating wave during greater than the 3rd cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OU1, second, four, five switching tube triggering signals are high level, first and third, six switching tube triggering signals are low level; When the value of modulating wave was greater than lower floor's triangular carrier afterwards, six switching tubes were equally according to twice zero level OL2 of continuous employing, and one time zero level OU1 produces pulse signal.Corresponding switching mode sequence is:
Switching mode
The value of modulating wave is greater than zero the time:
The value of modulating wave is greater than zero the time, the first switching tube, the first diode, second switch pipe, the second diode, the 3rd switching tube, the 3rd diode, the 5th switching tube, the 5th diode bear switching loss, and wherein the first switching tube, the 5th switching tube switching frequency are second switch pipe, the 3rd switching tube 2 times;
The value of modulating wave is less than zero the time:
The value of modulating wave is less than zero the time, second switch pipe, the second diode, the 3rd switching tube, the 3rd diode, the 4th switching tube, the 4th diode, the 6th switching tube, the 6th diode bear switching loss, and wherein the 4th switching tube, the 6th switching tube switching frequency are second switch pipe, the 3rd switching tube 2 times.
Can guarantee that by top modulation system switching device second switch pipe, the second diode, the 3rd switching tube, the 3rd diode and the first switching tube, the first diode, the 5th switching tube, the 5th diode, the 4th switching tube, the 4th diode, the 6th switching tube, the 6th diode are within whole modulation period, have identical on-off times, thereby improved the loss balancing characteristic of active neutral point clamp inverter.
(4) form the pulse-width signal of active all switching devices of neutral point clamp inverter three-phase brachium pontis;
Through step (1), step (2) and step (3), formed a pulse-width signal of six switching devices mutually, a phase modulation wave signal is lagged behind 120 °, adopt the manner of comparison identical with a phase switching device, can form the b pulse-width signal of six switching tubes mutually.A phase modulation wave signal is lagged behind 240 °, adopt the manner of comparison identical with a phase switching device, can form the c pulse-width signal of six switching tubes mutually.Adopt pulse-width signal to control the break-make of active each switching device of neutral point clamp inverter, converting direct-current power into alternating-current power is offered load.
Description of drawings
Fig. 1 is the active neutral point clamp inverter structure of three-phase tri-level figure;
Fig. 2 is three level active neutral point clamp inverter a phase level switching modes 1;
Fig. 3 is three level active neutral point clamp inverter a phase level switching modes 2;
Fig. 4 is modulator approach pulse width signal figure of the present invention;
Fig. 5 is that to utilize the active neutral point clamp inverter of modulator approach three-phase tri-level of prior art be 0.8 o'clock loss distribution map for the power-factor of load;
Fig. 6 is that to utilize the active neutral point clamp inverter of modulator approach three-phase tri-level of the present invention be 0.8 o'clock loss distribution map for the power-factor of load;
Fig. 7 is that to utilize the active neutral point clamp inverter of modulator approach three-phase tri-level of prior art be 0.2 o'clock loss distribution map for the power-factor of load;
Fig. 8 is that to utilize the active neutral point clamp inverter of modulator approach three-phase tri-level of the present invention be 0.2 o'clock loss distribution map for the power-factor of load.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
Fig. 4 is modulator approach pulse width signal figure of the present invention, mainly comprises three parts: (1) carrier wave and modulating wave be oscillogram relatively; (2) the active neutral point clamp inverter Udc/2 that produces more afterwards of carrier wave ratio, zero level and-Udc/2 three level square wave figure; (3), according to modulation system of the present invention, produce Ta1, Ta2, Ta3, Ta4, Ta5 ,Ta6Liu road pwm pulse.
Pulse duration modulation method of the present invention comprises the following steps:
(1) definition three level active neutral point clamp inverter output level state and level switching modes;
The active neutral point clamp inverter of three-phase tri-level is direct current to be transformed into the device of sinusoidal ac.As shown in Figure 1, the active neutral point clamp inverter of three-phase tri-level comprises DC power supply Udc, two dividing potential drop capacitor C 1, C2 that parameter is identical, and a, b, c three-phase brachium pontis.Every phase brachium pontis is comprised of 6 switching tubes, and each switching tube has diode Da1～Da6, Db1～Db6, the Dc1～Dc6 of reverse parallel connection.Wherein a phase brachium pontis is composed in series by the first switch transistor T a1, second switch pipe Ta2, the 3rd switch transistor T a3 and the 4th switch transistor T a4.The anodic bonding of the first switch transistor T a1 is to dc power anode P, the negative electrode of the first switch transistor T a1 connects the anode of second switch pipe Ta2, the negative electrode of second switch pipe Ta2 connects the output of a cross streams electricity and the anode of the 3rd switch transistor T a3, the negative electrode of the 3rd switch transistor T a3 connects the anode of the 4th switch transistor T a4, and the negative electrode of the 4th switch transistor T a4 connects the negative pole N of DC power supply.What connect between the first switch transistor T a1 and second switch pipe Ta2 is the anode of the 5th switch transistor T a5, the negative electrode of the 5th switch transistor T a5 is connected to the anode of midpoint potential O and the 6th switch transistor T a6, and the negative electrode of the 6th switch transistor T a6 is connected between the 3rd switch transistor T a3 and the 4th switch transistor T a4.B phase brachium pontis is composed in series by the 7th switching tube Tb1, the 8th switching tube Tb2, the 9th switch transistor T b3 and the tenth switch transistor T b4.the anodic bonding of the 7th switching tube Tb1 is to dc power anode P, the negative electrode of the 7th switching tube Tb1 connects the anode of the 8th switching tube Tb2, the negative electrode of the 8th switching tube Tb2 connects the output of b cross streams electricity and the anode of the 9th switch transistor T b3, the negative electrode of the 9th switch transistor T b3 connects the anode of the tenth switch transistor T b4, the negative electrode of the tenth switch transistor T b4 connects the negative pole N of DC power supply, what connect between the 7th switching tube Tb1 and the 8th switching tube Tb2 is the anode of the 11 switch transistor T b5, the negative electrode of the 11 switch transistor T b5 is connected to midpoint potential O and twelvemo is closed the anode of managing Tb6, the negative electrode that twelvemo is closed pipe Tb6 is connected between the 7th switching tube Tb3 and the 8th switching tube Tb4.C phase brachium pontis closes pipe Tc4 by the 13 switch transistor T c1, the 14 switch transistor T c2, the 15 switch transistor T c3 and sixteenmo and is composed in series.the anodic bonding of the 13 switch transistor T c1 is to dc power anode P, the negative electrode of the 13 switch transistor T c1 connects the anode of the 14 switch transistor T c2, the negative electrode of the 14 switch transistor T c2 connects the output of c cross streams electricity and the anode of the 15 switch transistor T c3, the negative electrode of the 15 switch transistor T c3 connects sixteenmo and closes the anode of pipe Tc4, sixteenmo closes the negative pole N of the negative electrode connection DC power supply of pipe Tc4, what connect between the 13 switch transistor T c1 and the 14 Tc2 is the anode of the 17 switching tube Tc5, the negative electrode of the 17 switching tube Tc5 is connected to midpoint potential O and eighteenmo closes the anode of managing Tc6, the negative electrode that eighteenmo closes pipe Tc6 is connected between the 13 switch transistor T c3 and the 14 switch transistor T c4.
Mutually as example, the operation principle of three level active neutral point clamp inverters is as follows take a:
The 5th switch transistor T a5 and the 6th switch transistor T a6 are used for the active-clamp of voltage, the first dividing potential drop capacitor C 1 and the second dividing potential drop capacitor C 2 for inverter provide Udc/2 and-direct voltage of Udc/2.The basic principle of three level neutral point clamped inverter pulse duration modulation methods is by controlling the break-make of each switching tube, each export mutually Udc/2,0 and-three kinds of level of Udc/2, three level active neutral point clamp inverters export equally Udc/2,0 and-three kinds of level of Udc/2, different from three level neutral point clamped inverters is the four kinds of zero level producing methods that have of three level active neutral point clamp inverters, and output level corresponding to the break-make of each switching tube done following explanation:
The first switch transistor T a1, second switch pipe Ta2 and the 6th switch transistor T a6 conducting, when the 3rd switch transistor T a3, the 4th switch transistor T a4 and the 5th switch transistor T a5 turn-off, the sense of current is timing, electric current flow through the first switch transistor T a1 and second switch pipe Ta2, when the sense of current is negative, electric current flow through the first diode Da1 and the second diode Da2, a phase output terminal voltage is Udc/2, open the 6th switch transistor T a6, the purpose of turn-offing the 5th switch transistor T a5 is the balance of voltage that guarantees between the 3rd switch transistor T a3 and the 4th switch transistor T a4;
The first switch transistor T a1, second switch pipe Ta2 and the 6th switch transistor T a6 turn-off, when the 3rd switch transistor T a3, the 4th switch transistor T a4 and the 5th switch transistor T a5 conducting, the sense of current is timing, electric current flow through the 3rd diode Da3 and the 4th diode Da4, when the sense of current is negative, electric current flow through the 3rd switch transistor T a3 and the 4th switch transistor T a4, a phase output terminal voltage is-Udc/2, turn-off the 6th switch transistor T a6, the purpose of opening the 5th switch transistor T a5 is the balance of voltage that guarantees between the first switch transistor T a1 and second switch pipe Ta2;
Second switch pipe Ta2 and the 5th switch transistor T a5 conducting, when the first switch transistor T a1, the 3rd switch transistor T a3, the 4th switch transistor T a4 and the 6th switch transistor T a6 turn-off, the sense of current is timing, electric current flow through second switch pipe Ta2 and the 5th diode Da5, when the sense of current is negative, electric current flow through the second diode Da2 and the 5th switch transistor T a5, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OU2 ";
Second switch pipe Ta2, the 4th switch transistor T a4 and the 5th switch transistor T a5 conducting, when the first switch transistor T a1, the 3rd switch transistor T a3 and the 6th switch transistor T a6 turn-off, the sense of current is timing, electric current flow through second switch pipe Ta2 and the 5th diode Da5, when the sense of current is negative, electric current flow through the second diode Da2 and the 5th switch transistor T a5, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OU1 ";
The first switch transistor T a1, the 3rd switch transistor T a3 and the 6th switch transistor T a6 conducting, when second switch pipe Ta2, the 4th switch transistor T a4 and the 5th switch transistor T a5 turn-off, the sense of current is timing, electric current flow through the 3rd diode Da3 and the 6th switch transistor T a6, when the sense of current is negative, electric current flow through the 3rd switch transistor T a3 and the 6th diode Da6, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OL1 ";
The 3rd switch transistor T a3 and the 6th switch transistor T a6 conducting, when the first switch transistor T a1, second switch pipe Ta2, the 4th switch transistor T a4 and the 5th switch transistor T a5 turn-off, the sense of current is timing, electric current flow through the 3rd diode Da3 and the 6th switch transistor T a6, when the sense of current is negative, electric current flow through the 3rd switch transistor T a3 and the 6th diode Da6, a phase output terminal voltage are zero, and define the zero level that this switch combination mode exports is " OL2 ";
Three level active neutral point clamp inverter output level state and switch combination such as following tables, " 1 " expression is open-minded, and " 0 " expression is turn-offed:
Definition a phase level switching mode is as follows:
Electric current flows to or flows out on off state " 0U1 ", " 0U2 ", " 0L1 ", " 0L2 " and determined the distribution situation of switching loss.All guiding paths are all through a switching tube and a diode, even plural switching device conducting, only have a switching tube and a diode to have switching loss, remaining all switching device can not bear blocking voltage and On current simultaneously.
Definition:
When the value of modulating wave greater than zero the time,
For switching mode 1, the switching mutually between zero level state OU2 and level state Udc/2 of expression brachium pontis output level;
For switching mode 2, the switching mutually between zero level state OL1 and level state Udc/2 of expression brachium pontis output level;
When the value of modulating wave less than zero the time,
For switching mode 1, the switching mutually between zero level state OU1 and level state-Udc/2 of expression brachium pontis output level;
Switching mode 2, the switching mutually between zero level state OL2 and level state-Udc/2 of expression brachium pontis output level.
(2) judge the loss distribution situation of active each switching device of neutral point clamp inverter under each switching mode;
For traditional three level neutral point clamped inverters, suppose that electric current and voltage are all forward, level switching mode mode is Udc/2 → 0, be brachium pontis output level while from Udc/2, being switched to the zero level state: turn-off the first switch transistor T a1, through a Dead Time, open the 3rd switch transistor T a2, the electric current first switch transistor T a1 that no longer flows through, change the 5th diode pipe Da5 that flows through into, second switch pipe Ta2 is in opening state all the time, the 4th switch transistor T a4 is in closed condition all the time, and the first switch transistor T a1 bears maximum switching loss.the level switching mode is-Udc/2 → 0, be the brachium pontis output level from-when Udc/2 is switched to the zero level state, the 4th switch transistor T a4 bears maximum switching loss, when electric current is negative sense, the first diode Da1 and the 4th diode Da4 bear maximum switching loss, just cause traditional three level neutral point clamped inverter outer switch devices: the first switch transistor T a1, the first diode Da1, the 4th switch transistor T a4, the 4th diode Da4 is than inner switch device: second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the switching loss that the 3rd diode Da3 bears is large, the imbalance that causes the switching tube loss, bear the highest device of switching loss and limited the raising of inverter power and the raising of switching tube frequency, affected simultaneously the harmonic characterisitic of output waveform.
For active neutral point clamp inverter, following several situation is arranged:
When active neutral point clamp inverter is in switching mode 1,
1) as Udc/2 → 0U2, the brachium pontis output level is switched to zero level state 0U2 from Udc/2, the flow through upper brachium pontis of mid point of phase current, at first turn-off the 6th switch transistor T a6, then turn-off the first switch transistor T a1, after a Dead Time, open the 5th switch transistor T a5, the first switch transistor T a1 bears maximum switching loss.
2) as 0U2 → Udc/2, the brachium pontis output level is switched to Udc/2 from zero level state 0U2, at first turn-off the 5th switch transistor T a5, then open the first switch transistor T a1, open finally the 6th switch transistor T a6, identical with traditional neutral point clamp inverter, be also that the first switch transistor T a1 and the 5th diode Da5 produce main switching loss.
When active neutral point clamp inverter is in switching mode 2,
1) as Udc/2 → 0L1, the brachium pontis output level is switched to zero level state 0L1 from Udc/2, at first turn-off second switch pipe Ta2, the first switch transistor T a1 still is in opening state, after a Dead Time, open the 3rd switch transistor T a3, the phase current lower brachium pontis of directly flowing through, second switch pipe Ta2 produces maximum turn-off power loss.
2) as 0L1 → Udc/2, the brachium pontis output level is switched to Udc/2 from zero level state 0L1, at first turn-offs the 3rd switch transistor T a3, then opens second switch pipe Ta2, and second switch pipe Ta2 and the 3rd diode Da3 produce main switching loss.
When above-mentioned active neutral point clamp inverter was in two kinds of switching modes, the loss analysis of its switching tube and diode was as follows:
1) when the value of modulating wave greater than zero the time:
When active neutral point clamp inverter is in switching mode 1, the brachium pontis output level is switching mutually between zero level state OU2 and level state Udc/2,
The first switch transistor T a1, the first diode Da1, the 5th switch transistor T a5, the 5th diode Da5 bear maximum switching loss at this moment;
When active neutral point clamp inverter is in switching mode 2, the brachium pontis output level is switching mutually between zero level state OL1 and level state Udc/2,
Second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the 3rd diode Da3 bear maximum switching loss at this moment;
2) when the value of modulating wave less than zero the time:
When active neutral point clamp inverter is in switching mode 1, the brachium pontis output level is switching mutually between zero level state OL2 and level state-Udc/2,
The 4th switch transistor T a4, the 4th diode Da4, the 6th switch transistor T a6, the 6th diode Da6 bear maximum switching loss at this moment;
When active neutral point clamp inverter is in switching mode 2, the brachium pontis output level is switching mutually between zero level state OU1 and level state-Udc/2,
Second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the 3rd diode Da3 bear maximum switching loss at this moment.
(3) choose reasonable level switching mode, control the active neutral point clamp inverter a break-make of each switching device mutually, obtains needed pulse-width signal;
Distribute according to level switching mode and the loss of step (1) and step (2), realize pulse-width modulation.The present invention can adopt carrier wave sinusoidal pulse width modulation method or the reverse sinusoidal pulse width modulation method of carrier wave in the same way, in three-level inverter, the carrier wave sinusoidal pulse width modulation method in the same way sinusoidal pulse width modulation method total harmonic distortion more reverse than carrier wave is low, so the present invention selects carrier wave pulse duration modulation method in the same way.Carrier wave consists of upper strata triangular carrier, lower floor's triangular carrier.Modulating wave is sinusoidal modulation wave, also can adopt the modulating wave of sine-wave superimposed triple-frequency harmonics or adopt the staircase modulation ripple to improve modulation ratio.Upper strata triangular carrier and lower floor's triangular carrier are all isosceles triangle waves, the value of upper strata triangular wave from 0 to 1, and the value of lower floor's triangular wave from-1 to 0, upper strata triangular carrier and lower floor's triangular carrier are in vertical direction in the same way.The value of modulating wave is limited to from-1 to 1, the triangle wave frequency is greater than the modulation wave frequency, the value of triangular carrier has intersection point with the value of modulating wave at the place of equating, if between two intersection points, modulating wave is on triangular carrier, represent that modulating wave is greater than triangular carrier, if modulating wave under triangular carrier, represents that modulating wave is less than triangular carrier.Greater than zero the time, the value of modulating wave and upper strata triangular carrier are compared at modulating wave, output positive half period pulse width modulated wave, and less than zero the time, the value of modulating wave and lower floor's triangular carrier are compared, output negative half-cycle pulse width modulated wave in modulation.
When the value of modulating wave greater than zero, and the value of modulating wave is during greater than the upper strata triangular carrier, a phase brachium pontis output voltage is Udc/2, the first switch transistor T a1, second switch pipe Ta2, the 6th switch transistor T a6 triggering signal are high level, and the 3rd switch transistor T a3, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are low level; When the value of modulating wave during less than first cycle of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second switch pipe Ta2, the 5th switch transistor T a5 triggering signal are high level, and the first switch transistor T a1, the 3rd switch transistor T a3, the 4th switch transistor T a4, the 6th switch transistor T a6 triggering signal are low level; When the value of modulating wave during less than the second period of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second switch pipe Ta2, the 5th switch transistor T a5 triggering signal are high level, and the first switch transistor T a1, the 3rd switch transistor T a3, the 4th switch transistor T a4, the 6th switch transistor T a6 triggering signal are low level; When the value of modulating wave during less than the 3rd cycle of upper strata triangular carrier, a phase brachium pontis output zero level OL1, the first switch transistor T a1, the 3rd switch transistor T a3, the 6th switch transistor T a6 triggering signal are high level, and second switch pipe Ta2, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are low level; When the value of modulating wave was less than the upper strata triangular carrier afterwards, six switching tubes were equally according to twice zero level OU2 of continuous employing, and one time the OL1 zero level produces pulse signal.
When the value of modulating wave less than zero, and the value of modulating wave is during less than lower floor's triangular carrier, a phase brachium pontis output voltage is-Udc/2, the first switch transistor T a1, second switch pipe Ta2, the 6th switch transistor T a6 triggering signal are low level, and the 3rd switch transistor T a3, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are high level; When the value of modulating wave during greater than first cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd switch transistor T a3, the 6th switch transistor T a6 triggering signal are high level, and the first switch transistor T a1, second switch pipe Ta2, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are low level; When the value of modulating wave during greater than the second period of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd switch transistor T a3, the 6th switch transistor T a6 triggering signal are high level, and the first switch transistor T a1, second switch pipe Ta2, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are low level; When the value of modulating wave during greater than the 3rd cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OU1, second switch pipe Ta2, the 4th switch transistor T a4, the 5th switch transistor T a5 triggering signal are high level, and the first switch transistor T a1, the 3rd switch transistor T a3, the 6th switch transistor T a6 triggering signal are low level; When the value of modulating wave was greater than lower floor's triangular carrier afterwards, six switching tubes were equally according to twice zero level OL2 of continuous employing, and one time zero level OU1 produces pulse signal.Corresponding switching mode sequence is:
The value of modulating wave is greater than zero the time:
The value of modulating wave is greater than zero the time, the first switch transistor T a1, the first diode Da1, second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the 3rd diode Da2, the 5th switch transistor T a5, the 5th diode Da5 bear switching loss, and wherein the first switch transistor T a1, the 5th switch transistor T a5 switching frequency are second switch pipe Ta2, the 3rd switch transistor T a3 2 times;
The value of modulating wave is less than zero the time:
The value of modulating wave is less than zero the time, second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the 3rd diode Da3, the 4th switch transistor T a4, the 4th diode Da4, the 6th switch transistor T a6, the 6th diode Da6 bear switching loss, and wherein the 4th switch transistor T a4, the 6th switch transistor T a6 switching frequency are second switch pipe Ta2, the 3rd switch transistor T a3 2 times.
Can guarantee that by top modulation system switching device second switch pipe Ta2, the second diode Da2, the 3rd switch transistor T a3, the 3rd diode Da3 and the first switch transistor T a1, the first diode Da1, the 5th switch transistor T a5, the 5th diode Da5, the 4th switch transistor T a4, the 4th diode Da4, the 6th switch transistor T a6, the 6th diode Da6 are within whole modulation period, have identical on-off times, thereby improved the loss balancing characteristic of active neutral point clamp inverter.
(4) form the pulse-width signal of all switching tubes of three-phase brachium pontis;
Through step (1), step (2) and step (3), formed a pulse-width signal of six switching devices mutually, a phase modulation wave signal is lagged behind 120 °, adopt the manner of comparison identical with a phase switching device, can form the b pulse-width signal of six switching tubes mutually, a phase modulation wave signal is lagged behind 240 °, adopt the manner of comparison identical with a phase switching device, can form the c pulse-width signal of six switching tubes mutually.Adopt pulse-width signal to control the break-make of active each switching device of neutral point clamp inverter,, with converting direct-current power into alternating-current power, offer load.
Below in conjunction with embodiment, implementation result of the present invention is described.
The inverter capacity that uses in the present embodiment is 750KVA, and switching tube IGBT model is FZ1500R33HE3, carrier frequency f=1200HZ, direct voltage Udc is 1800V, and capacitor C 1, C2 are 5mF, output current phase I=430A, output line voltage is 1000V, and modulation ratio is 0.8.
The transverse axis of Fig. 5, Fig. 6, Fig. 7, Fig. 8 represents switching device, and the longitudinal axis represents the switching loss of IGBT, the conduction loss of IGBT, the reverse recovery loss of diode and the conduction loss sum of diode.Simply with the method for 1:1 ratio modulation, compare with level switching mode 2 with existing level switching mode 1, it is 0.8 o'clock in the power-factor of load, the switching device loss distributes as shown in Figure 5 and Figure 6, the power loss of bearing the switching device generation of maximum power loss is reduced to 521W from 691W, and maximum loss has reduced by 25%.Be 0.2 o'clock in the power-factor of load, the switching device loss distributes as shown in Figure 7 and Figure 8, and the power loss of bearing the switching device generation of maximum power loss is reduced to 510W from 664W, and maximum loss has reduced by 23%.
The present invention can also be applied to the three level active neutral point clamp inverters that other any full-control type power electronic switching devices form.
Claims (2)
1. active neutral point clamp three-level inverter modulator approach, it is characterized in that, described method is based on three level sinusoidal pulse width modulation methods, by defining active neutral point clamp three-level voltage source inverter level switching mode, according to the impact of described switching mode for the power loss of switching device, design the conducting sequential of each switching device, thereby obtain needed pulse-width signal; Adopt described pulse-width signal to control the break-make of active each switching device of neutral point clamp inverter, converting direct-current power into alternating-current power is offered load.
2. modulator approach according to claim 1, is characterized in that described modulator approach comprises the steps:
(1) definition three level active neutral point clamp inverter output level state and level switching modes;
A phase brachium pontis switching tube on off state and level output state are defined as follows:
The first switching tube (Ta1), second switch pipe (Ta2) and the 6th switching tube (Ta6) are open-minded, and when the 3rd switching tube (Ta3), the 4th switching tube (Ta4) and the 5th switching tube (Ta5) turn-offed, a phase output terminal voltage was half Udc/2 of direct voltage;
The first switching tube (Ta1), second switch pipe (Ta2) and the 6th switching tube (Ta6) turn-off, and the 3rd switching tube (Ta3), the 4th switching tube (Ta4) and the 5th switching tube (Ta5) are while opening, and a phase output terminal voltage is-Udc/2;
Second switch pipe (Ta2) and the 5th switching tube (Ta5) are open-minded, when the first switching tube (Ta1), the 3rd switching tube (Ta3), the 4th switching tube (Ta4) and the 6th switching tube (Ta6) turn-off, a phase output terminal voltage is zero, and define the zero level that this switch combination mode exports is " OU2 ";
Second switch pipe (Ta2), the 4th switching tube (Ta4) and the 5th switching tube (Ta5) are open-minded, when the first switching tube (Ta1), the 3rd switching tube (Ta3) and the 6th switching tube (Ta6) turn-off, a phase output terminal voltage is zero, and define the zero level that this switch combination mode exports is " OU1 ";
The first switching tube (Ta1), the 3rd switching tube (Ta3) and the 6th switching tube (Ta6) are open-minded, when second switch pipe (Ta2), the 4th switching tube (Ta4) and the 5th switching tube (Ta5) turn-off, a phase output terminal voltage is zero, and define the zero level that this switch combination mode exports is " OL1 ";
The 3rd switching tube (Ta3) and the 6th switching tube (Ta6) are open-minded, when the first switching tube (Ta1), second switch pipe (Ta2), the 4th switching tube (Ta4) and the 5th switching tube (Ta5) turn-off, a phase output terminal voltage is zero, and define the zero level that this switch combination mode exports is " OL2 ";
The level switching mode:
Definition: the value of modulating wave greater than zero the time,
For switching mode 1, the switching mutually between zero level state OU2 and level state Udc/2 of expression brachium pontis output level;
For switching mode 2, the switching mutually between zero level state OL1 and level state Udc/2 of expression brachium pontis output level; The value of modulating wave less than zero the time,
For switching mode 1, the switching mutually between zero level state OU1 and level state-Udc/2 of expression brachium pontis output level;
Switching mode 2, the switching mutually between zero level state OL2 and level state-Udc/2 of expression brachium pontis output level;
(2) the loss distribution situation of each switching device under the various switching modes of judgement;
Under the mutually various switching modes of judgement a, the loss distribution situation of each switching device is as follows:
The value of modulating wave is greater than zero the time:
Switching mode 1;
The first switching tube (Ta1), the first diode (Da1), the 5th switching tube (Ta5), the 5th diode (Da5) bear maximum switching loss;
Switching mode 2:
Second switch pipe (Ta2), the second diode (Da2), the 3rd switching tube (Ta3), the 3rd diode (Da3) bear maximum switching loss;
The value of modulating wave is less than zero the time:
Switching mode 1:
The 4th switching tube (Ta4), the 4th diode (Da4), the 6th switching tube (Ta6), the 6th diode (Da6) bear maximum switching loss;
Switching mode 2:
Second switch pipe (Ta2), the second diode (Da2), the 3rd switching tube (Ta3), the 3rd diode (Da3) bear maximum switching loss;
(3) select the level switching mode, control the active neutral point clamp inverter a break-make of each switching device mutually, obtain needed pulse-width signal;
Each switching device loss distribution situation that obtains according to the level switching mode of step (1) and step (2) analysis realizes pulse-width modulation;
In three level sinusoidal pulse width modulation methods, carrier wave consists of upper strata triangular carrier, lower floor's triangular carrier; Modulating wave is sinusoidal modulation wave, perhaps adopts the modulating wave of sine-wave superimposed triple-frequency harmonics or adopts the staircase modulation ripple to improve modulation ratio; Greater than zero the time, modulating wave and upper strata carrier wave are compared in the value of modulating wave, output positive half period pulse width modulated wave, and less than zero, modulating wave and lower floor's carrier wave are compared, output negative half-cycle pulse width modulated wave in the value of modulating wave;
When the value of modulating wave greater than zero, and the value of modulating wave is during greater than the upper strata triangular carrier, a phase brachium pontis output voltage is Udc/2, the first switching tube (Ta1), second switch pipe (Ta2), the 6th switching tube (Ta6) triggering signal are high level, and the 3rd switching tube (Ta3), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are low level; When the value of modulating wave during less than first cycle of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second switch pipe (Ta2), the 5th switching tube (Ta5) triggering signal are high level, and the first switching tube (Ta1), the 3rd switching tube (Ta3), the 4th switching tube (Ta4), the 6th switching tube (Ta6) triggering signal are low level; When the value of modulating wave during less than the second period of upper strata triangular carrier, a phase brachium pontis output zero level OU2, second switch pipe (Ta2), the 5th switching tube (Ta5) triggering signal are high level, and the first switching tube (Ta1), the 3rd switching tube (Ta3), the 4th switching tube (Ta4), the 6th switching tube (Ta6) triggering signal are low level; When the value of modulating wave during less than the 3rd cycle of upper strata triangular carrier, a phase brachium pontis output zero level OL1, the first switching tube (Ta1), the 3rd switching tube (Ta3), the 6th switching tube (Ta6) triggering signal are high level, and second switch pipe (Ta2), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are low level; When the value of modulating wave was less than the upper strata triangular carrier afterwards, six switching tubes were equally according to twice zero level OU2 of continuous employing, and one time zero level OL1 produces pulse signal;
When the value of modulating wave less than zero, and the value of modulating wave is during less than lower floor's triangular carrier, a phase brachium pontis output voltage is-Udc/2, the first switching tube (Ta1), second switch pipe (Ta2), the 6th switching tube (Ta6) triggering signal are low level, and the 3rd switching tube (Ta3), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are high level; When the value of modulating wave during greater than first cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd switching tube (Ta3), the 6th switching tube (Ta6) triggering signal are high level, and the first switching tube (Ta1), second switch pipe (Ta2), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are low level; When the value of modulating wave during greater than the second period of lower floor's triangular carrier, a phase brachium pontis output zero level OL2, the 3rd switching tube (Ta3), the 6th switching tube (Ta6) triggering signal are high level, and the first switching tube (Ta1), second switch pipe (Ta2), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are low level; When the value of modulating wave during greater than the 3rd cycle of lower floor's triangular carrier, a phase brachium pontis output zero level OU1, second switch pipe (Ta2), the 4th switching tube (Ta4), the 5th switching tube (Ta5) triggering signal are high level, and the first switching tube (Ta1), the 3rd switching tube (Ta3), the 6th switching tube (Ta6) triggering signal are low level; When the value of modulating wave was greater than lower floor's triangular carrier afterwards, six switching tubes were equally according to twice zero level OL2 of continuous employing, and one time zero level OU1 produces pulse signal;
(4) form the pulse-width signal of active all switching devices of neutral point clamp inverter three-phase brachium pontis;
Through step (1), step (2) and step (3), formed a pulse-width signal of six switching tubes mutually, a phase modulation wave signal is lagged behind 120 °, adopt the manner of comparison mutually same with a phase switching device, form the b pulse-width signal of six switching tubes mutually; A phase modulation wave signal is lagged behind 240 °, adopt the manner of comparison identical with a phase switching device, form the c pulse-width signal of six switching devices mutually; Adopt pulse-width signal to control the break-make of active each switching device of neutral point clamp inverter,, with converting direct-current power into alternating-current power, offer load.
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