CN103391002A - System and method of predictive current feedback for switched mode regulators - Google Patents
System and method of predictive current feedback for switched mode regulators Download PDFInfo
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- CN103391002A CN103391002A CN2012103755979A CN201210375597A CN103391002A CN 103391002 A CN103391002 A CN 103391002A CN 2012103755979 A CN2012103755979 A CN 2012103755979A CN 201210375597 A CN201210375597 A CN 201210375597A CN 103391002 A CN103391002 A CN 103391002A
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Abstract
The invention relates to a system and method of predictive current feedback for switched mode regulators. The invention particularly discloses a predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.
Description
The cross reference of related application
The application requires the U.S. Provisional Application S/N61/646 that submitted on May 11st, 2012,007 rights and interests, and the full content of this application is intentional incorporated herein by reference with purpose for institute.
Description of drawings
By reference to the following description and accompanying drawing can understand better benefit of the present invention, feature and advantage, in the accompanying drawings:
Fig. 1 disposes the simplified block diagram of the electronic equipment of power system according to one embodiment of the invention, this power system has realization the adjuster of the modulator of predicted current feedback is arranged;
Fig. 2 is the simplified schematic block diagram according to the example regulator of the modulator that comprises Fig. 1 of an embodiment realization;
Fig. 3 represents according to schematic block diagram and the sequential chart of the predictability current feedback system of an embodiment realization;
Fig. 4 is that the exemplary VIL curve of marking and drawing Fig. 3 is compared the sequential chart of original HOLD signal together with a kind of composite signal HOLD+OFFSET of numeral configuration;
Fig. 5 marks and draws the sequential chart of the composite signal HOLD+OFFSET of VIL and a kind of analog configuration than original HOLD signal;
Fig. 6 is the simplification block diagram according to the predictability current feedback system of one embodiment of the invention realization; And
Fig. 7 marks and draws the inductor current signal IL (corresponding to VIL), ISMPL, IHOLD, IOFS and the IDROOP that overlap each other with respect to the zero level that is illustrated as I0 to add PWM and MCK signal, and these signals all are plotted with respect to the time.
Embodiment
By reference to the following description and accompanying drawing can understand better benefit of the present invention, feature and advantage.Those of ordinary skills provide following description so that can implement and utilize the present invention who provides under the background of application-specific and demand thereof.Yet the multiple modification of preferred embodiment will be clearly to those of ordinary skills, and the General Principle that this paper can be limited is applied to other embodiment.Therefore, the present invention is not intended to be subject to the specific embodiment that illustrates and describe herein, and should be given the widest scope consistent with principle disclosed herein and novel feature.
The electric current that flows through the output inductor of switch mode regulator is the parameter useful to various functions, such as output voltage, descends, encircles adjustment, current monitoring and/or report (IMON) etc.There have been many kinds of sensings, measurement or otherwise predicted the method for inductor current.
A kind of method of definite inductor current is monitoring or the voltage of measuring series connection DC resistance (DCR) two ends of output inductor.The DCR sensing has several shortcoming and deficiency.Because output inductor provides from outside with respect to adjuster control integration circuit (IC) usually, so the DCR sensing need to be coupled to output inductor with the additional external assembly for the voltage that detects the DCR two ends usually.For example, external resistor-capacitor (RC) circuit is coupled to output inductor, and the terminal of the external capacitor of RC circuit is used to detect inductor current.The DCR sensing usually also need to be for the NTC (negative temperature coefficient) of thermal drift compensation, and network should be adjusted and carry out thermal compensation thus.The NTC compensation has increased system complexity and cost to the Power Management Design person.
The other method of sensing inductor current is to provide the sense resistor of with output inductor, connecting.Independent sense resistor is the expense cost, and will have the consumption element to be inserted in power train, reduces thus the gross power conversion coefficient.
The buck adjuster generally includes the pair of electrons are device, and this current terminal to electronic device (for example drain electrode, source electrode) in series is coupling between input voltage VIN and reference voltage (for example).Electronic switch can be embodied as the transistor of any suitable type, for example metal-oxide semiconductor (MOS) (MOS) transistor, field-effect transistor (FET), MOSFET, bipolar junction transistor (BJT) and analog, igbt (IGBT) and analog, etc.The sensing of upper end (for example voltage at sensing upper end FET two ends) is difficult to complete at inner (for example in control chip).A kind of high voltage guiding or differential sensing method are used usually also should be accurate as much as possible.The upper end sensing should be the floating signal of reference again take ground.
Guide switch, for example the ratio version of actual switch FET, can produce proportional electric current to the electric current of those power devices.Yet acquisition has suitable common mode range (for example about 12V) and also has the accurate differential signal of transition time single digit nanosecond is difficult.
Drain electrode-source on-state resistance (R of top and bottom FET switch
DS_ON) the differential voltage measurement have the difficulty identical with guide device.
R to lower end FET switch
DS_ONSampling compares the top and bottom device, and both all sample more easy and cost is lower.Also allow the accuracy (for example to outside microprocessor report average inductor current, this average inductor current is the indication of load) of the enough degree of IMON function.The lower end sensing is enough for the IMON function, but for the current feedback of regulating with correctly carry out output voltage decline function usually fast not enough.Especially, due to the sampling time delay comprising during the load transient of transition and load releasing transition is inserted in load, the signal through sampling has larger error component.
As described herein, the gap during all load transient events can be based on the lower end current information through sampling and the ON time estimated also " being filled " of pulse-width modulation (PWM) control signal.Can predict the inductor current level during the load transient between sample event.
Fig. 1 is the simplified block diagram according to the electronic equipment that disposes power system 101 100 of the embodiment of the present invention, and this power system 101 has realization the adjuster 102 of the modulator 103 of predicted current feedback is arranged.Power system 101 produces one or more supply power voltages, and these one or more supply power voltages provide electric power for the other system equipment of electronic equipment 100.In the illustrated embodiment, electronic equipment 100 comprises processor 107 and peripheral system 109, processor 107 and peripheral system 109 all are coupled to receive supply power voltage from power system 101 via bus 105, and bus 105 comprises any combination of power and/or signal transmitter.In the illustrated embodiment, peripheral system 109 for example can comprise system storage 111(, comprise any combination of RAM and ROM types of devices and Memory Controller etc.) and any combination of I/O (I/O) system 113, this input/output 113 can comprise system controller etc., such as graphics controller, interrupt control unit, keyboard and mouse controller, system memory devices controller (for example, being used for the controller of hard disk drive etc.) etc.Illustrated system is exemplary, because it will be understood by those skilled in the art that a plurality of processor systems and support equipment can be integrated on processor chips.
Electronic equipment 100 can be computer or the computing equipment of any type, such as computer system (for example, notebook, desktop computer, net book computer etc.), the media flat-panel devices (for example, Kindle that the iPad that Apple produces, Amazon Company produce etc.), communication equipment (for example, cell phone, smart phone etc.), the electronic equipment (for example, media player, recording equipment etc.) of other types.Power system 101 can be configured to comprise battery (can fill again or non-can filling again) and/or can be configured to together with exchanging (AC) adapter etc. and work.
Fig. 2 is the simplification adaptability block diagram according to the example regulator that comprises modulator 103 102 of an embodiment realization.Adjuster 102 comprises can be to the phase circuit 201 of single phase system or polyphase system realization.Phase circuit 201 comprises gate drivers 203, and it receives pulse-width signal PWM and corresponding top gate signal UG is offered upper end electronic power switch Q1 and corresponding lower end signal LG is offered lower end electronic power switch Q2.Power switch Q1 and Q2 self have in series be coupling in input voltage VIN and common reference voltage GND(wherein GND represent ground connection or any other suitable plus or minus reference voltage level) between current terminal (for example drain electrode and source electrode).Note, GND can represent one or more reference nodes, comprises one or more earth levels or node (such as signal ground, power ground connection, base ground connection etc.) or any other suitable reference voltage level.Switch Q1 and Q2 are coupled at middle phase node 205 places, form thus phase voltage VPH, and the end of output inductor L is coupled to phase node 205 and the other end is coupled to the output node 207 that produces output voltage VO UT.Output capacitor CO and load 209 are coupling between output node 207 and GND.Load 209 represents any one or a plurality of load device, for example arbitrary device of processor 107 and/or peripheral system 109.
The electric current I L that flows through inductor L simulated sensing or otherwise synthetic, and corresponding inductor current sensing signal ISENS is provided for modulator 103.Modulator 103 receives feedback signal VFB and the ILSENS of VOUT and/or indication VOUT, and produces the pwm signal that is used for control phase circuit 201.VFB can be proportional signal that sense or indication VOUT, for example by voltage divider or analog (not shown), is produced.In operation, modulator 103 uses ISENS and VOUT (and/or VFB) and may use other signal that senses or parameter, and especially for the loop such as IMON and voltage drop etc. adjusts function, produces pwm signal.Gate drivers 203 produces UG and LG based on PWM, with conducting or disconnect electronic switch Q1 and Q2 to regulate the voltage level of VOUT.
The present invention describes as switch mode regulator with buck switching mode electric pressure converter, and wherein input voltage is higher than output voltage.Yet be appreciated that, the present invention can be applicable to the electric pressure converter of other type equally, for example boosting type converter (wherein output voltage is boosted to higher with respect to input voltage) and various compound mode, for example buck-boost and/or voltage boosting-reducing etc.Those skilled in that art should be understood that and know, the sensing inductor current can be applicable to the switch mode regulator of any type equally as described herein.
Fig. 3 represents according to schematic block diagram and the sequential chart of the predictability current feedback system of an embodiment realization.The output stage of adjuster 102 is illustrated as and comprises switch Q1, Q2, output inductor L, output capacitor CO and load 209.Sampling and the drain electrode that keeps (SNH) network 301 to have being coupled to Q2 (lower end FET) and positive pole input and the negative pole of source electrode are inputted, effectively the level of VPH sampled and in its output, to provide corresponding HOLD signal when the Q2 conducting.The exemplary legend of HOLD signal in operation has been described in the output of the diagram of SNH network 301, and when PWM this output and represent that the relevant voltage signal VIL of inductor current is overlapping when low.While being high, VIL dots in the drawings, does not wherein directly monitor the voltage of Q2 both sides as PWM.While when in the Q2 conducting, the voltage of Q2 both sides being sampled, VIL illustrates with solid line.Generally speaking, when PWM uprises, Q1 conducting and Q2 cut-off, thus make phase node 205 be coupled in input voltage VIN and therefore make the input side of inductor L be coupled in input voltage VIN, make thus the upward change of inductor current.When the PWM step-down, Q1 ends and the Q2 conducting, thereby makes phase node 205 be coupled in GND, and inductor current is become to declivity.
VIL generally is derived as the R of Q2
DS_ONMultiply by inductor current IL, or VIL=ILR
DS_ON.Therefore VIL is as PWM sign inductor current IL when low.When PWM was conducting, VIL was illustrated as dotted line, because this part of VIL is without sampling.When PWM is cut off and during the Q2 conducting, the voltage of Q2 both sides is by 301 samplings of SNH network and subsequently sampled value is remained on the output of Q2, until export next retention value.Generally speaking, at the duration of the ON time of Q2 between sampling period, have the nominal time cycle during limit, wherein 301 outputs of SNH network are greatly about the maintenance sampled value in the centre positions of name time cycle.Point along the HOLD signal represents when each retention value finishes to form the HOLD signal between sampling period.
When low, SNH network 301 only samples to form the HOLD signal to VIL as Q2 conducting and PWM.Originally when load when low, the HOLD signal is generally accurately and follows the DC level (and there is no ripple) of VIL.Yet, inserting transition in response to load, VIL upwards skips to higher level, and the HOLD signal remains on as lower level shown in time t1 simultaneously.Pwm signal remains conducting for a long time, thereby makes VIL increase to higher level.Due to the Q2 remain off, the level of sampling before HOLD is maintained at, this causes HOLD and as larger difference or error between the VIL shown in time t1.When PWM is finally dragged down and Q2 again during conducting, again VIL to be sampled by SNH network 301, and export another retention value, this makes the HOLD signal skip to higher level.
Remove transition in response to load, similar HOLD and the difference between VIL occur, and approximately occur in as shown in the figure time t2.In this case, only have a retention value to be output when the Q2 conducting, and Q2 keeps conducting in longer cycle, thereby make VIL be down to lower level.Because VIL keeps conducting for a long time, so the HOLD signal remains height, and this causes between HOLD and VIL the relatively large difference at time t2.While being high again, Q2 cut-off and Q1 conducting, so that the HOLD signal does not still change as PWM.Finally, the PWM step-down, thus making the Q2 conducting and export a new HOLD value, the HOLD signal skips to new DC level thus.
In short, HOLD follows VIL substantially, but deviates from significantly in VIL during load transient, comprises when load insertion and load are removed, as shown in time t1 and t2 in figure.
An input of predictable current feedback (PCF) network 303 is received in the HOLD signal of SNH network 301 outputs place, and its another input receives PWM, and its output provides the OFFSET signal.Combiner (for example adder) 305 adds to HOLD to form the signal HOLD+OFFSET through combination with OFFSET.PCF network 303 is configured to based on the level of PWM and HOLD prediction VIL and produces OFFSET, so that the signal of combination is more accurately characterizing of inductor current.The whole bag of tricks that is used for realizing PCF network 303 is provided, has comprised digital scheme and modeling scheme.
Fig. 4 is that the exemplary VIL curve of marking and drawing Fig. 3 is compared the sequential chart of original HOLD signal together with a kind of composite signal HOLD+OFFSET of numeral configuration.The digital signal of this combination represents with solid line, and wherein deviating from the drawings of original HOLD signal dots.ON time (the t of PCF network 303 monitoring pwm signals
ON) and with predetermined nominal ON time cycle t
ON_NOMCompare.Work as t
ONExceed t
ON_NOMOne Delta Time cycle Δ t
ON(t
ON_NOM+ Δ t
ON) time, it is asserted to a predetermined increment bias OFFON with OFFSET, and this increment bias OFFON is added to HOLD.As PWM at another Delta Time cycle Δ t
ON(t
ON_NOM+ 2 Δ t
ON) while keeping conducting, the OFFSET signal is doubly increased to doubles bias OFF
ON(2OFF
ON), this bias is added to HOLD increases another OFF with the signal that further makes combination
ONIncrement.As PWM at another Delta Time cycle Δ t
ON(t
ON_NOM+ 3 Δ t
ON) while keeping conducting, the OFFSET signal is doubly increased to and is three times in bias OFF by three times
ON(3OFF
ON), this bias is added to SNH to be increased with the signal that further makes combination.When PWM step-down and the final conducting of Q2, the signal through making up is held, until obtain new sampling.
After load remove between transient period, can carry out identical process.(t deadline of PCF network 303 monitoring pwm signals
OFF) and with predetermined nominal cycle deadline t
OFF_NOMCompare.Work as t
OFFExceed t
OFF_NOMOne Delta Time cycle Δ t
OFF(t
OFF_NOM+ Δ t
OFF) time, it is asserted to a predetermined increment bias OFF with OFFSET
OFF, this increment bias OFF
OFFBe added to HOLD.As PWM at another Delta Time cycle Δ t
OFF(t
OFF_NOM+ Δ t
OFF) during remain off, the OFFSET signal is doubly increased to doubles bias OFF
OFF(2OFF
OFF), this bias is deducted further to make the signal of combination to reduce another OFF from HOLD
OFFIncrement.When PWM conducting next time, this process repeats.
In general, for numeral configuration, than the predetermined name time cycle more longways when conducting or cut-off, HOLD is in the conducting that increases or increase or reduce an incremental change after cycle deadline as PWM.In one embodiment, the time cycle Δ t of each increase
ONFix, and the bias OFF of each increase
ONAlso fix, the HOLD signal through adjusting rises with fixing speed ladder when the PWM conducting thus.The time cycle that increases and biasing are for a customized configuration structure.Similarly, the time cycle Δ t of each increase
OFFFix, and the bias OFF of each increase
OFFAlso fix.In another embodiment, the time cycle of increase and/or bias can change.In any case, the time cycle that design time increases and corresponding biasing, so that composite signal HOLD+OFFSET closer follows VIL than independent HOLD.In one embodiment, can set adaptively bias OFF by modulator 103 based on operating parameter (for example voltage level of VIN) and component value
ONAnd OFF
OFF.
Fig. 5 marks and draws the sequential chart of the composite signal HOLD+OFFSET of VIL and a kind of analog configuration than original HOLD signal.The analog signal of this combination represents with solid line, and wherein deviating from the drawings of original HOLD signal dots.In one embodiment, in case the ON time of PWM exceeds predetermined nominal ON time cycle t
ON_NOM, for example in response to load, inserting transition, the OFFSET signal is just based on the upward change of simulation ratio of last lower end sampling, and the VIL speed upward change of HOLD+OFFSET to estimate thus, until PWM is cut off.After the PWM cut-off, sample normally and keep operation to continue, do not exceed t simultaneously
ON_NOMWith predetermined nominal cycle deadline t
OFF_NOM.Exceed predetermined nominal cycle deadline t when the deadline of PWM
OFF_NOMThe time, for example in response to load, remove transition, SNH network 301 is operated in to be followed the tracks of and Holdover mode, and this mode tracking VIL is until assert PWM next time.When next when time t1 asserts PWM, retention value is maintained at this level, until export next retention value, and PWM normal sampling and keep operating period at time t2 as shown in figure for cut-off.
Fig. 6 is the simplification block diagram according to the predictability current feedback system 600 of one embodiment of the invention realization.PWM is illustrated as the grid of driving Q1 and by phase inverter 603 paraphase, this phase inverter 603 provides the paraphase version of PWM in its output to the grid of Q2, or
This is a kind of simplification and functional descriptions of operation, and wherein for example the gate drivers of gate drivers 203 generally is used for the driving power switch.Analog-digital converter (ADC) 601 samples at PWM phase voltage VPH (or VIL) to the Q2 both sides when low.ADC601 provides digital current sampled value I in its output
SMPL, this digital current sampled value I
SMPLBe provided for the input of memory 605.Memory 605 provides clock by the memory clock signal MCK of output place of 2 input AND doors 629, and 2 input AND doors 629 receive in its input
With signal DO.
Provide by the output of phase inverter 603 or by the output of another phase inverter 613.When DO is asserted to height and while
When high, the I that memory 605 will receive in its input in its output
SMPLValue remains digital current retention value I
S﹠amp; H.I
S﹠amp; HBe provided for the input of I2C IMON report blocks 607, I2C IMON report blocks 607 need not to proofread and correct external devices for the report inductor current through keeping version.
D-A converter (DAC) 609 receives I in its input (or the input of corresponding numeral)
S﹠amp; H, and at it, export analog current value I
HOLDOffer electric current summing junction 610.I
S﹠amp; H(numeral) and I
HOLD(simulation) is corresponding with previously described HOLD signal.Node 610 output drop-out current I
DROOP, I
DROOPBe provided for decline network (not shown) to carry out the decline function.As those skilled in that art understood, the decline function was because becoming in the premeditated adjusting of the voltage level to output voltage VO UT of load.Requirement provides than by I
HOLDThe VIL more accurately that provides characterizes.As described further herein, pass through bias current I based on the predictability current feedback
OFSTo I
DROOPRegulate, described predictability current feedback is used for providing more accurately characterizing of inductor current IL.Therefore, I
DROOP=I
HOLD+ I
OFS, I wherein
DROOPCharacterize previously described composite signal HOLD+OFFSET (DIG).Be noted that as described further herein, for lower COUNT value, I
OFSBe zero.
PWM is provided for edge and detects the input of piece 617, and this edge detects piece 617 and has the output of zero clearing (CLR) input that is provided for the counter 619 that makes progress.Upwards counter 619 has clock input (CLK), and this clock input (CLK) receives has a frequency F by what clock generator 621 provided
CLKClock signal clk.In one embodiment, CLK has corresponding over-sampling frequency (F for example
CLK=50MHz) over-sampling clock, although also can consider the clock frequency that substitutes.Therefore, upwards counter 619 at the rising edge of PWM with trailing edge all is cleared and with by F
CLKThe speed of determining is counting (from predetermined minimum value or zero) upwards, and digital output value COUNT is provided.COUNT is provided for decoder 612, and the output of this decoder 612 is with digital bias value I
OFFOffer the corresponding input of another DAC611.DAC611 has sampling input, the reception that receives PWM
Maintenance input (via phase inverter 613) and simulation bias current signal I is provided
OFSAnalog current output, bias current signal I
OFSI
OFFAnalog version.When PWM is asserted to switch 615 closures when high, and when closed switch 615 with electric current I
OFSOffer node 610.When PWM is asserted to I when high
DROOPBe confirmed as I
HOLDAdd I
OFS, as PWM I when low
DROOPBe confirmed as I
HOLD(when switch 615 disconnects).
Numeral COUNT value is provided for the input of decoder 627, and another input of this decoder 627 receives the digital version of dutyfactor value D.Piece 623 detects input voltage VIN and output voltage VO UT, and the analog version of duty ratio is defined as D=VOUT/VIN.The output of piece 623 is provided for the input of ADC625, and ADC625 offers decoder 627 with the digital version of D.In the illustrated embodiment, as COUNT=((1-D)/2) TSF
CLKThe time, decoder 627 its output make DO be high impulse to AND door 629, wherein TS is the switching cycle of adjuster 102.
In general, upwards counter 619 is used to provide COUNT, the duration of pulse duration when COUNT indication PWM is in conducting (for example high) and is in cut-off (for example low).Decoder 627 use COUNT determine the PWM suitable retention time (for example intermediate point) of low time, and while Q2 conducting thinks that memory 605 provides clock with the value I with through sampling
SMPLRemain I
S﹠amp; H, I
S﹠amp; HThe indication inductor current.While being high, decoder 612 use COUNT follow the tracks of t as PWM
ON_NOMWith Δ t
ON, and with I
OFFBe asserted to proper level with drop-out current I
DROOPAdjust a suitable amount of bias I
OFS.When PWM exceeds the nominal time quantum t that occurs when upwards counter 619 arrives the nominal count value of being determined by decoder 612
ON_NOMThe time, regulate I according to following equation
OFS: I
OFS=(VIN-VOUT) TS/ (2L)+Δ t
ON(VIN-VOUT)/L, wherein " L " is the inductance of output inductor L, and Δ t
ONTo describe the identical fixed increment time cycle with front.
Fig. 7 marks and draws inductor current signal IL (corresponding with VIL), the I that overlaps each other with respect to the zero level that is illustrated as I0
SMPL, I
HOLD, I
OFSAnd I
DROOPAnd PWM and MCK signal are all with respect to the sequential chart of time.As PWM while being high, IL is upward straighten the PWM step-down till, for example be illustrated as initial time t0, IL becomes to declivity to returning there.When PWM becomes when low at time t0, the sampled value I of inductor current
SMPLSaltus step is with the level of reflection IL.When PWM when low (thus
For height) and IL while to declivity, becoming, I
SMPLValue is followed IL.As COUNT=((1-D)/2) TSF
CLKAnd when PWM was low, for example such shown in time t1, decoder 627 made the DO pulse paramount, and this also makes the MCK pulse paramount at time t1.Memory 605 at time t1 with I
S﹠amp; HAssert into I
SMPLThrough retention value, and electric current I
HOLDRemainder in circulation keeps indication I
S﹠amp; HValue therefore (and at the I of time t1
SMPLRetention value).Operate in next circulation shown in time t2 and repeat by this way, wherein MCK forms pulse with I once again at time t2
S﹠amp; HRemain on I
SMPLValue.So, at the ON time t of PWM
ONDo not exceed t
ON_NOMThe time, I
HOLDGenerally follow the tracks of the mean value of IL and there is no load transient.Within this time, electric current I
DROOPGenerally follow I
HOLD.
Pwm signal uprises again at time t3, and PWM keeps comparing t at time t4 in this circulation
ON_NOMHave more Delta Time t
ON, transition is inserted in this indication load.Time t4 is the time t with respect to time t3
ON_NOM+ Δ t
ON.At time t4, I
OFSRecruitment I
DC+ I
INC, I wherein
DCIndication I
HOLDInitial DC amount and I
INCIt is the increment current level.Therefore at time t4, I
DROOPFrom I
HOLDLevel skips to I
HOLD+ I
DC+ I
INCHigh value, this high value is the about same level at the IL of time t4.As PWM for each additional incremental time Δ t
ONWhile keeping conducting, another increment current amount I
INCBe added to I
OFS, as shown in time t5 in figure.Due to I
DROOP=I
HOLD+ I
OFS, I
DROOPIncrease identical amount.Therefore, I when the PWM maintenance is high
DROOPAnd I
OFSAll with step-wise manner, increase, and I
HOLDAt I
SMPLLast retention value remain unchanged.Therefore, I
DROOPIncrementally increase with than I
HOLDFollow more closely IL.
At ensuing time t6, the last step-down of PWM so that IL again start to become to declivity.I
SMPLUpwards skip to the new level of IL and at it, follow IL when declivity becomes, as described previously.I
DROOPPosition at the peak level near IL temporarily remains unchanged, and subpulse is paramount again until MCK is at time t7.At time t7, I
OFSTo returning step-down to I0, I
HOLD(it is I to skip to the new level of IL
SMPLAnd I level at time t7),
DROOPSkip to I downwards
HOLDLevel.I
HOLD, and then I
DROOP, the average level of all following IL, until next load transient event.
At time t6, IL deviates from I
HOLDReach a significant quantity, thus I
HOLDTemporarily inaccurately reflect IL, until ensuing time t7.As shown in the figure, at time t4 between time t7, I
OFSWith I
HOLDAddition allow I
DROOPFollow more accurately IL.Although clearly do not illustrate in Fig. 7, responsive load is removed the transition meeting identical operation, I is in this case occurred
OFSAlong the negative direction stepped change with respect to I
HOLDReduce I
DROOPTo follow the tracks of more accurately IL.
Although with reference to some preferred version of the present invention, the present invention has been carried out enough detailed description, yet also can consider other version and become example.Those skilled in that art be to be understood that they can use easily disclosed theory and specific embodiment as design with the basis of revising other structure so that the present invention to be provided identical purpose, and do not break away from the spirit and scope of the present invention as following claims definition.
Claims (20)
1. predictability current feedback system that is used for switch mode regulator comprises:
Sampling and keep network, be used for the voltage of the power switch both sides of described adjuster is sampled and is provided as the inhibit signal of its indication; And
Predictability current feedback network, described predictability current feedback network adds to described inhibit signal based on the duration of the pulsewidth of the pulse control signal that is formed by described adjuster with bias-adjusted.
2. predictability current feedback system as claimed in claim 1, is characterized in that, the described inhibit signal of described predictability current feedback network adjustment is with the more accurately judgement of electric current that the output inductor by described adjuster is provided.
3. predictability current feedback system as claimed in claim 1, is characterized in that, described predictability current feedback network adds to described inhibit signal with an amount of bias after each at least one the Delta Time cycle after the name time cycle in described pulsewidth.
4. predictability current feedback system as claimed in claim 1, is characterized in that, described bias-adjusted is included in during described pulsewidth the predetermined increment bias-adjusted for each predetermined Delta Time cycle.
5. predictability current feedback system as claimed in claim 1, is characterized in that, described bias-adjusted comprises time varying signal, and described time varying signal changes and changes based on the expection of the electric current of the output inductor that flows through described adjuster.
6. predictability current feedback system as claimed in claim 1, it is characterized in that, described pulse control signal is switching back and forth between conducting and cut-off, wherein said predictability current feedback network adds to described inhibit signal with the first amount of bias at each at least one first Delta Time of the first name time cycle after the cycle in described pulse control signal conducting, and described predictability current feedback network all after dates of each at least one second Delta Time after the second name time cycle in described pulse control signal cut-off deduct the second amount of bias from described inhibit signal.
7. predictability current feedback system as claimed in claim 1, it is characterized in that, described pulse control signal is switching back and forth between conducting and cut-off, wherein said predictability current feedback network adds to described inhibit signal with time varying signal in the first name after the time cycle in described pulse control signal conducting, and described sampling and keep network to follow the voltage of described power switch both sides in described pulse control signal cut-off after the second nominal time cycle.
8. predictability current feedback system as claimed in claim 1, is characterized in that, also comprises:
Counter network, described counter network provide the indication described pulse control signal the ON time duration and deadline duration count value;
Described sampling and keep network to comprise the first decoder, described the first decoder determine when to keep during for cut-off when described pulse control signal value through sampling based on described count signal during described deadline duration; And
Described predictability current feedback network comprises the second decoder, described the second decoder determines based on described counting when the described conducting duration of described pulse control signal after the predetermined name time cycle exceeds each Delta Time cycle, and is provided as the corresponding bias of its indication.
9. predictability current feedback system as claimed in claim 8 is characterized in that:
Described sampling and maintenance network comprise:
The first transducer, described the first transducer becomes sampled value with the voltage transitions of described power switch both sides;
Memory, described memory receive described sampled value and response is indicated retention value is provided from the maintenance of described the first decoder; And
The second transducer, described the second transducer converts described retention value to the maintenance electric current; And
Wherein said predictability current feedback network comprises the 3rd transducer, and described the 3rd transducer converts described bias to bias current, and described bias current is added to described maintenance electric current in the described conducting duration of described pulse control signal.
10. electronic equipment comprises:
Modulator, described modulator receive output voltage sensing signal and current sensing signal and the formation pulse control signal as its indication, are used for the control switch adjuster with regulation output voltage;
Sampling and keep network, be used for the voltage of the phase node of described switching regulaor is sampled and is provided as the inhibit signal of its indication; And
Predictability current feedback network, described predictability current feedback network provides bias-adjusted to regulate described inhibit signal based on the pulsewidth duration of described pulse control signal, thereby forms described current sensing signal.
11. electronic equipment as claimed in claim 10, is characterized in that, also comprises:
Output node, described output node forms described output voltage; And
Load, described load coupling is to described output node.
12. electronic equipment as claimed in claim 11, is characterized in that, described load comprises the processor that is coupled to memory.
13. electronic equipment as claimed in claim 10 is characterized in that:
Described switching regulaor comprises:
Upper end switch, described upper end switch are coupling between input voltage node and described phase node;
Lower end switch, described lower end switch are coupling between described phase node and datum node;
Output inductor, described output inductor are coupling between described phase node and output node,
Described output node forms described output voltage; And
Conducting when described upper end switch is high at described pulse control signal, and described lower end switch is in the conducting when low of described pulse control signal;
Wherein said sampling and keep network the voltage of described lower end switch both sides to be sampled when low at described pulse control signal, and form the described inhibit signal as its indication; And
Described predictability current feedback network is configured to after a name time cycle, each Delta Time cycle be setovered and incrementally adds to described inhibit signal one while being high at described pulse control signal.
14. electronic equipment as claimed in claim 10 is characterized in that:
Described switching regulaor comprises:
Upper end switch, described upper end switch are coupling between input voltage node and described phase node;
Lower end switch, described lower end switch are coupling between described phase node and datum node;
Output inductor, described output inductor are coupling between described phase node and output node, and described output node forms described output voltage; And
When described pulse control signal described upper end switch conduction while being high, when described pulse control signal described lower end switch conduction when low;
Wherein said sampling and keep network the voltage of described lower end switch both sides to be sampled when low at described pulse control signal and form described inhibit signal as its indication; And
Described predictability current feedback network be configured to described pulse control signal while being high after the name time cycle will the time become biasing and add to described inhibit signal.
15. the method that the predictability current feedback is provided for switch mode regulator comprises:
During the first state of described pulse control signal, the voltage of power switch both sides is sampled, and be provided as the retention value of its indication; And
During the second state of described pulse control signal, biasing is added to described retention value in response to load transient.
16. method as claimed in claim 15, is characterized in that, described interpolation biasing is included in each first Delta Time after the first name time cycle during the second state of described pulse control signal and adds one first bias after the cycle.
17. method as claimed in claim 15, is characterized in that, also is included in each second Delta Time after the second name time cycle during the first state of described pulse control signal and deducts the second bias from described retention value after the cycle.
18. method as claimed in claim 15, is characterized in that, describedly adds that a biasing is included in during the second state of described pulse control signal and will become for the moment bias add to described retention value after the first name time cycle.
19. method as claimed in claim 18, is characterized in that, follows the voltage of described phase node to regulate described retention value during also being included in the first state of described pulse control signal after the second name time cycle.
20. method as claimed in claim 15, is characterized in that, describedly retention value is provided and describedly biasing is added to described retention value comprises that producing a decline control signal based on load descends to control output voltage.
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| US201261646007P | 2012-05-11 | 2012-05-11 | |
| US61/646,007 | 2012-05-11 | ||
| US13/531,751 US8901910B2 (en) | 2012-05-11 | 2012-06-25 | System and method of predictive current feedback for switched mode regulators |
| US13/531,751 | 2012-06-25 |
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| CN103391002A true CN103391002A (en) | 2013-11-13 |
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