CN103389962A - CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture - Google Patents
CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture Download PDFInfo
- Publication number
- CN103389962A CN103389962A CN2013103217947A CN201310321794A CN103389962A CN 103389962 A CN103389962 A CN 103389962A CN 2013103217947 A CN2013103217947 A CN 2013103217947A CN 201310321794 A CN201310321794 A CN 201310321794A CN 103389962 A CN103389962 A CN 103389962A
- Authority
- CN
- China
- Prior art keywords
- data
- network node
- network
- node
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a CDMA (code division multiple access) on-chip network architecture based on a standard orthonormal basis and a realization method of the CDMA on-chip network architecture. The CDMA on-chip network architecture and the method mainly solve the problem that in the prior art, the on-chip network architecture cannot reduce the resource waste or reduce the power consumption while ensuring the transmission quality and the transmission efficiency. The CDMA on-chip network architecture based on the standard orthonormal basis comprises a network transmitting module, an arbitration module and more than two processing units, wherein the network transmitting module and the arbitration module are integrated, and the processing units are connected with the network transmitting module and the arbitration module respectively through network nodes. Through the scheme, the CDMA on-chip network architecture and the method have the advantages that the goals that the transmission quality and the transmission efficiency are high, in addition, the resource waste and the power consumption are low are reached, and high practical value and popularization value are realized.
Description
Technical field
The present invention relates to a kind of on-chip network structure of CDMA based on orthonormal basis and its implementation.
Background technology
Along with processor quantity integrated on one single chip increases, multicomputer system has used network-on-chip (Network-on-Chip, NoC) framework to solve the problem that the inter-processor communication amount is large and communication delay is high more and more.
Existing on-chip network structure mainly is included as the traditional on-chip network structure based on cache way, this kind on-chip network structure can solve the problem of data traffic between node, and can promote certain data transfer delay, but to the data transmission between two nodes, can't guarantee the stability of data transfer delay, namely, internodal transmission delay is a variable, and is subject to the impact of network congestion.Therefore, be not suitable for the communications applications of requirement assurance stable transfer delay based on the network-on-chip of cache way, namely can't meet the requirement of communications applications on service quality QoS (Quality of Service).
In order to guarantee service quality, a kind of based on code division multiplexing CDMA(Code Division Multiple Access) on-chip network structure of technology is suggested.In the code division multiplexing on-chip network structure, each sending node module first uses different orthogonal codes to encode to data before sending data, then the stacked data after forwarding module will be encoded is added up, and finally superposed signal is transferred to each receiver module by shared channel.Orthogonality due to coding codeword, raw data can obtain by the decoding of the orthogonal code with corresponding superposed signal at receiving node, owing to using the transmission channel of sharing, internodal data transmission can not produce congested, so in the code division multiplexing on-chip network structure, internodal data transfer delay is a constant, therefore, uses the network-on-chip technology based on code division multiplexing can meet the needs of communications applications to service quality.
Yet, although based on code division multiplexing technology on-chip network structure, good performance is arranged on service quality and data transfer delay, but because current code division multiplexing on-chip network structure generally all adopts the Walsh code, data are encoded, so exist following defect: the Walsh code of N bit length can only provide N-1 codified code word, and N=2
n, wherein n is integer, and n〉and 1, so use the Walsh code to be easy to cause the problem of the low and wasting of resources of code word utilization.For example, because the Walsh of 16 bit lengths can only provide 15 codified code words, therefore, the NoC system of 16 nodes, need the Walsh code of 32 bit lengths to encode, and causes finally 16 coding codewords to be wasted; When expansion the transmission of data bit wide, area and flash-up that the Walsh coding/decoding module consumes are very large.
Summary of the invention
The object of the present invention is to provide a kind of on-chip network structure of CDMA based on orthonormal basis and its implementation, mainly solve the on-chip network structure that exists in prior art can't reduce the wasting of resources and reduce power consumption when guaranteeing transmission quality and transfer efficiency problem.
To achieve these goals, the technical solution used in the present invention is as follows:
, based on the CDMA on-chip network structure of orthonormal basis, comprise the forwarded module and the arbitration modules that integrate, two above processing units that are connected with arbitration modules by network node and forwarded module respectively.
Specifically, described two above processing units are connected with respectively the Network-Node Interface that is connected with network node, described network node comprises and the two-way data buffering module that is connected of Network-Node Interface, with the two-way data transmit-receive module that is connected of data buffering module, described data transmit-receive module is connected and is connected with arbitration modules with the forwarded module.
As preferably, described processing unit is general purpose microprocessor, hardware-accelerated core or dsp processor.
Based on above-mentioned device blocks, the invention provides a kind of implementation method of the on-chip network structure of the CDMA based on orthonormal basis, comprise the following steps:
(1) on two above processing units, Network-Node Interface is set respectively, the Network-Node Interface of each processing unit is connected on same forwarded module and arbitration modules by a network node respectively, and with the forwarded module together with arbitration modules is integrated in;
While (2) carrying out data transmission between processing unit, the processing unit that carries out the data transmission is sent to coupled network node by coupled Network-Node Interface with data to be transmitted and purpose processing unit address, sending data to the forwarded module by network node after through arbitration modules, allowing processes, then data after treatment are sent to the network node that is connected with the purpose processing unit, the purpose processing unit carries out data receiver by the Network-Node Interface on it.
Described step (2) specifically comprises the following steps:
The network node that (2a) with the processing unit that carries out the data transmission, is connected is initiated the output application to arbitration modules when the data that receive processing unit send instruction;
(2b) arbitration modules judges whether corresponding purpose processing unit of this moment receives only a data transfer request, encode and merge if allow network node to send data to the forwarded module, will encode afterwards with merge after data transmission to the network node that is connected with the purpose processing unit; According to the round-robin algorithm, select the permission output node if not, respectively arbitration result is sent to simultaneously and carries out the data network node that sends and the network node that carries out data receiver, the network node that obtains afterwards arbitrating permission carries out data output, carry out the network node of data receiver according to reception orthogonal code corresponding to arbitration result configuration, and carry out the data reception;
The network node that (2c) carries out data receiver receives the laggard row decoding of data and reduction.
Further, in step (2), if the forwarded module receives from network node and sends and next forwarding data, according to the orthogonal code of distributing to the corresponding network node, forwarding data is encoded, and the data after encoding according to XOR merge, and the data transmission after merging by shared channel afterwards is to the network node that respectively receives.
Further, described data encoding specifically comprises the following steps:
(2d) to each, carry out a different set of orthonormal basis code word of network node distribution that data send;
The coded data that (2e) according to the logic XOR, will carry out each network node that data send merges;
(2f) data transmission after merging is to respectively carrying out the network node of data receiver.
Described step (3) specifically comprises the following steps:
(2c1) carry out the network node of data receiver according to the corresponding orthonormal basis code word of arbitration information configuration that obtains from arbitration modules;
Logic and operation is carried out in the fused data that (2c2) will receive from the forwarded module and the corresponding orthonormal basis code word step-by-step of carrying out the network node of data transmission, obtains decoded data;
(2c3) decoded data are added up, realize reduction.
In the present invention, described network node by with the two-way data buffering module that is connected of Network-Node Interface, one end and data buffering module be two-way to be connected, the other end forms with the data transmit-receive module that the forwarded module is connected with arbitration modules, described processing unit carries out data receiver or all will wait to receive while sending or data to be sent deposit the data buffering module in, then receives or transmission processing.
Compared with prior art, the present invention has following beneficial effect:
(1) than traditional Walsh code coded system, use the present invention can solve the problem of the low and wasting of resources of code word utilization factor, have in actual applications good adaptability and dirigibility, realize that difficulty is lower, meets technical need.
(2) simple than based on the Walsh code of encoding and decoding structure of the present invention, therefore when expansion the transmission of data bit wide, can saving chip area and power consumption based on the coding/decoding module of orthonormal basis, be conducive to realize the cost control of code division multiplexing network-on-chip, cost performance is higher, accords with the demands of the market.
(3) the present invention is by the setting to system architecture, both can carry out fast data interaction between processing unit, the transmission delay that can guarantee again data between processing unit is fixed value, so the present invention needing to go for the communications applications of quality of service guarantee, in addition, than traditional CDMA NoC framework, the present invention is simple in structure, can reduce design difficulty, saves the time in design and Qualify Phase consumption, and at implementation phase, can Cost reduction and realize difficulty.
(4) in the present invention, adopt the round-robin algorithm to select the permission output node, synchronization, for same receiving node, only have a sending node to obtain output and allow, therefore can guarantee the correct reception of data, simultaneously can guarantee that each node obtains the fairness of permission, and can avoid node to can not get allowing to occur " dying of hunger " phenomenon, mode is ingenious, fair, realistic demand.
Description of drawings
Fig. 1 is the NoC configuration diagram of Star topology in the present invention.
Fig. 2 is the concrete configuration diagram that is connected of processing unit and network node in the present invention.
Fig. 3 is coding scheme schematic diagram of the present invention.
Fig. 4 is decoding configuration diagram of the present invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples, and embodiments of the present invention include but not limited to the following example.
Embodiment
The problem of and the wasting of resources low for the code word utilization factor that solves traditional Walsh code coded system, as shown in Fig. 1 ~ 4, the present invention has designed a kind of on-chip network structure of CDMA based on orthonormal basis, coded system by the Application standard orthogonal basis has effectively increased adaptability and dirigibility in actual applications, and can saving chip area and power consumption, be conducive to realize the cost control of code division multiplexing network-on-chip.
As shown in Figure 1 and Figure 2, the present invention includes a plurality of processing units, be arranged on the Network-Node Interface on processing unit, with the two-way data buffering module that is connected of Network-Node Interface, with the two-way data transmit-receive module that is connected of data buffering module, forwarded module and arbitration modules with the two-way connection of data transmit-receive module, together with being integrated in.
Wherein, data buffering module and data transmit-receive module have formed network node, because all processing units all are connected in same forwarded module, so the present invention design is based on the structure of Star topology code division multiplexing network-on-chip, in order to realize the exchanges data between each processing unit.In the present invention, processing unit can be selected general processor core, DSP core, hardware-accelerated core etc.
The network node that the data transmission is carried out in definition is sending node, and the network node that carries out data receiver is receiving node, and each processing unit is carried out data transmission in the following manner:
if a processing unit need to send data to other processing units, by coupled Network-Node Interface, data to be sent and corresponding purpose processing unit number (are indicated, destination) send to network node, complete data transmission by network node, namely, after sending instruction, the data that network node receives processing unit at first to arbitration modules, initiate the output application, in order to prevent that a plurality of sending nodes from sending data to same receiving node and causing data that confusion occurs, each network node needed first to arbitration modules, to transmit application before sending data, guarantee that synchronization only has a sending node carrying out data transmission for a receiving node, by the time after transmission application is allowed, the network node data of carrying out the data transmission send to the forwarded module, by the forwarded module with data encoding, merge and be transferred to receiving node, if the forwarded module receives the forwarding data that sends from network node, according to the orthogonal code of distributing to the map network node, forwarding data is encoded, and the data after encoding carry out XOR and merge, the data after merging finally by a shared transmission to all reception network nodes,
if network node receives the data receiver order of processing unit, check in the data buffering module whether be ready to corresponding data,, if be ready to, send the data to processing unit, otherwise continue to receive the fused data that obtains from the forwarded module, and to the decoding data buffer memory, when network node is exported application to arbitration modules, if arbitration modules receives the output request of a plurality of sending nodes simultaneously, according to the Round-Robin algorithm, it is the timeslice round robin algorithm, select the node that allows output, this algorithm can guarantee synchronization, for same receiving node, only having a sending node to obtain output allows, guarantee that simultaneously each node obtains the fairness of permission, can avoid node to can not get allowing to occur " dying of hunger " phenomenon, after arbitration modules is completed arbitration, notify simultaneously sending node and receiving node with arbitration result, sending node starts data output after receiving arbitration result, after receiving node obtains arbitration result,, according to reception orthogonal code corresponding to arbitration result configuration, guarantee to be correctly decoded.
In above-mentioned, the forwarded module is encoded to data in the following manner:
At first, for each sending node distributes a different set of orthonormal basis code word, for example: sending node n correspondence orthonormal basis code word n, when coding, the raw data of sending node is encoded according to the order of 1 bit 1 bit, be that each bit raw data all needs and each bit step-by-step of corresponding orthonormal basis is carried out logic and operation and obtained coded data, for example,, if 1 bit raw data is encoded through 8 bit standard orthogonal basis code word logical ands, can obtain 8 bits of encoded data afterwards; Then, the coded data step-by-step of different sending nodes is merged by the logic XOR; Finally, the data transmission after merging is arrived each receiving node.
Receiving node carries out decoding to data in the following manner:
As shown in Figure 3, at first, receiving node is according to the orthonormal basis code word of the corresponding sending node of sending node arbitration information configuration that obtains from arbitration modules; Then, the fused data that receives from the forwarded module is carried out decoding, when decoding, order according to 1 bit 1 bit, logic and operation is carried out in the orthonormal basis step-by-step of fused data and corresponding sending node, for example, 8 bit standard orthogonal basis code words will be carried out logic and operation with 8 encoded data pits, obtain 8 bit decoded signals; Afterwards, decoded signal is added up, after cumulative the end, the data of output are the raw data of sending node.In the present invention, preferably use totalizer to add up.
Specific works step of the present invention is as follows:
Step 1: processing unit produces the transmission needs according to executing the task, at this moment, processing unit is given an order to the network node that correspondence connects, if processing unit need to send data to other processing units, to network node, send the identification number that sends order and purpose processing unit, and deposit data to be sent in data buffering module wait network node and send; If processing unit need to receive the data of other processing units, to network node, send the identification number that receives order and purpose processing unit, after receiving DSR and depositing data buffering in, processing unit reads the data that need from the data buffering module when network node;
Step 2: after network node receives order and purpose processing unit identification number,, if send order, to arbitration modules, initiate the output application, and wait for that the output of arbitration modules feedback allows; If receive order, check the data that whether receive the alignment processing unit,, if receive, data are deposited in the data buffering module, and the notifier processes unit reads, if not yet receive data, the notifier processes unit is waited for, simultaneously, network node continues the data in wait and reception forwarded module,, until receive the data that need and deposit the data buffering module in, namely activate processing unit and read;
Step 3: arbitration modules receives output and asks, and, if arbitration modules has been fed back the output permission this moment, keeps current output to allow, and makes the sending node wait of other all initiation output requests; , if arbitration modules is feedback output permission at this moment,, according to the output request that receives, export and allow according to round-robin algorithm feedback of selection from the sending node of all initiation output applications, and other sending nodes are waited for; Simultaneously, the object information notice receiving node that arbitration modules will be arbitrated, facilitate receiving node to carry out corresponding decodes codeword configuration;
Step 4: sending node is read the data in the data buffering module in order, and to the forwarded module, is sent after receiving the output permission of arbitration modules;
Step 5: the data from different sending nodes that the forwarded module will be received are encoded with various criterion orthogonal basis code word corresponding to each sending node respectively, during coding, each Bit data that receives is all carried out logic phase and operation with each step-by-step of orthonormal basis, difference according to sending node, obtain coded data separately, then, these coded datas are carried out the logic xor operation according to bit-order, the transmission of data after being merged.Finally, the data step-by-step after merging is sent to all receiving nodes;
step 6: the arbitration result that receiving node sends according to arbitration modules obtains the information of sending node, and the orthonormal basis code word that needs according to this information configuration, make it and can carry out correct decoding to the fused data that receives, when decoding, the fused data that receives is carried out logic and operation according to the orthonormal basis code word step-by-step of bit-order and configuration, obtain decoded data, and then use an accumulator module to add up to decoded data, finally, the output of accumulator module is namely the raw data of sending node, receiving node just is connected into merit and receives the raw data of sending node at this moment,
Step 7:, if the raw data of sending node also is not sent, returns to step 4 and proceed data transmission; If sending node has been completed the transmission of all raw data, expression once complete data interaction complete, return to step 1 this moment, notifies simultaneously the arbitration modules end of transmission (EOT), makes arbitration modules select new node to carry out data transmission from the sending node of other waits.
In order to verify implementation result of the present invention, as shown in table 1, the area that the present invention and prior art are consumed has carried out experimental verification, and is as shown in table 2, and the power that the present invention and prior art consume is verified:
Table 1
Table 2
, according to above-described embodiment, just can realize well the present invention.
Claims (9)
1., based on the CDMA on-chip network structure of orthonormal basis, it is characterized in that, comprise the forwarded module and the arbitration modules that integrate, two above processing units that are connected with arbitration modules by network node and forwarded module respectively.
2. the on-chip network structure of the CDMA based on orthonormal basis according to claim 1, it is characterized in that, described two above processing units are connected with respectively the Network-Node Interface that is connected with network node, described network node comprises and the two-way data buffering module that is connected of Network-Node Interface, with the two-way data transmit-receive module that is connected of data buffering module, described data transmit-receive module is connected and is connected with arbitration modules with the forwarded module.
3. the on-chip network structure of the CDMA based on orthonormal basis according to claim 2, is characterized in that, described processing unit is general purpose microprocessor, hardware-accelerated core or dsp processor.
4., based on the implementation method of the CDMA on-chip network structure of orthonormal basis, it is characterized in that, comprise the following steps:
(1) on two above processing units, Network-Node Interface is set respectively, the Network-Node Interface of each processing unit is connected on same forwarded module and arbitration modules by a network node respectively, and with the forwarded module together with arbitration modules is integrated in;
While (2) carrying out data transmission between processing unit, the processing unit that carries out the data transmission is sent to coupled network node by coupled Network-Node Interface with data to be transmitted and purpose processing unit address, sending data to the forwarded module by network node after through arbitration modules, allowing processes, then data after treatment are sent to the network node that is connected with the purpose processing unit, the purpose processing unit carries out data receiver by the Network-Node Interface on it.
5. the implementation method of the on-chip network structure of the CDMA based on orthonormal basis according to claim 4, is characterized in that, described step (2) specifically comprises the following steps:
The network node that (2a) with the processing unit that carries out the data transmission, is connected is initiated the output application to arbitration modules when the data that receive processing unit send instruction;
(2b) arbitration modules judges whether corresponding purpose processing unit of this moment receives only a data transfer request, encode and merge if allow network node to send data to the forwarded module, will encode afterwards with merge after data transmission to the network node that is connected with the purpose processing unit; According to the round-robin algorithm, select the permission output node if not, respectively arbitration result is sent to simultaneously and carries out the data network node that sends and the network node that carries out data receiver, the network node that obtains afterwards arbitrating permission carries out data output, carry out the network node of data receiver according to reception orthogonal code corresponding to arbitration result configuration, and carry out the data reception;
The network node that (2c) carries out data receiver receives the laggard row decoding of data and reduction.
6. the implementation method of the on-chip network structure of the CDMA based on orthonormal basis according to claim 5, is characterized in that, described data encoding specifically comprises the following steps:
(2d) to each, carry out a different set of orthonormal basis code word of network node distribution that data send;
The coded data that (2e) according to the logic XOR, will carry out each network node that data send merges;
(2f) data transmission after merging is to respectively carrying out the network node of data receiver.
7. the implementation method of the on-chip network structure of the CDMA based on orthonormal basis according to claim 6, it is characterized in that, in step (2), if the forwarded module receives from network node and sends and next forwarding data, according to the orthogonal code of distributing to the corresponding network node, forwarding data is encoded, and the data after encoding according to XOR merge, and the data transmission after merging by shared channel afterwards is to the network node that respectively receives.
8. the implementation method of the on-chip network structure of the CDMA based on orthonormal basis according to claim 7, is characterized in that, described step (2c) specifically comprises the following steps:
(2c1) carry out the network node of data receiver according to the corresponding orthonormal basis code word of arbitration information configuration that obtains from arbitration modules;
Logic and operation is carried out in the fused data that (2c2) will receive from the forwarded module and the corresponding orthonormal basis code word step-by-step of carrying out the network node of data transmission, obtains decoded data;
(2c3) decoded data are added up, realize reduction.
9. the implementation method of the on-chip network structure of the CDMA based on orthonormal basis according to claim 8, it is characterized in that, described network node by with the two-way data buffering module that is connected of Network-Node Interface, one end and data buffering module be two-way to be connected, the other end forms with the data transmit-receive module that the forwarded module is connected with arbitration modules, described processing unit carries out data receiver or all will wait to receive while sending or data to be sent deposit the data buffering module in, then receives or transmission processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310321794.7A CN103389962B (en) | 2013-07-29 | 2013-07-29 | Based on CDMA on-chip network structure and its implementation of orthonormal basis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310321794.7A CN103389962B (en) | 2013-07-29 | 2013-07-29 | Based on CDMA on-chip network structure and its implementation of orthonormal basis |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103389962A true CN103389962A (en) | 2013-11-13 |
| CN103389962B CN103389962B (en) | 2016-01-20 |
Family
ID=49534238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310321794.7A Expired - Fee Related CN103389962B (en) | 2013-07-29 | 2013-07-29 | Based on CDMA on-chip network structure and its implementation of orthonormal basis |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103389962B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446798A (en) * | 2014-07-31 | 2016-03-30 | 展讯通信（上海）有限公司 | Multi-core processing system and method, and mobile terminal |
| CN107113102A (en) * | 2014-09-29 | 2017-08-29 | 加利福尼亚大学董事会 | For the method and apparatus for the coding for disturbing network |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060153190A1 (en) * | 2005-01-11 | 2006-07-13 | Samsung Electronics Co., Ltd. | System-on-a-chip using CDMA bus and data transmission method therefor |
| CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
-
2013
- 2013-07-29 CN CN201310321794.7A patent/CN103389962B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060153190A1 (en) * | 2005-01-11 | 2006-07-13 | Samsung Electronics Co., Ltd. | System-on-a-chip using CDMA bus and data transmission method therefor |
| CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
Non-Patent Citations (3)
| Title |
|---|
| ANUROOP VIDAPALAPATI ET AL.: "NoC Architectures with Adaptive Code Division Multiple Access based Wireless Links", 《2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
| XIN WANG ET AL.: "Applying CDMA Technique to Network-on-Chip", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS》 * |
| 李建彬: "片上网络拓扑结构研究和交换节点设计", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446798A (en) * | 2014-07-31 | 2016-03-30 | 展讯通信（上海）有限公司 | Multi-core processing system and method, and mobile terminal |
| CN107113102A (en) * | 2014-09-29 | 2017-08-29 | 加利福尼亚大学董事会 | For the method and apparatus for the coding for disturbing network |
| CN107113102B (en) * | 2014-09-29 | 2021-02-02 | 加利福尼亚大学董事会 | Method and apparatus for coding of interfering networks |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103389962B (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103109248B (en) | Repeater and chip circuit | |
| CN104158738A (en) | Network-on-chip router with low buffer area and routing method | |
| CN101267450B (en) | Multicast routing method for distributed network application layer based on network coding | |
| CN101778049A (en) | Router and transmission method thereof on packet-circuit switching chip | |
| WO2017092394A1 (en) | Data transmission method and apparatus | |
| CN101834789B (en) | Packet-circuit exchanging on-chip router oriented rollback steering routing algorithm and router used thereby | |
| CN102521201A (en) | Multi-core DSP (digital signal processor) system-on-chip and data transmission method | |
| CN105007226A (en) | Multicast router based on package and circuit switching technology and working mode thereof | |
| CN103106173A (en) | Interconnection method among cores of multi-core processor | |
| CN101930417B (en) | Arbiter for serial data bus-based streaming media transmission system terminal equipment | |
| CN103024597B (en) | The optimal bit allocation method of multiple vision point video stream multi-rate multicast transmission | |
| CN102811152A (en) | Method for realizing real-time transaction and data exchange of multiple main bus network communication | |
| CN101488923B (en) | Implementing method for network-on-chip data packet encoding optimization | |
| CN103389962B (en) | Based on CDMA on-chip network structure and its implementation of orthonormal basis | |
| CN104796343A (en) | Communication structure based on network-on-chip | |
| CN105530157A (en) | Method for sharing credit by multiple virtual links in AFDX (Avionics Full Duplex Switched Ethernet) network switch | |
| CN104009943B (en) | LLDP message transmitting methods and DCB equipment | |
| CN105764091A (en) | Method of effectively utilizing wireless bandwidth | |
| CN101217564B (en) | A parallel communication system and the corresponding realization method of simple object access protocol | |
| CN103078808B (en) | The data flow being applicable to multithread matching regular expressions exchanges multiplex system and method | |
| CN102740170B (en) | Uplink and downlink transmission method of broadband optical access data | |
| CN104009817A (en) | Method for energy-saving dispatching in PON based on network coding | |
| CN109643301B (en) | Multi-core chip data bus wiring structure and data transmission method | |
| CN106603416B (en) | A kind of CDMA routing node based on parallel organization CODEC | |
| CN102110074A (en) | Multi-core processor and flow classification control device and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160120 Termination date: 20160729 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |