CN103378263A - 发光二极管封装结构的制造方法 - Google Patents

发光二极管封装结构的制造方法 Download PDF

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CN103378263A
CN103378263A CN201210127471XA CN201210127471A CN103378263A CN 103378263 A CN103378263 A CN 103378263A CN 201210127471X A CN201210127471X A CN 201210127471XA CN 201210127471 A CN201210127471 A CN 201210127471A CN 103378263 A CN103378263 A CN 103378263A
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fluorescent powder
powder film
substrate
led
package structure
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张洁玲
罗杏芬
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Rongchuang Energy Technology Co ltd
Zhanjing Technology Shenzhen Co Ltd
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Rongchuang Energy Technology Co ltd
Zhanjing Technology Shenzhen Co Ltd
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Priority to TW101124468A priority patent/TW201344989A/zh
Priority to US13/865,163 priority patent/US8828754B2/en
Publication of CN103378263A publication Critical patent/CN103378263A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50Wavelength conversion elements
    • H01L33/507Wavelength conversion elements the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0041Processes relating to semiconductor body packages relating to wavelength conversion elements

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

一种发光二极管封装结构的制造方法,包括以下步骤:提供一基板;提供一发光二极管芯片,设置该发光二极管芯片于基板上;提供一光学元件,将该光学元件设置在该基板上,并覆盖该发光二极管芯片;提供一荧光粉薄膜,将该荧光粉薄膜设置在该光学元件上;提供一具有毛细孔的载板,将该荧光粉薄膜设置在该光学元件上;提供一模具,该模具与该载板共同形成一收容空间,荧光粉薄膜及基板收容在该收容空间内;通过载板的毛细孔将收容空间内的空气抽出与/或通过对该荧光粉薄膜吹气的方式而使该荧光粉薄膜贴附在光学元件上;固化该荧光粉薄膜至该光学元件上。

Description

发光二极管封装结构的制造方法
技术领域
本发明涉及一种半导体发光元件的制造方法,尤其涉及一种发光二极管封装结构的制造方法。
背景技术
发光二极管凭借其高光效、低能耗、无污染等优点,已被应用于越来越多的场合之中,大有取代传统光源的趋势。
现有的发光二极管封装结构通常包括基板、位于基板上的电极、承载于基板上并与电极电性连接的发光二极管芯片以及覆盖发光二极管芯片的封装体。为改善发光二极管芯片发光特性,通常会在发光二极管封装结构中设置荧光粉。荧光粉通常是采用喷涂的方式涂覆在封装胶的出光面上,然而喷涂的随机性容易导致荧光粉分布不均匀。此外,荧光粉也可在点封装胶之前混合在封装胶材料中,而由于封装胶材料凝固时悬浮在封装胶材料中的荧光粉会发生沉积,从而也会导致固化后的封装胶中的荧光粉分布不均匀,从而影响发光二极管封装结构最终的出光效果。
发明内容
有鉴于此,有必要提供一种荧光粉分布均匀的发光二极管封装结构的制造方法。
一种发光二极管封装结构的制造方法,包括以下步骤:
提供一基板;
提供一发光二极管芯片,设置该发光二极管芯片于基板上;
提供一光学元件,将该光学元件设置在该基板上,并覆盖该发光二极管芯片;
提供一荧光粉薄膜,将该荧光粉薄膜设置在该光学元件上;
提供一具有毛细孔的载板,将该荧光粉薄膜设置在该光学元件上;
提供一模具,该模具与该载板共同形成一收容空间,荧光粉薄膜及基板收容在该收容空间内;
通过载板的毛细孔将收容空间内的空气抽出与/或通过对该荧光粉薄膜吹气的方式而使该荧光粉薄膜贴附在光学元件上;
固化该荧光粉薄膜至该光学元件上。
本发明的发光二极管封装结构的制造方法中,先通过载板的毛细孔将收容空间内的空气抽出与/或通过对该荧光粉薄膜吹气的方式而将该荧光粉薄膜直接贴附在光学元件上,再通过高温烘烤将该荧光粉薄膜固化在光学元件上,保证了荧光粉薄膜中的荧光粉分布均匀、制作过程简便,避免了荧光粉喷涂或点胶工艺中出现的荧光粉分布不均的现象。
下面参照附图,结合具体实施例对本发明作进一步的描述。
附图说明
图1至图10为本发明一实施方式的发光二极管封装结构的制造方法中各步骤示意图。
图11为采用本发明另一实施方式的发光二极管封装结构的制造方法制造的发光二极管封装结构的示意图。
主要元件符号说明
基板 10
孔洞 100
第一电连接部 11
第二电连接部 12
发光二极管芯片 30、30a
半导体发光结构 31
第一电极 34
第二电极 35
导线 32、33
透镜 40、40a
凹面 46a
填充空间 42
封装层 44
载板 60
荧光粉薄膜 50、50a
模具 70
收容空间 711
上模 72
贯穿孔 720
下模 71
加压装置 90
抽真空装置 80
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
本发明一实施例的发光二极管封装结构制造方法包括如下步骤:
请参照图1及图2(其中图1为剖视图,图2为俯视图),步骤1,提供一基板10。具体地,该基板10开设若干贯穿基板10的孔洞100,且该基板10的上表面上设置第一电连接部11和第二电连接部12。所述第一电连接部11和第二电连接部12相互间隔。所述孔洞100设置于第一电连接部11和第二电连接部12之间的绝缘带的两端。
请同时参照图3及图4(其中图3为剖视图,图4为俯视图),步骤2,提供一发光二极管芯片30,设置该发光二极管芯片30于基板10上。具体地,该发光二极管芯片30设置在第一电连接部11的上表面上。所述发光二极管芯片30包括半导体发光结构31以及设置在半导体发光结构31顶部的第一电极34和第二电极35。所述第一电极34、第二电极35间隔设置在半导体发光结构31远离基板10的顶面上。所述第一电极34通过一导线32与第一电连接部11形成电性连接,所述第二电极35通过另一导线33与第二电连接部12形成电性连接。本实施例中,该基板10上设有两个发光二极管芯片30。具体实施时,所述发光二极管芯片30的个数不限于本实施例的情况,其可为三个,也可为多个。
请同时参照图5及图6,步骤3,提供一透镜40,将该透镜40设置在该基板10上,该透镜40覆盖该发光二极管芯片30。具体地,该透镜40与该基板10之间形成一填充空间42,沿着该基板10的孔洞100填充封装材料到该填充空间42内,以在该透镜40与该基板10之间形成包覆该发光二极管芯片30的一封装层44。
请同时参照图7,步骤4,提供一荧光粉薄膜50,将该荧光粉薄膜50设置在该透镜40上。具体地,该荧光粉薄膜50中均匀分布有荧光粉,荧光粉的材料可以为石榴石(garnet)结构的化合物。将该荧光粉薄膜50盖设在该透镜40上时,该荧光粉薄膜50为半凝固状态。由于该荧光粉薄膜50具有一定的伸缩强度和弹性,从而可以靠透镜40的支撑而不至于从各透镜40的孔隙处掉落。由于该荧光粉薄膜50为半凝固状态,因此其内部的荧光粉不会像流体状态的封装层一样发生沉积进而使荧光粉分布不均匀。
步骤5,提供一具有毛细孔(图未示)的载板60,将该基板10设置在该载板60上。具体地,该载板60内具有连通载板60上下表面的毛细孔,该载板60的面积大于该基板10的面积。
请同时参照图8,步骤6,提供一模具70,该模具70与该载板60共同形成一收容空间711,荧光粉薄膜50及基板10收容在该收容空间711内。具体地,该模具70包括下模71及上模72,该下模71围设在该载板60周围,该上模22设置在该下模21上,该下模21的顶面及该荧光粉薄膜50的上表面处于同一平面,该上模22的底面与该下模21的顶面及该荧光粉薄膜50的上表面接触,该下模71、上模72及该载板60共同形成所述收容空间711。该上模72中央开设一贯穿孔720,一加压装置90设置在该贯穿孔720处。
请同时参照图9,步骤7,通过载板60的毛细孔将收容空间711内的空气抽出与/或通过对该荧光粉薄膜50吹气的方式而使该荧光粉薄膜50贴附在透镜40上。具体地,提供一抽真空装置80,将该抽真空装置80对准该载板60的底部来抽离该收容空间711内的空气,使收容空间711内的空气沿着载板60的毛细孔流出。同时,加压装置90对该荧光粉薄膜50吹气以施加一个向下的、朝向透镜40的压力,使得该荧光粉薄膜50紧密地贴附在该透镜40表面。当然,具体实施过程中,上述抽真空装置80与加压装置90可只选择一种,即通过载板60的毛细孔将收容空间711内的空气抽出或通过对该荧光粉薄膜50吹气的方式而使该荧光粉薄膜50贴附在透镜40上。
步骤8,通过高温烘烤使该荧光粉薄膜50固化至该透镜40。具体地,可先移除模具70、加压装置90、抽真空装置80及载板60,再通过高温烘烤使荧光粉薄膜50固化至该透镜40。当然,也可先固化荧光粉薄膜50,然后再移除模具70、加压装置90、抽真空装置80及载板60。最后,可将如图10所示的发光二极管封装结构沿着虚线切割,以获得多个发光二极管封装结构。
当然,上述制造方法中,该荧光粉薄膜50还可通过将收容空间711内的空气抽出与/或通过对该荧光粉薄膜50吹气的方式贴附在其他光学元件上,如封装层44上,即先直接在该发光二极管芯片30上覆盖封装层44,然后再通过将收容空间711内的空气抽出与/或通过对该荧光粉薄膜50吹气的方式将该荧光粉薄膜50贴附在封装层44上。
本发明的发光二极管封装结构的制造方法中,先通过载板60的毛细孔将收容空间711内的空气抽出与/或通过对该荧光粉薄膜50吹气的方式而将该荧光粉薄膜50贴附在透镜40上,再将该荧光粉薄膜50固化在透镜40上,保证了荧光粉薄膜50中的荧光粉分布均匀、制作过程简便,避免了荧光粉喷涂或点胶工艺中出现的荧光粉分布不均的现象。
如图11所示为对应本发明另一实施例的发光二极管封装结构的制造方法制造的发光二极管封装结构的示意图。该另一实施例的制造方法与前述实施例的制造方法的区别在于:该另一实施例采用中心具有凹面46a的透镜40a,使该发光二极管芯片30a发出的光通过透镜40a后,形成蝙蝠翼形的光场而增加侧向出光。该透镜40a的外表面的中央为凹面,再通过采用空气抽出与/或通过对该荧光粉薄膜50a吹气的方式将荧光粉薄膜50a贴附在该透镜40a上,使荧光粉薄膜50a中的荧光粉在透镜40a表面均匀分布。而采用现有技术的制造方法将荧光粉薄膜贴附在中心具有凹面的透镜上,荧光粉更容易在透镜的凹面内沉积,导致荧光粉在透镜表面分布不均匀。所以本发明另一实施例的制造方法相对于现有技术的制造方法取得更优的技术效果。
应该指出,上述实施方式仅为本发明的较佳实施方式,本领域技术人员还可在本发明精神内做其它变化。这些依据本发明精神所做的变化,都应包含在本发明所要求保护的范围之内。

Claims (10)

1.一种发光二极管封装结构的制造方法,包括以下步骤:
提供一基板;
提供一发光二极管芯片,设置该发光二极管芯片于基板上;
提供一光学元件,将该光学元件设置在该基板上,并覆盖该发光二极管芯片;
提供一荧光粉薄膜,将该荧光粉薄膜设置在该光学元件上;
提供一具有毛细孔的载板,将该荧光粉薄膜设置在该光学元件上;
提供一模具,该模具与该载板共同形成一收容空间,荧光粉薄膜及基板收容在该收容空间内;
通过载板的毛细孔将收容空间内的空气抽出与/或通过对该荧光粉薄膜吹气的方式而使该荧光粉薄膜贴附在光学元件上;
固化该荧光粉薄膜至该光学元件上。
2.如权利要求1所述的发光二极管封装结构的制造方法,其特征在于:上述将模具内的空气抽出是采用一抽真空装置对准载板的方式进行。
3.如权利要求1所述的发光二极管封装结构的制造方法,其特征在于:上述对薄膜吹气是采用一种加压装置对荧光粉薄膜施加压力的方式进行。
4.如权利要求1至3任意一项所述的发光二极管封装结构的制造方法,其特征在于:该模具包括下模及上模,该下模围设在该载板周围,该上模设置在该下模上,该上模开设一贯穿孔,该加压装置设置在该贯穿孔处。
5.如权利要求1至3任意一项所述的发光二极管封装结构的制造方法,其特征在于:先移除模具、加压装置/抽真空装置及载板,然后固化荧光粉薄膜。
6.如权利要求1至3任意一项所述的发光二极管封装结构的制造方法,其特征在于:先固化荧光粉薄膜,然后移除模具、加压装置/抽真空装置及载板。
7.如权利要求1至3任意一项所述的发光二极管封装结构的制造方法,其特征在于:所述基板上设有多个发光二极管芯片,所述发光二极管封装结构通过切割而得到多个单个的发光二极管封装结构。
8.如权利要求1所述的发光二极管封装结构的制造方法,其特征在于:该光学元件为透镜,该透镜的外表面的中央为凹面。
9.如权利要求1所述的发光二极管封装结构的制造方法,其特征在于:该基板开设若干贯穿基板的孔洞,该光学元件为透镜,该透镜与该基板之间形成一填充空间,沿着该基板的孔洞填充封装材料到该填充空间内,在该透镜与该基板之间形成包覆该发光二极管芯片的一封装层。
10.如权利要求1所述的发光二极管封装结构的制造方法,其特征在于:该光学元件为封装层,该荧光粉薄膜贴附在封装层上。
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