CN103378102B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN103378102B CN103378102B CN201210107541.5A CN201210107541A CN103378102B CN 103378102 B CN103378102 B CN 103378102B CN 201210107541 A CN201210107541 A CN 201210107541A CN 103378102 B CN103378102 B CN 103378102B
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Abstract
The invention discloses a kind of semiconductor structure, there is the electrically conductive barrier of position between capacitor conductive material and semiconductor substrate.Electrically conductive barrier again besieged capacitor conductive material dielectric layer around, and directly contacting capacitor electric conducting material and semiconductor substrate.Electrically conductive barrier is as the embedded connecting band structure of reduction being electrically connected capacitor conductive material and semiconductor substrate.
Description
Technical field
The present invention relates to a kind of for embedded connecting band (BS, buriedstrap) conductive barrier Rotating fields and manufacture craft thereof, particularly relate to a kind of in deep slot type capacitor, there is the homogeneous conductive barrier layer structure and manufacture craft thereof repairing and subtract area, belong to technical field of manufacturing semiconductors.
Background technology
At present, industrial circle extensively adopts a transistor to arrange in pairs or groups the structure of a capacitor, as the elementary cell of dynamic random access memory (DRAM).A this transistor is arranged in pairs or groups the assembly combination of a capacitor, makes dynamic random access memory structure become bank bit very high density, electronic building brick that unit manufacturing cost is low again, so have irreplaceable status in multiple computer access device.Simultaneously along with the develop rapidly of semiconductor technology, also promote dynamic random access memory element just rapidly to the future development of high density, high power capacity simultaneously.
How can unit element area is ever-reduced while, can create again and maintain the capacitor of capacitance in suitable level, be most importantly in dynamic random access memory technology also need most one of challenge constantly overcome always.One has the dynamic random access memory unit basic structure of deep slot type (deeptrench) capacitor, generally employ three dimensional design, first below silicon wafer surface, excavate in the mode of etching the use that deep trouth preparation forms capacitor, thus vertical structure can be utilized in the limited unit area of plane to increase capacitor storage area, this deep slot type capacitor design is one of main flow of current high density dynamic device technology.
Be filled with heavily doped polysilicon in the deep trouth of this deep slot type capacitor, and connected by the source electrode of connecting band (strap) and transistor.In order to increase dynamic random access memory cellular array density further, industrial circle have employed again a kind of preparation technology being called embedded connecting band, second layer polysilicon use inclination technique inject ion, coordinate selectivity etch back process to form groove and obtain monolateral autoregistration connection, be called embedded connecting band.Because this technique have employed embedded connecting band, namely connecting band is pushed on the zanjon wall below silicon wafer surface, the deep trench capacitor so completed can be positioned over the below of passive wordline, reduces the distance between two wordline, effectively adds the density of dynamic random access memory cell array.In the literature this deep trench capacitor is documented in detail.
Because monolateral self aligned connecting band, need, through heat treatment process, alloy is diffused to ground, and connect with the source electrode of transistor is electrically upper.In order to effective control connection band, as the window (window) alloy being diffused to ground in heat treatment process, monolateral self aligned connecting band must have the area that size is just right, otherwise can increase the electric field of connecting band knot (junction).
But be used in the monolateral self aligned connecting band of deep trench capacitor in this dynamic random access memory unit, but still facing to many difficulties in technique.Such as, in order to reach the general uniform requirement of dynamic random access memory unit character, monolateral self aligned connecting band must have even and that size is just right area, namely there is the general uniform strict demand of etching, therefore very high to the requirement of etching technics.In addition, in order to reach the requirement of capacitance, the material layer on deep slot type capacitor furrow bank requires very thin, thus has the risk of defect increase, affects yield.
Summary of the invention
Therefore, the slot type capacitor structure that the present invention will propose in a kind of dynamic random access memory structure, can ensure that monolateral self aligned connecting band has even and just right window area, overcome above-mentioned critical technological point.
The technical problem to be solved in the present invention is that monolateral self aligned connecting band must have the problem of even and just right area, so provide a kind of to have dynamic random access memory structure of reducing embedded connecting band structure and preparation method thereof.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of semiconductor structure, has semiconductor substrate, capacitor conductive material, dielectric layer and electrically conductive barrier.Semiconductor substrate has groove.Capacitor conductive material position is in groove.Dielectric layer position in the trench, and surrounds capacitor conductive material.The electrically conductive barrier of position between capacitor conductive material and semiconductor substrate, by dielectric layer up and down around, and directly contacting capacitor electric conducting material and semiconductor substrate.Electrically conductive barrier has the area of reduction, as electrical connection capacitor conductive material and the trimmed uniform embedded connecting band structure of semiconductor substrate.
As a preferred version of the present invention, dielectric layer up and down around and directly contact electrically conductive barrier.
As another preferred version of the present invention, the while of electrically conductive barrier, position is at capacitor conductive material, between dielectric layer and semiconductor substrate.
As another preferred version of the present invention, dielectric layer comprises first medium layer and second dielectric layer respectively.Wherein, first medium layer is different with second dielectric layer, and has the inclined plane of complementation respectively.
The present invention proposes again a kind of preparation method of semiconductor structure, comprises the following steps:
First medium layer is filled up in step one, the groove in semiconductor substrate in place, capacitor conductive material, the first electrically conductive barrier and the second electrically conductive barrier is had in the groove of semiconductor substrate, capacitor conductive material position is in groove and have groove, first medium layer around capacitor conductive material, first electrically conductive barrier position is between capacitor conductive material and semiconductor substrate, and the second electrically conductive barrier position in a groove;
Step 2, utilize etch-back techniques to remove to fill up a part of first medium layer of groove, make first medium layer form the inclined plane of position on groove, and expose capacitor conductive material;
Step 3, the capacitor conductive material utilizing finishing lithographic technique removal part to expose, and remove the first electrically conductive barrier of part simultaneously, reduce the area of the first electrically conductive barrier and expose semiconductor substrate partly; And
Step 4, fill up second dielectric layer in the trench, and covering capacitor electric conducting material and the first electrically conductive barrier after reducing, make the first electrically conductive barrier position between capacitor conductive material and semiconductor substrate, and direct contacting capacitor electric conducting material and semiconductor substrate, as the embedded connecting band structure of smooth being electrically connected capacitor conductive material and semiconductor substrate.
As a preferred version of the present invention, before filling up first medium layer in the trench, remove position the second electrically conductive barrier in a groove.
As another preferred version of the present invention, the first medium layer filling up groove has uneven surface.
As another preferred version of the present invention, utilize uneven surface and etch-back techniques, form the inclined plane of position on groove.
As another preferred version of the present invention, service time pattern and endpoint mode at least one wherein control finishing lithographic technique, accurately reduce the area of the first electrically conductive barrier.
As another preferred version of the present invention, the first electrically conductive barrier stops the alloy diffusion in semiconductor substrate.
Accompanying drawing explanation
Fig. 1-7 is that in embodiment, preparation has the process flow diagram reducing embedded connecting band structure.
Fig. 8 reduces embedded connecting band structure schematic diagram in embodiment.
Wherein, description of reference numerals is as follows:
101 semiconductor substrate 132 inclined planes
111 etching window 140 capacitor conductive materials
The connecting band that 110 hard masks 141 are monolateral
120 groove 142 grooves
130 first medium layer 151 first electrically conductive barriers
131 protruding 152 second electrically conductive barriers
Embodiment
Further illustrate device architecture of the present invention and preparation technology below in conjunction with accompanying drawing, in order to illustrate facilitate accompanying drawing and not according to true scale.
First please refer to Fig. 1, the present embodiment, to adopt based on the technique making embedded connecting band, provides a kind of electrically conductive barrier in embedded connecting band structure, and has trimmed uniform acreage reduction.The hard mask 110 that Fig. 1 draws semiconductor substrate 101, formation has etching window 111 and position are at the groove 120 in semiconductor substrate 101, first medium layer 130, capacitor conductive material 140, groove 142, first electrically conductive barrier 151 and the second electrically conductive barrier 152.Semiconductor substrate 101 has alloy, can adopt P type substrate or N-type substrate.
The etching window 111 of saturating hard mask 110, forms position at the groove 120 in semiconductor substrate 101.Hard mask 110 can be layer of nitride material, such as silicon nitride layer.Conventional photoetching process and etching technics can be utilized to define the etching window 111 of groove 120.Such as, first prepare the hard mask 110 of a flood, hard mask 110 applies one deck anti-reflecting layer ARC (Anti-ReflectiveCoating) (not shown), recycling photoetching process defines the etching window 111 being used in groove 120 and hard mask 110 on photoresist (not shown), then carry out etching and the etching window 111 of defined groove 120 is transferred on hard mask 110, then remove photoresist (not shown) and anti-reflecting layer (not shown).
Then, utilize the hard mask 110 being formed with etching window 111 to carry out groove 120 again and etch, be etched to semiconductor substrate 101 always.Be more than a kind of more conventional lithographic etch process, the present invention also can adopt other feasible chemical wet etching method, and is not limited only to this.Subsequently, as shown in Figure 1, in groove 120, furrow bank forms first medium layer 130, and be filled with the use of polycrystalline silicon material as capacitor conductive material 140 of alloy, the dynamic random access memory unit preparation technology with deep slot type capacitor of any industrial quarters can be adopted, such as adopt embedded connecting band technique, form monolateral connecting band 141.
As shown in Figure 1, capacitor conductive material 140 in groove 120, and has and utilizes inclination technique to inject ion, coordinates the groove 142 that selectivity etch back process is formed.Chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition) or high temperature thermal process (highthermo) can be utilized to prepare first medium layer 130, and first medium layer 130 is around capacitor conductive material 140.First electrically conductive barrier 151 is between capacitor conductive material 140 and semiconductor substrate 101, and other second electrically conductive barrier 152 is in groove 142.First electrically conductive barrier 151 and the second electrically conductive barrier 152 can be polysilicon, metal or metal silicide.Such as, sedimentation is used to form the first electrically conductive barrier 151 and the second electrically conductive barrier 152 of polysilicon or metal material together.Or, utilize metal silicide technology to form metal silicide.Such as, the semiconductor substrate 101 surface deposition metal using physical vapour deposition (PVD) (PVD, PhesicalVaporDeposition) technique exposing; Carry out first time rapid thermal annealing (RTA) technique, make the pasc reaction on metal and semiconductor substrate 101 surface, and form metal silicide in surface of silicon; Wet etching is utilized to remove unreacted metal.Recycling second time rapid thermal anneal process is heat-treated metal silicide, forms final metal silicide.
Secondly, as shown in Figure 2, in place in the groove 120 of semiconductor substrate 101, fill up first medium layer 130 before first remove the second electrically conductive barrier 152.Such as, wet etching is used to remove unwanted second electrically conductive barrier 152.If the first electrically conductive barrier 151 of some is not blocked by first medium layer 130, as shown in Figure 2, the first medium layer 130 come out can also be removed when removing the second electrically conductive barrier 152.
Then, first medium layer 130 is filled up in the groove 120 in semiconductor substrate 101 in place and groove 142.First medium layer 130 can be layer of oxide material, such as, can be silicon oxide layer.The uneven surface of first medium layer 130.Such as, the surface of first medium layer 130 has protruding 131.Protruding 131 may close to groove 142, as shown in Figure 3, or away from groove 142, as shown in Figure 4.Protruding 131 can help the embedded connecting band structure forming acreage reduction.
Secondly, as shown in Figure 5, utilize etch-back techniques, such as deep dry etch process, remove a part of first medium layer 130 filling up groove 120, until capacitor conductive material 140 comes out.Such as, can consider that terminal (end-point) pattern or setting (default) pattern determine to eat-back terminal.Now, the first electrically conductive barrier 151 can protect semiconductor substrate 101 not have the problem of side direction etching.Because protruding 131, can etch-back techniques be adjusted, make first medium layer 130 form the inclined plane 132 of position on groove 142.Should illustrate, as shown in Figure 5, some first medium layer 130 may cover hard mask 110.
Then, as shown in Figure 6, utilize the capacitor conductive material 140 that finishing (trimming) lithographic technique removal part again exposes, and repair simultaneously and remove the first electrically conductive barrier 151 of part, and expose the semiconductor substrate 101 of part.Such as, remove the capacitor conductive material 140 of 40nm downwards, reduce again the area of the first electrically conductive barrier 151 simultaneously.Should illustrate, because inclined plane 132, the capacitor conductive material 140 that finishing lithographic technique removal part exposes can be strengthened, and strengthen the first electrically conductive barrier 151 removing part simultaneously, until the first electrically conductive barrier 151 narrows down to suitable area, and by evenly trimmed.Such as, can consider that terminal (end-point) pattern or temporal mode (timemode) accurately control finishing lithographic technique, determine when finishing etching stops.Should illustrate, finishing lithographic technique comprises over etching.
Secondly, as shown in Figure 7, reuse high-quality first medium layer 130 cover the capacitor conductive material 140 that position highly reduced in semiconductor substrate 101 groove 120, the semiconductor substrate 101 exposing part and area reduce after the first electrically conductive barrier 151.So, the first electrically conductive barrier 151 after area reduces between capacitor conductive material 140 and semiconductor substrate 101, again by first medium layer about 130 complete around, and directly contacting capacitor electric conducting material 140 and semiconductor substrate 101.First electrically conductive barrier 151 can stop the alloy diffusion in semiconductor substrate 101.First electrically conductive barrier 151 has the area of reduction, during embedded connecting band structure 110 as electrical connection capacitor conductive material 140 and semiconductor substrate 101 smooth, has the even and just right window area controlled by finishing lithographic technique.
Then, as shown in Figure 8, in groove 111, second dielectric layer 150 is filled up, and covering capacitor electric conducting material 140 and the first electrically conductive barrier 151 after reducing.Second dielectric layer 150 can be the oxide material of normal quality, so first medium layer 130 is different with second dielectric layer 150, and has complementary inclined plane 132 respectively.
In addition, the present invention also comprises other assembly of formative dynamics random access device, such as source electrode, drain electrode or the preparation technology of grid, and other technology related in the present invention belongs to the category that those skilled in the art are familiar with, and does not repeat them here.
Beneficial effect of the present invention is: monolateral self aligned connection, with the window area of even and just right size, reaches the uniform requirement of dynamic random access memory unit character.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a semiconductor structure, is characterized in that, comprising:
Semiconductor substrate, has groove;
Capacitor conductive material, position is in groove;
Dielectric layer, in the trench and surround capacitor conductive material, wherein said dielectric layer comprises first medium layer and second dielectric layer, and described first medium layer and described second dielectric layer have different quality, and has complementary inclined plane respectively in position; And
Electrically conductive barrier, position is between described capacitor conductive material and semiconductor substrate, by dielectric layer around, and directly contact described capacitor conductive material and described semiconductor substrate, as the embedded connecting band structure of reduction being electrically connected described capacitor conductive material and described semiconductor substrate.
2. semiconductor structure according to claim 1, it is characterized in that described dielectric layer around and the direct described electrically conductive barrier of contact.
3. semiconductor structure according to claim 1, it is characterized in that described electrically conductive barrier simultaneously position at described capacitor conductive material, between described dielectric layer and described semiconductor substrate.
4. a preparation method for semiconductor structure, is characterized in that, comprises the following steps:
The groove of position in semiconductor substrate, capacitor conductive material, first medium layer, the first electrically conductive barrier and the second electrically conductive barrier are provided, wherein, described capacitor conductive material position is in described groove and have groove, described first medium layer around described capacitor conductive material, described first electrically conductive barrier position is between described capacitor conductive material and described semiconductor substrate, and described second electrically conductive barrier position in a groove;
Fill up first medium layer in the trench;
Utilize etch-back techniques to remove the described first medium layer filling up part in described groove, make described first medium layer form the inclined plane of position on described groove, and expose described capacitor conductive material;
Utilize the described capacitor conductive material that finishing lithographic technique removal part exposes, and remove described first electrically conductive barrier of part simultaneously, and reduce the area of described first electrically conductive barrier and expose described semiconductor substrate partly; And
Fill up second dielectric layer in the trench, cover described capacitor conductive material and reduce rear described first electrically conductive barrier, make described first electrically conductive barrier position between described capacitor conductive material and described semiconductor substrate, and directly contact described capacitor conductive material and described semiconductor substrate, as the embedded connecting band structure of reduction being electrically connected described capacitor conductive material and described semiconductor substrate.
5. the preparation method of semiconductor structure according to claim 4, before it is characterized in that filling up described first medium layer in the trench, removes described second electrically conductive barrier.
6. the preparation method of semiconductor structure according to claim 4, is characterized in that the described first medium layer filling up described groove has uneven surface.
7. the preparation method of semiconductor structure according to claim 6, is characterized in that utilizing described uneven surface and described etch-back techniques to form the described inclined plane of position on described groove.
8. the preparation method of semiconductor structure according to claim 4, it is characterized in that service time pattern and endpoint mode at least one wherein accurately control described finishing lithographic technique, accurately reduce the area of described first electrically conductive barrier.
9. the preparation method of semiconductor structure according to claim 4, is characterized in that described first electrically conductive barrier stops the alloy diffusion in described semiconductor substrate.
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| CN1241809A (en) * | 1998-03-31 | 2000-01-19 | 西门子公司 | Method and apparatus having improved control of buried strap in trench capacitors |
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| DE10131709B4 (en) * | 2001-06-29 | 2006-10-26 | Infineon Technologies Ag | Method for producing one-sided buried straps |
| US7179748B1 (en) * | 2005-08-02 | 2007-02-20 | Nanya Technology Corporation | Method for forming recesses |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1241809A (en) * | 1998-03-31 | 2000-01-19 | 西门子公司 | Method and apparatus having improved control of buried strap in trench capacitors |
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