CN103377154A - Access-memory control device and method of memorizer, processor and north-bridge chip - Google Patents
Access-memory control device and method of memorizer, processor and north-bridge chip Download PDFInfo
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Abstract
Provided are an access-memory control device and method of a memorizer, a processor and a north-bridge chip. The access-memory control device of the memorizer comprises an analysis requesting unit for accessing and analyzing a request to form an operation command sequence including a plurality of operation commands, and an arbitration unit for performing arbitration of the operation commands in the operation command sequence according to arbitration conditions so as to send the operation commands to the memorizer. Compared with the prior art, the access-memory control device concurrently sends the operation command sequence through the analysis requesting unit and utilizes first temporal constraint, second temporal constraint and third temporal constraint to control a time interval from the sending time of an existing operation command to the sending time of a previous operation command adjacent to the existing operation command in the same operation command sequence, and concurrent accessing of multiple memorizers can be performed. In addition, multiple memorizer groups can be concurrently accessed, multi-dimensional concurrent accessing is achieved, the average handling time of request accessing and memorizing is remarkably shortened, and the overall access-memory performance of a system is improved.
Description
Technical field
The present invention relates to the computer memory control field, particularly the memory access control device of storer and method, processor and north bridge chips.
Background technology
Storer is the key factor that affects the computer system overall performance, and the lifting of its data transmission rate has positive role to improving processor performance.One times of about per 18 monthly increment of the speed of processor, and the speed of storer approximately just doubled in per 10 years, therefore, the raising of processor and memory performance is also asynchronous.Along with the progress of technological level, the speed of processor causes occurring the bottleneck of " storage wall " considerably beyond the speed of storer.
The technical bottleneck of bringing in order to alleviate " storage wall ", memory manufacturer have adopted many new memory architectures.With dynamic RAM (Dynamic Random Access Memory, DRAM) be example, dynamic RAM manufacturer has for example adopted many bodies (Multibanking) structure so that a plurality of memory access affairs can by concurrent processing, adopt two row bufferings (Row Buffer) so that the memory access affairs of hitting continuously with delegation can be accelerated processing.
For the architecture that makes storer actively plays a role, the memory access performance of controller is most important.In controller's design, the arbitration of access request and scheduling have vital effect to the utilization factor of raising storer and the performance of storage system, are the emphasis of controller design.Outstanding controller can effectively utilize the architecture of above-mentioned storer, improves memory bandwidth, reduces memory access latency.In the prior art, although the processor technology such as employing is looked ahead, out of order execution, prediction, multithreading are conducive to the memory access latency of concealing memory, but it is still increasing that memory access latency accounts for the proportion of processor dead time, and the processor technology of many concealing memory access delay has also proposed more and more higher requirement to memory bandwidth.
More technical schemes about the computer memory control field can be the Chinese patent of CN1588552A with reference to publication number, this patent disclosure a kind of double speed dynamic random access memory control device and method that asynchronous buffer is arranged, device comprises moderator, control unit interface and controller.Said apparatus is arbitrated the reading and writing data request of Client Model according to the requirement of decoding pipelined architecture, the read/write access operation of control data, the large data bandwidth that has utilized possibly storer, still, the memory access efficient of system improves limited, does not still solve the problems of the technologies described above.
Summary of the invention
It is larger that the problem that the present invention solves is that the prior art memory access latency accounts for the proportion of processor dead time, the problem that memory bandwidth is lower.
Technical solution of the present invention provides a kind of memory access control device, comprising: the request analysis unit, be used for access request is resolved to the operational order sequence, and described operational order sequence comprises some operational orders; Arbitration unit, be used for by referee conditions the operational order of described operational order sequence being arbitrated, operational order is sent to described storer, described referee conditions comprises: operational order is sent to the time interval satisfied the first temporal constraint, the second temporal constraint and the 3rd temporal constraint of described storer; Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank; Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks; Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
Alternatively, the described request resolution unit comprises two resolution unit that are associated with described set of memory banks, and each resolution unit comprises some parsing modules that are associated with described memory bank.
Alternatively, described arbitration unit comprises: the first temporal constraint register, and the quantity m of the quantity c of its quantity and the type of operational order, the quantity n of set of memory banks and the memory bank in the set of memory banks is related; The second temporal constraint register, the quantity c of its quantity and the type of operational order and the quantity n of set of memory banks are related; The 3rd temporal constraint register, its quantity is related with the quantity c of the type of operational order; Writing unit, be used for after the transmit operation order, write numerical value to the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register corresponding to the type of the operational order that has sent, the numerical associations of said write is in the clock period of described storer and the time interval requirement between the operational order; The numerical value of each temporal constraint register reduces to 0 based on the clock period of described storer certainly from the numerical value that writes; Control module, be used for when corresponding to the type of the operational order that does not send and specify access set of memory banks memory bank the first temporal constraint register numerical value, corresponding to the type of the described operational order that does not send and specify access set of memory banks the second temporal constraint register numerical value and be 0 corresponding to the numerical value of the 3rd temporal constraint register of the type of the described operational order that does not send, sends extremely described storer of the described operational order that does not send.
Alternatively, the quantity of described the first temporal constraint register is
The quantity of described the second temporal constraint register is n * c
2The quantity of described the 3rd temporal constraint register is c
2
Alternatively, described arbitration unit comprises: the first temporal constraint judging unit, whether the time interval that is used for judging the transmitting time of current time and last operational order satisfies the first temporal constraint between current operational order and the last operational order, and described current operational order and described last operational order belong to same operational order sequence; The second temporal constraint judging unit is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the second temporal constraint between the described last operational order; The 3rd temporal constraint judging unit is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the 3rd temporal constraint between the described last operational order; Transmitting element, it is to send described current operational order to described storer that the judged result that is used for the judged result of judged result, the second temporal constraint judging unit when described the first temporal constraint judging unit and the 3rd sequential judging unit is.
Alternatively, described access request is read request, write request or reads-revise-write request.
Alternatively, described operational order is activation command, read command, write order or writes back order.
Alternatively, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
Alternatively, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
Optionally, described access request is for reading-revise-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Perhaps, described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
Technical solution of the present invention also provides a kind of access control method of storer, comprising: access request is resolved to the operational order sequence, and described operational order sequence comprises some operational orders; By referee conditions the operational order in the described operational order sequence is arbitrated, so that operational order is sent to storer, described referee conditions comprises: described operational order is sent to the time interval satisfied the first temporal constraint, the second temporal constraint and the 3rd temporal constraint of described storer; Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank; Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks; Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
Technical solution of the present invention also provides a kind of processor, comprises the memory access control device of above-mentioned storer.
Technical solution of the present invention also provides a kind of north bridge chips, comprises the memory access control device of above-mentioned storer.
With respect to prior art, technical solution of the present invention is by concurrently transmit operation command sequence of request analysis unit, and utilize the first temporal constraint, the second temporal constraint and the control of the 3rd temporal constraint to send current operation order in the same operational order sequence and the time interval between the last operational order adjacent with described current operation order, not only can a plurality of memory banks of concurrent access (Bank), and can a plurality of set of memory banks of concurrent access (Rank), realized the multidimensional memory access that walks abreast.Experiment showed, that technical solution of the present invention can significantly shorten the average handling time of access request, improve entire system memory access performance.In addition, with respect to the traditional controller of existing employing " body walk abreast memory access strategy ", technical solution of the present invention does not obviously increase hardware yet and realizes cost.
Description of drawings
Fig. 1 is the synoptic diagram of controller access SDRAM;
Fig. 2 is the general structure synoptic diagram of the memory access control device of the storer that provides of embodiment of the present invention;
Fig. 3 is the synoptic diagram of an embodiment of request analysis unit;
Fig. 4 is the synoptic diagram of an embodiment of arbitration unit;
Fig. 5 is the synoptic diagram of an embodiment of the memory access control device of storer provided by the invention;
Fig. 6 is the process flow diagram of the access control method of the storer that provides of embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization in the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
The synchronous DRAM that the embodiment of the invention generally adopts take modem computer systems (Synchronous Dynamic Random Access Memory, SDRAM) describes as example.Please refer to Fig. 1, Fig. 1 is the synoptic diagram of controller access SDRAM.When internal storage access operates, generally send read request, write request or read-revise-write request to controller 100 by processor, again by controller 100 from internal memory, for example carry out corresponding data manipulation among the SDRAM.SDRAM only comprises 2 set of memory banks (Rank) among Fig. 1, and those skilled in the art know, and in real system, can comprise more Rank.
For SDRAM, comprise n storage particle (Chip) among each Rank, the numbering of a said n storage particle (Chip) is followed successively by 0,1,2 ..., n-2, n-1.Memory bank (Bank) in each storage particle (Chip) is called physical store body (P-Bank).Comprise 8 physical store bodies (P-Bank) among each Chip, the numbering of above-mentioned 8 physical store bodies (P-Bank) is followed successively by 0,1,2 ..., 6,7.Be when reality is used, in order to increase data bit width, generally n Chip can be connected use side by side.The bit wide of supposing each Chip is 8bit, and then the data bit width of 9 Chip is 8bits*9=72bits.At this moment, the Bank in each Chip also connects side by side, can regard the physical store body (P-Bank) of reference numeral in the above-mentioned Chip that connects side by side as a logical memory bank that is formed in parallel (L-Bank).As, the P-Bank0 of storage particle Chip0, the P-Bank0 of storage particle Chip2 ..., the physics P-Bank0 of storage particle Chipn, they form logical memory bank (L-Bank0) jointly.That is to say, in order to increase bit wide, the physical store body (P-Bank) of reality is connected use side by side, namely they can be regarded as " Bank that same bit wide is larger ", be called logical memory bank (L-Bank).In the present embodiment, unless otherwise indicated, described memory bank (Bank) all refers to logical memory bank (L-Bank).
In addition, for the storer that comprises three or three above Rank, when using technical solution of the present invention, can at first the Rank in the storer be divided into two groups, also, all Rank be divided into two logic Rank (L-Rank).In the present embodiment, unless otherwise indicated, described set of memory banks (Rank) all refers to logical memory bank group (L-Rank).
With reference to figure 2, the memory access control device 10 of the storer that embodiment of the present invention provides comprises request analysis unit 11 and arbitration unit 12.
Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank (Bank); Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks (Rank); Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
For SDRAM, user's access request comprises following three classes:
(1) read request.The user uses this request, can take out data from SDRAM.
(2) write request.The user uses this request, can deposit data in SDRAM.
(3) request of " reading-revise-write ".The user uses this request, can take out data from SDRAM; Then these data are made amendment and obtain a new data after (as add certain number, deduct certain number etc.); At last, this new data is restored this SDRAM.
Operational order refers to the order that storer can be accepted, identifies and process.What usually, operational order comprised will have: order symbol, chip select signal and reference address.At present, for SDRAM, be to realize the various access requests that the user sends, itself needed basic operation command comprises activation command (ACT), read command (RD), write order (WE) and writes back order (PRE).Here for convenience of description, only with order symbolic representation operational order, omit other key elements.
The operational order sequence is comprised of some operational orders, particularly:
(1) read request, general treatment scheme is: at first activate the data line that will access with activation command; Then, " activate row " with the read command access, sense data; At last, use writes back order and will activate the capable storage array that writes back.Correspondingly, request analysis unit 11 can resolve to read request by activation command, read command and write back the operational order sequence A CT_RD_PRE that order forms.
(2) write request, general treatment scheme is: at first activate the data line that will access with activation command; Then, data are write " activating row " with write order; At last, use writes back order and will activate the capable storage array that writes back.Correspondingly, request analysis unit 11 can resolve to write request by activation command, write order and write back the operational order sequence A CT_WE_PRE that order forms.
(3) request of " reading-revise-write " can be regarded as by read request and write request and combines.Request analysis unit 11 can with read-revise-write request resolves to ACT_RD_WE_PRE, also can with read-revise-write request resolves to ACT_RD_PRE and ACT_WE_PRE.
The read-write sequence of relevant memory bank and other ins and outs can be referring to " DDR3 SDRAM Specification ".It should be noted that the embodiment of the invention only enumerated operational order type commonly used, such as ACT, RD, WE, PRE, for the operational order of unlisted other types, technical solution of the present invention is applicable equally.
The below specifies request analysis unit 11 and how access request is resolved to the operational order sequence.In the present embodiment, described storer (for example SDRAM) comprises 2 Rank.As shown in Figure 3, described request resolution unit 11 comprises two resolution unit that are associated with described set of memory banks, i.e. the first resolution unit 111 and the second resolution unit 112.Each resolution unit is associated with a Rank, and for example in the present embodiment, the first resolution unit 111 is associated with Rank0, and the second resolution unit 112 is associated with Rank1.Each described resolution unit comprises some parsing modules that are associated with described memory bank.
In the present embodiment, the first resolution unit 111 comprises 4 parsing module M00, the M01, M02, the M03 that are associated with Bank.Owing to comprise 8 Bank (Bank0 to Bank7) among the Rank0, and first resolution unit 111 related with Rank0 comprises 4 parsing modules, so corresponding two Bank of each parsing module, namely can set parsing module M00 and be associated with Bank0 and Bank4, parsing module M01 is associated with Bank1 and Bank5, parsing module M02 is associated with Bank2 and Bank6, and parsing module M03 is associated with Bank3 and Bank7.
Correspondingly, continue with reference to figure 3, described the second resolution unit 112 comprises 4 parsing module M10, M11, M12, M13 that are associated with Bank.Owing to comprise 8 Bank (Bank0 to Bank7) among the Rank1, and second resolution unit 112 related with Rank1 comprises 4 parsing modules, so corresponding two Bank of each parsing module, namely can set parsing module M10 and be associated with Bank0 and Bank4, parsing module M11 is associated with Bank1 and Bank5, parsing module M12 is associated with Bank2 and Bank6, and parsing module M13 is associated with Bank3 and Bank7.Be that each parsing module " is responsible for " two Bank.
Each parsing module all can resolve to the operational order sequence with access request (for example " read request ", " write request " or " reading-revise-write request ").Take parsing module M00 as example: when parsing module M00 has received that a target is after the Bank4 of Rank0 " read request ", will send first an act command, then send a RD order, send at last a PRE order, above-mentioned three operational orders form an ACT_RD_PRE operational order sequence, and the Action Target of this operational order sequence is Bank corresponding to parsing module M00.
If send at parsing module M00 read request operational order sequence A CT_RD_PRE during, parsing module M01 receives an access request, for example target is the read request of the Bank1 of Rank0, parsing module M01 also can at first send act command so, then send the RD order, send at last the PRE order, above-mentioned three operational orders also form an ACT_RD_PRE operational order sequence, different from parsing module M00 is that the Action Target of the operational order sequence A CT_RD_PRE that parsing module M01 sends is Bank corresponding to parsing module M01.
By the general treatment scheme of aforementioned access request (comprise read request, write request or read-revise-write request) as can be known, request analysis unit 11 is to storer, SDRAM for example, in the time of the transmit operation command sequence, be not that the operational order in this operational order sequence is sent to SDRAM simultaneously.Particularly, for being resolved the operational order sequence A CT_RD_PRE form by read request, three operational order ACT, RD and PRE are sent to SDRAM simultaneously, need to follow certain constraint condition between the operational order.This constraint condition is to be determined by the physical characteristics of storer.For example, after memory access control device 11 sends an operational order ACT to SDRAM, at once transmit operation order RD, but must wait for the regular hour first, after device SDRAM to be stored is ready to, could continue transmit operation order RD.
For this reason, also comprise arbitration unit in the memory access control device of the storer that provides of the embodiment of the invention.See also Fig. 4, described arbitration unit 12 comprises:
The first temporal constraint register, the quantity of the quantity of its quantity and the type of operational order, the quantity of set of memory banks and the memory bank in the set of memory banks is related.
The second temporal constraint register, the quantity of its quantity and the type of operational order and the quantity of set of memory banks are related.
The 3rd temporal constraint register, its quantity is related with the quantity of the type of operational order.
Writing unit 126, be used for after the transmit operation order, write numerical value to the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register corresponding to the type of the operational order that has sent, the numerical associations of said write is in the clock period of described storer and the time interval requirement between the operational order; The numerical value of each temporal constraint register reduces to 0 based on the clock period of described storer certainly from the numerical value that writes.
The time interval that the memory access control device of the storer of the embodiment of the invention sends by adjacent operational order in the value control operation command sequence that the temporal constraint register is set.For example, if need to wait for that 9 clock period could transmit operation order RD after the transmit operation order ACT, then after having sent operational order ACT, value that can the temporal constraint register is set to 9, then whenever the value of this temporal constraint register is subtracted 1 through a clock period, when the value of this temporal constraint register is 0, also namely passed through 9 clock period, but this moment is with regard to transmit operation order RD.So, utilize the temporal constraint register can realize temporal constraint between the operational order.
It should be noted that the time interval between the operational order requires relevant with the storer that adopts.The memory access control device of storer adopts configurable mode in the embodiment of the invention, and the numerical value of each write timing constraint register and physical characteristics and the clock of storer are periodic associated.For example, if require to be 15ns (physical characteristics that depends on storer) that the clock period is 1.5ns, then can write numerical value 15ns/1.5ns=10 in the temporal constraint register of correspondence from operational order ACT to the time interval the operational order RD.
Particularly, see also Fig. 4, arbitration unit 12 comprises several the first temporal constraint registers, several the second temporal constraint registers and several the 3rd temporal constraint registers.The quantity of the type of hypothesis operational order is c in the present embodiment, and the quantity of set of memory banks (Rank) is n, and the quantity of memory bank among each Rank (Bank) is m.
The quantity of the quantity of the quantity of described the first temporal constraint register and the type of operational order, the quantity of set of memory banks and the memory bank in the set of memory banks is related.
In the present embodiment, the quantity of described the first temporal constraint register can be:
Be that described arbitration unit 12 comprises
Individual the first temporal constraint register sees Table 1.
Table 1. the first temporal constraint register
The quantity of the quantity of described the second temporal constraint register and the type of operational order and the quantity of set of memory banks are related.
In the present embodiment, the quantity of described the second temporal constraint register can be:
n×c
2，
Be that described arbitration unit 12 comprises n * c
2=2 * 4
2=32 the second temporal constraint registers see Table 2.
Table 2. the second temporal constraint register
The quantity of described the 3rd temporal constraint register is related with the quantity of the type of operational order.
In the present embodiment, the quantity of described the 3rd temporal constraint register can be: c
2,
Be that described arbitration unit 12 comprises c
2=4
2=16 the 3rd temporal constraint registers see Table 3.
Table 3. the 3rd temporal constraint register
" X2Y " expression " operational order X is to the constraint of operational order Y " in above-mentioned the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.For example, ACT2RD represents operational order ACT to the constraint of operational order RD, and the operational order ACT that namely sends first is to the time interval requirement of the operational order RD of rear transmission.
The target that the below sends take a parsing module M03 is the operational order sequence of the Bank3 of Rank0 describes the memory access control device of described storer in detail as example the course of work.
Parsing module M03 in the request analysis unit receives the read request that the user sends, as previously mentioned, parsing module M03 can send first an act command, then send a RD order, send at last a PRE order, above-mentioned three operational orders form an ACT_RD_PRE operational order sequence, and the Action Target of this operational order sequence is Bank corresponding to parsing module M03.
At first, for operational order ACT, it sends target is the Bank3 of Rank0, and then whether the value of the following register of control module inspection in the arbitration unit 12 is 0:
Rank0_SameBank37_ACT2ACT；Rank0_SameBank37_RD2ACT；
Rank0_SameBank37_WE2ACT；?Rank0_SameBank37_PRE2ACT；
Above-mentioned four registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2ACT；Rank0_DiffBank_RD2ACT；
Rank0_DiffBank_WE2ACT；?Rank0_DiffBank_PRE2ACT；
Above-mentioned four registers belong to the second temporal constraint register.
DiffRank_ACT2ACT；DiffRank_RD2ACT；
DiffRank_WE2ACT；?DiffRank_PRE2ACT。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
The value that checks above-mentioned the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register when control module is 0, described arbitration unit 12 arbitrations are by described operational order ACT, and the memory access control device of described storer sends described operational order ACT to described storer.If the value of above-mentioned register all is not 0, then above-mentioned register is simultaneously from subtracting, and for example each clock period is from subtracting 1; If the value of above-mentioned register is not that 0 (value of some register is 0 entirely, the value of some register is not 0), so, in next clock period, described request resolution unit 11 continues to send this operational order ACT, and described control module continues to check whether the value of above-mentioned register is 0, until the value of above-mentioned register is 0, described arbitration unit 12 arbitrations are by described operational order ACT, and the memory access control device of described storer sends described operational order ACT to described storer.
In the present embodiment, the first temporal constraint register, the second temporal constraint register and the 3rd each clock period of temporal constraint register are from subtracting 1.In other embodiments, also can design the first temporal constraint register, the second temporal constraint register and per two clock period of the 3rd temporal constraint register or more clock period are carried out from subtracting.Correspondingly, the numerical value that writes of the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register is also different.For example, if require to be 15ns (physical characteristics that depends on storer) from operational order ACT to the time interval the operational order RD, clock period is 1.5ns, per 2 clock period of the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register then can write numerical value 15ns/ (1.5ns*2)=5 from subtracting in the temporal constraint register of correspondence.
After operational order sent, writing unit upgraded the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Particularly, writing unit writes interval confinement time to the subsequent operation order according to the type of the operational order that sent to described the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.
In the present embodiment, after operational order ACT was sent completely, the said write unit upgraded the value of following register:
Rank0_SameBank37_ACT2ACT；Rank0_SameBank37_ACT2RD；
Rank0_SameBank37_ACT2WE；?Rank0_SameBank37_ACT2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2ACT；Rank0_DiffBank_ACT2RD；
Rank0_DiffBank_ACT2WE；?Rank0_DiffBank_ACT2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2ACT；DiffRank_ACT2RD；
DiffRank_ACT2WE；?DiffRank_ACT2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Then, for operational order RD, it sends target is the Bank3 of Rank0, and then whether the value of the following register of control module inspection in the arbitration unit 12 is 0:
Rank0_SameBank37_ACT2RD；Rank0_SameBank37_RD2RD；
Rank0_SameBank37_WE2RD；?Rank0_SameBank37_PRE2RD；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2RD；Rank0_DiffBank_RD2RD；
Rank0_DiffBank_WE2RD；?Rank0_DiffBank_PRE2RD；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2RD；DiffRank_RD2RD；
DiffRank_WE2RD；?DiffRank_PRE2RD。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
ACT is similar with the transmit operation order, the value that checks above-mentioned the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register when control module is 0, described arbitration unit 12 arbitrations are by described operational order ACT, and the memory access control device of described storer sends described operational order RD to described storer.If the value of above-mentioned register all is not 0, then above-mentioned register is simultaneously from subtracting, and for example each clock period is from subtracting 1; If the value of above-mentioned register is not that 0 (value of some register is 0 entirely, the value of some register is not 0), so, in next clock period, the described request resolution unit continues to send this operational order RD, and described control module continues to check whether the value of above-mentioned register is 0, until the value of above-mentioned register is 0, described arbitration unit 12 arbitrations are by described operational order ACT, and the memory access control device of described storer sends described operational order RD to described storer.
After operational order RD was sent completely, the said write unit upgraded the value of following register:
Rank0_SameBank37_RD2ACT；Rank0_SameBank37_RD2RD；
Rank0_SameBank37_RD2WE；?Rank0_SameBank37_RD2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_RD2ACT；Rank0_DiffBank_RD2RD；
Rank0_DiffBank_RD2WE；?Rank0_DiffBank_RD2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_RD2ACT；DiffRank_RD2RD；
DiffRank_RD2WE；?DiffRank_RD2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
At last, for operational order PRE, it sends target is the Bank3 of Rank0, and then whether the value of the following register of control module inspection in the arbitration unit 12 is 0:
Rank0_SameBank37_ACT2PRE；Rank0_SameBank37_RD2PRE；
Rank0_SameBank37_WE2PRE；?Rank0_SameBank37_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2PRE；Rank0_DiffBank_RD2PRE；
Rank0_DiffBank_WE2PRE；?Rank0_DiffBank_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2PRE；DiffRank_RD2PRE；
DiffRank_WE2PRE；DiffRank_PRE2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Similarly, the value that checks above-mentioned the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register when control module is 0, described arbitration unit 12 arbitrations are by described operational order ACT, and the memory access control device of described storer sends described operational order PRE to described storer.
After operational order PRE was sent completely, the said write unit upgraded the value of following register:
Rank0_SameBank37_PRE2ACT；Rank0_SameBank37_PRE2RD；
Rank0_SameBank37_PRE2WE；?Rank0_SameBank37_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_PRE2ACT；Rank0_DiffBank_PRE2RD；
Rank0_DiffBank_PRE2WE；?Rank0_DiffBank_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_PRE2ACT；DiffRank_PRE2RD；
DiffRank_PRE2WE；?DiffRank_PRE2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
So far, the operational order sequence A CT_RD_PRE that sends of parsing module M03 all is sent to storer.
It will be appreciated by those skilled in the art that preamble has only exemplarily provided the process of parsing module M03 transmit operation command sequence, said process is equally applicable to parsing module M00-M02, M10-M13.And, in the process of parsing module M03 transmit operation command sequence, other parsing modules, for example parsing module M00-M02, M10-M13 also can send other operational order sequences concurrently.So, utilize the memory access control device of the storer of technical solution of the present invention to walk abreast and send a plurality of operational order sequences, improve the memory access efficient of storer.
It should be noted that register during subtracting, if the subsequent operation order arrives the temporal constraint register, as long as then there is operational order to pass through arbitration unit, writing unit is just revised the value of corresponding temporal constraint register.
Illustrate, if parsing module M11 sends the first operational order sequence A CT_RD_PRE, the target of described the first operational order sequence is the Bank1 of Rank1 or the Bank5 of Rank1.Parsing module M12 sends the second operational order sequence A CT_RD_PRE, and the target of described the second operational order sequence is the Bank2 of Rank1 or the Bank6 of Rank1.
Operational order RD in described the first operational order sequence is sent to storer after by arbitration unit, and the writing unit in the arbitration unit will upgrade the value of corresponding the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Suppose that writing unit is updated to 10 with the value of Rank1_DiffBank_RD2RD for the second temporal constraint register, the value of Rank1_DiffBank_RD2WE is updated to 20.Above-mentioned temporal constraint register carried out from subtracting in each clock period, so after 10 clock period, the value of Rank1_DiffBank_RD2RD is that the value of 0, Rank1_DiffBank_RD2WE is 10.
If the operational order RD in the second operational order sequence arrives and passes through arbitration unit at this moment, then the writing unit in the arbitration unit also will upgrade corresponding the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Be above-mentioned temporal constraint register Rank1_DiffBank_RD2RD, the value of Rank1_DiffBank_RD2WE also is updated, and writing unit is updated to 10 with the value of Rank1_DiffBank_RD2RD, and the value of Rank1_DiffBank_RD2WE is updated to 20.
That is, register is during subtracting, as long as there is operational order to pass through arbitration unit, writing unit is just revised the value of corresponding temporal constraint register.
In the present embodiment, each resolution unit comprises four parsing modules in the request analysis unit, corresponding two Bank of each parsing module, and arbitration unit is arbitrated by the operational order that three groups of above-mentioned parsing modules of temporal constraint register pair send.
In other embodiments, the quantity of parsing module also can be not limited to four in the resolution unit, for example resolution unit can comprise two parsing modules, corresponding four Bank of each parsing module, in this case, arbitration unit still can be arbitrated by the operational order that three groups of above-mentioned parsing modules of temporal constraint register pair send.Different from above-described embodiment is that the quantity of the first temporal constraint register, the second temporal constraint register and/or the 3rd temporal constraint register can correspondingly change in the arbitration unit.For example, if the resolution unit of corresponding Rank0 comprises two parsing modules, one of them parsing module corresponding Bank0, Bank1, Bank2, Bank3, another parsing module corresponding Bank4, Bank5, Bank6, Bank7.With reference to figure 4, for the first temporal constraint register, as long as will change corresponding to the first temporal constraint register of Rank0_SameBank04, Rank0_SameBank15, Rank0_SameBank26 and Rank0_SameBank37 the first temporal constraint register corresponding to Rank0_SameBank0123 and Rank0_SameBank4567 into, each first temporal constraint register indoor design and principle of work are constant, only change four groups of original temporal constraint registers into present two groups of temporal constraint registers.
It should be noted that, stipulate that each Rank comprises 8 Bank in the existing relevant standard of SDRAM, but the application of technical solution of the present invention is not limited to each Rank of above-mentioned correlation standard comprises 8 Bank situations, for example, if each Rank comprises 16 Bank, then adjust in the resolution unit incidence relation of parsing module and Bank and can also realize technique effect of the present invention.
With reference to figure 5, another embodiment of the memory access control device 10A of storer of the present invention comprises request analysis unit 11 and arbitration unit 12A.
Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank (Bank); Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks (Rank); Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
In the present embodiment, arbitration unit 12A comprises:
The first temporal constraint judging unit 121, whether the time interval that is used for judging the transmitting time of current time and last operational order satisfies the first temporal constraint between current operational order and the last operational order, and described current operational order and described last operational order belong to same operational order sequence.
The second temporal constraint judging unit 122 is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the second temporal constraint between the described last operational order.
The 3rd temporal constraint judging unit 123 is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the 3rd temporal constraint between the described last operational order.
Transmitting element 124, it is to send described current operational order to described storer that the judged result that is used for the judged result of judged result, the second temporal constraint judging unit when described the first temporal constraint judging unit and the 3rd sequential judging unit is.
It will be appreciated by those skilled in the art that, the all or part of of technique scheme is to come the relevant hardware of instruction to finish by program, described program can be stored in the computer-readable recording medium, and described storage medium can be ROM, RAM, magnetic disc, CD etc.
Described access request comprises read request, write request or reads-revise-write request.Described operational order is activation command (ACT), read command (RD), write order (WE) or writes back order (PRE).
If described access request is read request, described resolution unit resolves to operational order sequence A CT_RD_PRE with described access request.
If described access request is write request, described resolution unit resolves to operational order sequence A CT_WE_PRE with described access request.
If described access request is for reading-revise-write request, described resolution unit can resolve to described access request operational order sequence A CT_RD_WE_PRE, also described access request can be resolved to operational order sequence A CT_RD_PRE and ACT_WE_PRE.
The control device that it should be noted that the storer of technical solution of the present invention can be integrated in the north bridge chips, also can be integrated in the processor (for example CPU).If the control device of this storer is integrated in the north bridge chips, can think that then user's access request is to be sent in the control device of this storer by processor (for example CPU); If the control device of storer is integrated in the processor (for example CPU), can think that then access request is the control device that is sent to this storer by the modules such as internet, transfer bus on the sheet of processor inside.
The memory access control device of corresponding above-mentioned storer, technical solution of the present invention also provides a kind of access control method of storer.Consult Fig. 6, the access control method of described storer comprises:
S1: access request is resolved to the operational order sequence, and described operational order sequence comprises some operational orders.
S2: the operational order in the described operational order sequence is arbitrated by referee conditions, so that operational order is sent to storer, described referee conditions comprises: described operational order is sent to the time interval satisfied the first temporal constraint, the second temporal constraint and the 3rd temporal constraint of described storer.
Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank (Bank); Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks (Rank); Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
Described access request comprises read request, write request or reads-revise-write request.Described operational order is activation command (ACT), read command (RD), write order (WE) or writes back order (PRE).
If described access request is read request, described resolution unit resolves to operational order sequence A CT_RD_PRE with described access request.
If described access request is write request, described resolution unit resolves to operational order sequence A CT_WE_PRE with described access request.
If described access request is for reading-revise-write request, described resolution unit can resolve to described access request operational order sequence A CT_RD_WE_PRE, also described access request can be resolved to operational order sequence A CT_RD_PRE and ACT_WE_PRE.
In one embodiment, by referee conditions the operational order in the described operational order sequence is arbitrated described in the step S2, comprises so that operational order is sent to storer:
After the transmit operation order, write numerical value to the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register corresponding to the type of the operational order that has sent, the numerical associations of said write is in the clock period of described storer and the time interval requirement between the operational order; The numerical value of each temporal constraint register reduces to 0 based on the clock period of described storer certainly from the numerical value that writes.
When corresponding to the type of the operational order that does not send and specify the first temporal constraint register of the memory bank in the set of memory banks of access numerical value, corresponding to the type of the described operational order that does not send and specify access set of memory banks the second temporal constraint register numerical value and be 0 corresponding to the numerical value of the 3rd temporal constraint register of the type of the described operational order that does not send, sends extremely described storer of the described operational order that does not send.
The quantity m of the quantity c of the quantity of described the first temporal constraint register and the type of operational order, the quantity n of set of memory banks and the memory bank in the set of memory banks is related.
The quantity c of the quantity of described the second temporal constraint register and the type of operational order and the quantity n of set of memory banks are related.
The quantity of described the 3rd temporal constraint register is related with the quantity c of the type of operational order.
In the present embodiment, the quantity of described the first temporal constraint register can for
The quantity of described the second temporal constraint register can be n * c
2The quantity of described the 3rd temporal constraint register can be c
2
In another embodiment, by referee conditions the operational order in the described operational order sequence is arbitrated described in the step S2, comprises so that operational order is sent to storer:
Whether the time interval of judging the transmitting time of current time and last operational order satisfies the first temporal constraint between current operational order and the last operational order, and described current operational order and described last operational order belong to same operational order sequence.
Judge whether the time interval of the transmitting time of described current time and described last operational order satisfy described current operational order and the second temporal constraint between the described last operational order.
Judge whether the time interval of the transmitting time of described current time and described last operational order satisfy described current operational order and the second temporal constraint between the described last operational order.
Be in the situation that is in above-mentioned judged result, send described current operational order to described storer.
Technical solution of the present invention also provides a kind of processor, comprises the memory access control device of above-mentioned storer.Access request is sent to the memory access control device of described storer by the modules such as internet, transfer bus on the sheet of described processor inside.The process that the memory access control device of described storer resolves to the operational order sequence with access request and is sent to storer please refer to above-described embodiment, and this does not give unnecessary details.
Technical solution of the present invention also provides a kind of north bridge chips, comprises the memory access control device of above-mentioned storer.Access request is sent to the memory access control device of the described storer that is integrated in the described north bridge chips by processor (for example CPU).The process that the memory access control device of described storer resolves to the operational order sequence with access request and is sent to storer please refer to above-described embodiment, and this does not give unnecessary details.
The memory access control device of the storer that the embodiment of the invention proposes has improved memory bandwidth greatly in the situation that does not obviously increase hardware spending, reduced memory access latency.Particularly:
The commercial chip of available technology adopting " body walk abreast memory access strategy " has only been considered the temporal constraint situation between the memory bank (Bank), and does not consider the temporal constraint situation between the memory set (Rank).Realize that the register quantity that existing " body walk abreast memory access strategy " needs to use is: 128+16=144 is individual.
The memory access control device of the storer that the embodiment of the invention proposes had both been considered the temporal constraint situation between the memory bank (Bank), had considered again the temporal constraint situation between the set of memory banks (Rank), had realized the parallel memory access of the multidimensional of storer.The register quantity that technical solution of the present invention is used is the quantity sum of the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register, that is: 128+32+16=176.Therefore, the hardware costs of technical solution of the present invention has only increased (176-144)/144=22.2%, but can fully excavate the parallel memory access ability between the set of memory banks (Rank).
In sum, with respect to prior art, technical solution of the present invention is by concurrently transmit operation command sequence of request analysis unit, and utilize the first temporal constraint, the second temporal constraint and the control of the 3rd temporal constraint to send current operation order in the same operational order sequence and the time interval between the last operational order adjacent with described current operation order, not only can a plurality of memory banks of concurrent access (Bank), and can a plurality of set of memory banks of concurrent access (Rank), realized the multidimensional memory access that walks abreast.Experiment showed, that technical solution of the present invention can significantly shorten the average handling time of access request, improve entire system memory access performance.In addition, with respect to the traditional controller of existing employing " body walk abreast memory access strategy ", technical solution of the present invention does not obviously increase hardware yet and realizes cost.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (21)
1. the memory access control device of a storer is characterized in that, comprising:
The request analysis unit is used for access request is resolved to the operational order sequence, and described operational order sequence comprises some operational orders;
Arbitration unit, be used for by referee conditions the operational order of described operational order sequence being arbitrated, operational order is sent to described storer, described referee conditions comprises: operational order is sent to the time interval satisfied the first temporal constraint, the second temporal constraint and the 3rd temporal constraint of described storer;
Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank; Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks; Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
2. the memory access control device of storer according to claim 1 is characterized in that, the described request resolution unit comprises two resolution unit that are associated with described set of memory banks, and each resolution unit comprises some parsing modules that are associated with described memory bank.
3. the memory access control device of storer according to claim 1 is characterized in that, described arbitration unit comprises:
The first temporal constraint register, the quantity m of the quantity c of its quantity and the type of operational order, the quantity n of set of memory banks and the memory bank in the set of memory banks is related;
The second temporal constraint register, the quantity c of its quantity and the type of operational order and the quantity n of set of memory banks are related;
The 3rd temporal constraint register, its quantity is related with the quantity c of the type of operational order;
Writing unit, be used for after the transmit operation order, write numerical value to the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register corresponding to the type of the operational order that has sent, the numerical associations of said write is in the clock period of described storer and the time interval requirement between the operational order;
The numerical value of each temporal constraint register reduces to 0 based on the clock period of described storer certainly from the numerical value that writes;
Control module, be used for when corresponding to the type of the operational order that does not send and specify access set of memory banks memory bank the first temporal constraint register numerical value, corresponding to the type of the described operational order that does not send and specify access set of memory banks the second temporal constraint register numerical value and be 0 corresponding to the numerical value of the 3rd temporal constraint register of the type of the described operational order that does not send, sends extremely described storer of the described operational order that does not send.
4. the memory access control device of storer according to claim 3 is characterized in that,
The quantity of described the first temporal constraint register is
The quantity of described the second temporal constraint register is n * c
2
The quantity of described the 3rd temporal constraint register is c
2
5. the memory access control device of storer according to claim 1 is characterized in that, described arbitration unit comprises:
The first temporal constraint judging unit, whether the time interval that is used for judging the transmitting time of current time and last operational order satisfies the first temporal constraint between current operational order and the last operational order, and described current operational order and described last operational order belong to same operational order sequence;
The second temporal constraint judging unit is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the second temporal constraint between the described last operational order;
The 3rd temporal constraint judging unit is used for judging whether the time interval of the transmitting time of described current time and described last operational order satisfies described current operational order and the 3rd temporal constraint between the described last operational order;
Transmitting element, it is to send described current operational order to described storer that the judged result that is used for the judged result of judged result, the second temporal constraint judging unit when described the first temporal constraint judging unit and the 3rd sequential judging unit is.
6. the memory access control device of storer according to claim 1 is characterized in that, described access request is read request, write request or reads-revise-write request.
7. the memory access control device of storer according to claim 1 is characterized in that, described operational order is activation command, read command, write order or writes back order.
8. the memory access control device of storer according to claim 1 is characterized in that, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
9. the memory access control device of storer according to claim 1 is characterized in that, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
10. the memory access control device of storer according to claim 1 is characterized in that, described access request is for reading-revise-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Perhaps, described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
11. the access control method of a storer is characterized in that, comprising:
Access request is resolved to the operational order sequence, and described operational order sequence comprises some operational orders;
By referee conditions the operational order in the described operational order sequence is arbitrated, so that operational order is sent to storer, described referee conditions comprises: described operational order is sent to the time interval satisfied the first temporal constraint, the second temporal constraint and the 3rd temporal constraint of described storer;
Described the first temporal constraint refers to access the time interval requirement between the operational order of same memory bank; Described the second temporal constraint refers to access the time interval requirement between the operational order of different bank in the same set of memory banks; Described the 3rd temporal constraint refers to access the time interval requirement between the operational order of different bank group.
12. the access control method of storer according to claim 11 is characterized in that, describedly by referee conditions the operational order in the described operational order sequence is arbitrated, and comprises so that operational order is sent to storer:
After the transmit operation order, write numerical value to the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register corresponding to the type of the operational order that has sent, the numerical associations of said write is in the clock period of described storer and the time interval requirement between the operational order;
The numerical value of each temporal constraint register reduces to 0 based on the clock period of described storer certainly from the numerical value that writes;
When corresponding to the type of the operational order that does not send and specify the first temporal constraint register of the memory bank in the set of memory banks of access numerical value, corresponding to the type of the described operational order that does not send and specify access set of memory banks the second temporal constraint register numerical value and be 0 corresponding to the numerical value of the 3rd temporal constraint register of the type of the described operational order that does not send, sends extremely described storer of the described operational order that does not send;
The quantity m of the quantity c of the quantity of described the first temporal constraint register and the type of operational order, the quantity n of set of memory banks and the memory bank in the set of memory banks is related;
The quantity c of the quantity of described the second temporal constraint register and the type of operational order and the quantity n of set of memory banks are related;
The quantity of described the 3rd temporal constraint register is related with the quantity c of the type of operational order.
13. the access control method of storer according to claim 12 is characterized in that,
The quantity of described the first temporal constraint register is
The quantity of described the second temporal constraint register is n * c
2
The quantity of described the 3rd temporal constraint register is c
2
14. the access control method of storer according to claim 11 is characterized in that, describedly by referee conditions the operational order in the described operational order sequence is arbitrated, and comprises so that operational order is sent to storer:
Whether the time interval of judging the transmitting time of current time and last operational order satisfies the first temporal constraint between current operational order and the last operational order, and described current operational order and described last operational order belong to same operational order sequence;
Judge whether the time interval of the transmitting time of described current time and described last operational order satisfy described current operational order and the second temporal constraint between the described last operational order;
Judge whether the time interval of the transmitting time of described current time and described last operational order satisfy described current operational order and the second temporal constraint between the described last operational order;
Be in the situation that is in above-mentioned judged result, send described current operational order to described storer.
15. the access control method of storer according to claim 11 is characterized in that, described access request is read request, write request or reads-revise-write request.
16. the access control method of storer according to claim 11 is characterized in that, described operational order is activation command, read command, write order or writes back order.
17. the access control method of storer according to claim 11 is characterized in that, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
18. the access control method of storer according to claim 11 is characterized in that, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
19. the access control method of storer according to claim 11 is characterized in that, described access request is for reading-revise-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Perhaps, described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
20. a processor is characterized in that, comprises the memory access control device of each described storer in the claim 1 to 10.
21. a north bridge chips is characterized in that, comprises the memory access control device of each described storer in the claim 1 to 10.
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