CN103367399B - The formation method of transistor and transistor - Google Patents
The formation method of transistor and transistor Download PDFInfo
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- CN103367399B CN103367399B CN201210093559.4A CN201210093559A CN103367399B CN 103367399 B CN103367399 B CN 103367399B CN 201210093559 A CN201210093559 A CN 201210093559A CN 103367399 B CN103367399 B CN 103367399B
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Abstract
The invention provides a kind of formation method of transistor and transistor.Described transistor comprises: Semiconductor substrate; Be positioned at the grid structure of described Semiconductor substrate upper surface; And, be positioned at described Semiconductor substrate and be positioned at the groove of described grid structure both sides; Be positioned at the source electrode of described grid structure side groove; And be positioned at the drain electrode of described grid structure opposite side groove, described groove comprises Part I and Part II, described Part I is connected with the upper surface of described Semiconductor substrate, and described Part II and described Part I be through to be connected and to extend to the below of described grid structure.Described source electrode and described drain electrode, both near channel region, have again larger volume, when described source electrode and described drain electrode are served as by the stressor layers of adulterating, can produce more significantly effect of stress, improve the mobility of charge carrier further to channel region.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of formation method of transistor and transistor.
Background technology
In existing semiconductor fabrication process, the introducing of stress can change the lattice parameter of silicon materials, thus changes its energy gap and carrier mobility, and the electric property therefore improving transistor by introducing stressor layers becomes more and more conventional means.
Be in the United States Patent (USP) of US7569443B2, disclose a kind of method adopting embedded germanium silicon (EmbeddedSiGe) technology to improve the performance of transistor in the patent No., namely need the region forming source electrode and drain electrode first to form germanium silicon layer, and then carry out source electrode and drain electrode that doping forms transistor.Owing to there is lattice misfit (LatticeMismatch) in the two-phase interface (Interphase) of silicon and germanium silicon, germanium silicon layer can produce effect of stress to channel region, changes silicon crystal lattice arrangement wherein.Therefore, the carrier mobility in channel region is improved, thus improves the performance of transistor.
For 45 nanometer technology nodes and above semiconductor fabrication process, get a greater increase to make the performance of transistor, prior art adopt described stressor layers made more near channel region to promote the stress in channel region larger, specifically please refer to Fig. 1 to Fig. 3.
First, with reference to figure 1, provide Semiconductor substrate 100.
The upper surface of described Semiconductor substrate 100 is formed with grid structure 110.The first groove 120 being positioned at described grid structure 110 both sides is formed in described Semiconductor substrate 100.
Then, with reference to figure 2, anisotropic wet etch (AnisotropicWetEtch) is carried out to described first groove 120, described first groove 120 is extended below described grid structure 110 and extends to described Semiconductor substrate 100 lower surface, forming the second groove 130.
Described second groove 130 can have various types of bowl-type shape, the profile that such bowl-type shape shows in illustrated section is the class bowl-type of various shape, but all there is the part extended to below grid structure, such as, utilize Tetramethylammonium hydroxide (tetramethylammoniumhydroxide, TMAH) solution carries out described anisotropic wet etch, obtain groove as shown in Figure 2, the profile that this groove shows in illustrated section is have wedge angle outstanding below grid structure.
Then, with reference to figure 3, in described second groove 130, form stressor layers 140.Because described stressor layers 140 extends to below described grid structure 110, therefore, described stressor layers is more near channel region, and the stress produced can bring more obvious effect.
In order to obtain larger effect of stress, prior art also adopts the mode increasing stressor layers volume.The volume increasing stressor layers just needs the volume increasing described second groove.Such as, the time of described anisotropic wet etch is extended to increase the volume of described second groove.But the long base area of described second groove that easily causes of etch period is too small.Even, as used shown in dotted line in Fig. 2, the bottom of the second groove 130 ' of formation is to the outstanding wedge angle of the lower surface of described Semiconductor substrate 100.Too small base area is unfavorable for that subsequently epitaxial growing forms stressor layers, and the bottom of stressor layers occurs that outstanding wedge angle easily causes harmful effect to the performance of device downwards.
Prior art also adopts a kind of mode to increase the volume of the second groove, namely the volume of described first groove is first expanded, the bottom surface of described first groove and sidewall can be made respectively to the lower surface of Semiconductor substrate due to anisotropic wet etch and extend below grid structure, thus obtain having the second groove of the part extended to below grid structure, therefore, the volume that the volume expanding the first groove correspondingly can expand the second groove also can become large.But the method also needs to etch away more semiconductor substrate materials, extend etch period.
Along with the development of semiconductor technology, more and more higher to the requirement of device performance, therefore, need a kind of transistor and forming method thereof, larger effect of stress can be produced to channel region, thus improve the mobility of charge carrier further, improve the performance of transistor.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, source electrode and drain electrode are more near channel region, and there is larger volume, when source electrode and drain electrode are served as by the stressor layers of adulterating, larger effect of stress can be produced to channel region, thus improve the mobility of charge carrier further, improve the performance of transistor.
For solving the problem, embodiments of the invention provide a kind of transistor, comprising: Semiconductor substrate; Be positioned at the grid structure of described Semiconductor substrate upper surface; And, be positioned at described Semiconductor substrate and be positioned at the groove of described grid structure both sides; Be positioned at the source electrode of described grid structure side groove; And be positioned at the drain electrode of described grid structure opposite side groove, described groove comprises Part I and Part II, described Part I is connected with the upper surface of described Semiconductor substrate, and described Part II and described Part I be through to be connected and to extend to the below of described grid structure.
Alternatively, have the stressor layers of doping in described groove, the stressor layers being positioned at the doping of described grid structure side groove, as described source electrode, is positioned at the stressor layers of the doping of described grid structure opposite side groove as described drain electrode.
Alternatively, the altitude range of described Part I is 2 ~ 40nm, and the altitude range of described Part II is 2 ~ 100nm.
Alternatively, the altitude range of described Part I is 10 ~ 30nm, and the altitude range of described Part II is 30 ~ 100nm.
Alternatively, described transistor is PMOS transistor, and the material of the stressor layers of described doping is SiGe.
Alternatively, described transistor is nmos pass transistor, and the material of the stressor layers of described doping is SiC.
Correspondingly, embodiments of the invention also provide a kind of formation method of transistor, comprising:
Semiconductor substrate is provided;
Form grid structure on the semiconductor substrate;
Described Semiconductor substrate and described grid structure are formed first mask layer with opening;
With described first mask layer for mask, remove part Semiconductor substrate along opening dry etching, form the first groove in grid structure both sides;
Form the second mask layer covering described first trenched side-wall;
Along the first trench dry etch semiconductor substrates, form the second groove;
With described second mask layer for mask, the bottom surface of wet etching second groove and sidewall, make described second groove extend below described grid structure and extend to described Semiconductor substrate lower surface, and described first groove and the second groove after extending are as groove;
Remove described second mask layer; And
Form the source electrode of transistor at the groove being arranged in described grid structure side, form the drain electrode of transistor at the groove being arranged in described grid structure opposite side.
Alternatively, formation covering described second mask layer of described first trenched side-wall and the step of described second groove specifically comprise: formed and cover described substrate, described grid structure and the bottom surface of described first groove and the second mask layer of sidewall; And utilize dry etching, remove the second mask layer being positioned at described first trench bottom surfaces, and along the first trench dry etch semiconductor substrates, form the second groove.
Alternatively, the dry etch process parameter forming described first groove comprises: etching pressure 10 ~ 200mTorr, HBr flow 100 ~ 1000sccm, O
2flow 2 ~ 20sccm, He flow 100 ~ 1000sccm, Cl
2flow 2 ~ 200sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
Alternatively, the dry etch process forming described second groove is plasma etching industrial.
Alternatively, when described second mask layer is silica, the parameter of described plasma etching industrial comprises: etching pressure 1 ~ 200mTorr, CF
4flow 2 ~ 200sccm, O
2flow 2 ~ 20sccm, He flow 10 ~ 500sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time; When described second mask layer is silicon nitride, the parameter of described plasma etching industrial comprises: etching pressure 1 ~ 200mTorr, CF
4or CHF
3flow 2 ~ 200sccm, O
2flow 2 ~ 500sccm, He flow 10 ~ 1000sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
Alternatively, the etching agent that described wet-etching technology adopts comprises: potassium hydroxide, ammoniacal liquor or tetramethyl aqua ammonia.
Alternatively, the etching agent that described wet-etching technology adopts is tetramethyl aqua ammonia, temperature 15 ~ 70 degrees Celsius, 20 ~ 500 seconds time.
Alternatively, described first mask layer is different with the material of described second mask layer.
Alternatively, the material of described first mask layer and described second mask layer is respectively the one in silica and silicon nitride.
Alternatively, the thickness range of described first mask layer or described second mask layer is 10 dust to 200 dusts.
Alternatively, before forming described first mask layer, comprise further and form the covering upper surface of described grid structure and the protective layer of sidewall, described protective layer, described first mask layer and described second mask layer form NON structure or ONO structure.
Alternatively, the altitude range of described first groove is 2 ~ 40nm, and the altitude range of the second groove after extension is 2 ~ 100nm.
Alternatively, the altitude range of described first groove is 10 ~ 30nm, and the altitude range of the second groove after extension is 30 ~ 100nm.
Alternatively, the step forming described source electrode and drain electrode comprises: the stressor layers forming doping in described groove, and the stressor layers being positioned at the doping of side groove, as described source electrode, is positioned at the stressor layers of the doping of opposite side groove as described drain electrode.
Alternatively, when described transistor is PMOS transistor, the material of the stressor layers of described doping is SiGe.
Alternatively, when described transistor is nmos pass transistor, the material of the stressor layers of described doping is SiC.
Compared with prior art, embodiments of the invention have the following advantages:
First, in the transistor that embodiments of the invention provide, described groove comprises Part I and Part II, and described Part I is connected with the upper surface of described Semiconductor substrate, and described Part II and described Part I be through to be connected and to extend to the below of described grid structure.And the groove of prior art only comprises the structure that is similar to described Part I or only comprises the structure being similar to described Part II.Therefore, compared with prior art, the source electrode formed in described groove and drain electrode are both near channel region, there is again larger volume (volume of increase corresponds to the volume of described Part I), when source electrode and drain electrode are served as by the stressor layers of adulterating, more significantly effect of stress can be produced to channel region, improve the mobility of charge carrier further.
Further, according to the formation method of the transistor that embodiments of the invention provide, in the process forming described groove, first form the first groove, the Part I of described first groove respective slot, i.e. the part of compared with prior art volume increase; Then, the sidewall and bottom surface of described first groove form the second mask layer; Then, remove the second mask layer of the first channel bottom, and remove Semiconductor substrate along the first groove, form the second groove; Then with remaining second mask layer for mask, the bottom surface of wet etching second groove and sidewall, second groove is extended to the lower surface of Semiconductor substrate, and extend to the below of grid structure, described first groove and the second groove after extending form groove, the Part II of the second groove respective slot after extension.Because the sidewall of described first groove is covered by the second mask layer, in wet-etching technology, the pattern of described first groove does not change, thus make this wet-etching technology only extend described second groove, namely, the semiconductor substrate materials needing in this step to remove is reduced, avoids the too small situation even occurring wedge angle of the bottom portion of groove area caused because etch period is long, improve the performance of device.
Further, in the specific embodiment of the invention, described first mask layer is different with the material of described second mask layer.Not only therefore, by controlling the parameter of etching technics, can more conveniently realize removing described second mask layer but also retain described first mask layer.Described first mask layer can protect described grid structure in the described stressor layers of the follow-up formation carried out and ion doping technique, makes the performance of the final transistor formed better.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the intermediate structure generalized section of the transistor forming process that prior art provides;
Fig. 4 is the generalized section of the transistor of the embodiment of the present invention;
Fig. 5 is the schematic flow sheet of the formation method of the transistor of the embodiment of the present invention;
Fig. 6 to Figure 14 is the intermediate structure generalized section of the transistor forming process of the embodiment of the present invention.
Embodiment
In order to produce larger effect of stress to channel region, thus improve the mobility of charge carrier further, improve the performance of transistor, embodiments of the invention provide a kind of a kind of formation method of transistor and transistor, both made stressor layers as the doping of source electrode and drain electrode near channel region, in turn increase the volume of stressor layers, but also the bottom area avoiding stressor layers is too small even occurs wedge angle, thus improves the performance of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail embodiments of the invention below in conjunction with accompanying drawing.A lot of detail has been set forth so that fully understand the present invention in description below.But the present invention can implement to be much different from other modes described here, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
It should be noted that, the generalized section in accompanying drawing all adopts Longitudinal cross section schematic.Longitudinal section in the present invention refers to both vertical with the upper surface of Semiconductor substrate, cross section vertical with the bearing of trend of grid structure again.
Also it should be noted that, for the ease of representing, the size of the structure in accompanying drawing is also disobeyed actual ratio and is illustrated.
With reference to figure 4, first the present invention provides a kind of transistor, comprising: Semiconductor substrate 200, is positioned at the grid structure 210 in described Semiconductor substrate 200, and is positioned at the groove of described grid structure 210 both sides in described Semiconductor substrate 200; Be positioned at the source electrode of described grid structure side groove; And be positioned at the drain electrode of described grid structure opposite side groove; In the present invention, source electrode and drain electrode are served as by the stressor layers 230 of adulterating in groove.That is, be positioned at the source electrode of stressor layers as described transistor of the doping of described grid structure 210 side, be positioned at the drain electrode of doping stressor layers as described transistor of described grid structure 210 opposite side.
Described Semiconductor substrate 200 can be silicon substrate or silicon-on-insulator substrate etc., is well known to those skilled in the art, does not repeat them here.
Described grid structure 210 comprises the gate dielectric layer be positioned in described Semiconductor substrate 200 and the gate electrode be positioned on described gate dielectric layer, also comprises the side wall being positioned at described gate dielectric layer and described gate electrode both sides.Described gate electrode, gate dielectric layer and described side wall illustrate in the mode of structure as a whole, and namely described grid structure 210 is only shown.Described gate electrode can be polygate electrodes or metal gate electrode.
Described groove comprises Part I 221 and Part II 222 (going out with dotted line frame in the diagram), and described Part I 221 is between the upper surface and described Part II 222 of described Semiconductor substrate 200.As shown in Figure 4, described Part I 221 is connected with the upper surface of described Semiconductor substrate 200, and described Part II 222 and described Part I 221 be through to be connected and to extend to the below of described grid structure 210.Described Part II 222 can have the shape of multiple types bowl-type.Such as, the longitudinal section (section namely in diagram) of described Part II 222 has to the outstanding wedge angle of the Semiconductor substrate below described grid structure 210.The longitudinal section of described Part II 222 can also have such as circular arc or other erose profiles.Inventor finds, when the longitudinal section of described Part II 222 has the wedge angle outstanding to the Semiconductor substrate below described grid structure 210, the performance of described transistor is better.
The stressor layers 230 being formed at the doping in described groove has the shape same with described groove.Owing to extending to the below of described grid structure 210, the stress that the stressor layers 230 of described doping produces can bring larger castering action to the carrier mobility in channel region.And compared with prior art, add Part I, the volume of the stressor layers 230 of therefore described doping is larger, and the region producing lattice misfit is more many, thus can produce larger stress.
It should be noted that, the technical problem that the present invention solves how to produce larger effect of stress to improve the mobility of charge carrier to channel region, therefore, the stressor layers 230 of described doping needs to extend to below grid structure in the side near described grid structure 210, but, in semiconductor fabrication process, for making simple process, workable, the structure formed often has symmetry, therefore, groove shown in accompanying drawing of the present invention, the stressor layers of doping is symmetrical structure, in class bowl-type, be only exemplary explanation, unsuitable restriction should do not formed to protection range.
In one embodiment of the invention, described transistor is PMOS transistor, and because SiGe can produce compression to channel region, be conducive to the mobility improving charge carrier (hole), therefore, the material of described stressor layers is SiGe.In another embodiment of the invention, described transistor is nmos pass transistor, and because SiC can produce tension stress to channel region, be conducive to the mobility improving charge carrier (electronics), therefore, the material of described stressor layers is SiC.
In embodiments of the invention, the height h1 scope of described Part I 221 is 2 ~ 40nm, and width d1 scope is 5 ~ 500nm, and the height h2 scope of described Part II 222 is 2 ~ 100nm, and width d2 scope is 5 ~ 500nm.
For the semiconductor fabrication process of different technologies node, the characteristic size of device is different, and correspondingly, the size of described groove is also different.For the transistor that grid long (GateLength) are 45 nanometers, in one particular embodiment of the present invention, the height h1 scope of described Part I 221 is 10 ~ 30nm, width d1 scope is 50 ~ 100nm, the height h2 scope of described Part II 222 is 30 ~ 100nm, and width d2 scope is 50 ~ 100nm.
It should be noted that, in embodiments of the invention, highly refer to the distance of object upper surface to lower surface; Width refers to object ultimate range in the horizontal direction, this horizontal direction parallel in described Semiconductor substrate upper surface and perpendicular to the bearing of trend of described grid structure.
Provide the embodiment of the method forming said structure below.
Fig. 5 is the schematic flow sheet of the formation method of the transistor of one embodiment of the invention, and the method comprises:
S301, provides Semiconductor substrate;
S303, forms grid structure on the semiconductor substrate;
S305, described Semiconductor substrate and described grid structure are formed first mask layer with opening;
S307, with described first mask layer for mask, removes part Semiconductor substrate along opening dry etching, forms the first groove in grid structure both sides;
S309, forms the second mask layer covering described first trenched side-wall;
S311, along the first trench dry etch semiconductor substrates, forms the second groove;
S313, with described second mask layer for mask, the bottom surface of wet etching second groove and sidewall, make described second groove extend below described grid structure and extend to described Semiconductor substrate lower surface, and described first groove and the second groove after extending are as groove;
S315, removes described second mask layer; And
S317, forms the source electrode of transistor at the groove being arranged in described grid structure side, form the drain electrode of transistor at the groove being arranged in described grid structure opposite side.
Below in conjunction with cross-sectional view Fig. 6 ~ Figure 14, the formation method of the transistor of the embodiment of the present invention is described in further detail.
In conjunction with reference to figure 5 and Fig. 6, perform step S301, Semiconductor substrate 300 is provided.
Described Semiconductor substrate 300 can be silicon substrate or silicon-on-insulator substrate etc., is well known to those skilled in the art, does not repeat them here.
In conjunction with reference to figure 5 and Fig. 7, perform step S303, described Semiconductor substrate 300 forms grid structure 310.
Described grid structure 310 comprises the gate dielectric layer be positioned in described Semiconductor substrate 300 and the gate electrode be positioned on described gate dielectric layer, also comprises the side wall being positioned at described gate dielectric layer and described gate electrode both sides.Described gate electrode, gate dielectric layer and described side wall illustrate in the mode of structure as a whole, and namely described grid structure 310 is only shown.Described gate electrode can be polygate electrodes or metal gate electrode.The technique forming grid structure is well known to those skilled in the art, and does not repeat them here.
In one embodiment of the invention, the step forming protective layer is also comprised.Described protective layer covers described grid structure 310, namely covers upper surface and the sidewall of described grid structure, and this is protective layer used in protecting described grid structure 310 unaffected in follow-up technique.The material of described protective layer can be oxide or nitride, as silica or silicon nitride.Also can not comprise the step forming described protective layer, and adopt the first mask layer of follow-up formation to protect described grid structure 310.
It should be noted that, below describe and will be further described not form protective layer on described grid structure 310.
In conjunction with reference to figure 5 and Fig. 8, perform step S305, described Semiconductor substrate 300 and described grid structure 310 are formed first mask layer 320 with opening 330.
Be positioned at the position of the source electrode of the corresponding described transistor in position of the opening of described grid structure 310 side, be positioned at the position of the drain electrode of the corresponding described transistor in position of the opening of described grid structure 310 opposite side.
Described first mask layer 320 for protecting described grid structure 310 and not needing the described Semiconductor substrate 300 of part that is etched in subsequent technique.
The step forming described first mask layer 320 specifically comprises: form the first mask layer covering described Semiconductor substrate 300 and described grid structure 310; Described first mask layer utilize photoetching process to form graphical photoresist layer; With described patterned photoresist layer for mask, etch described first mask layer, form described opening 330, first mask layer with opening is described first mask layer; And, remove described photoresist layer.
The material of described first mask layer 320 can be silica or silicon nitride, and the scope of thickness is 10 dust to 200 dusts.
The corresponding source electrode of transistor in position of described opening 330 and the position of drain electrode, do not repeat them here.
In conjunction with reference to figure 5 and Fig. 9, with described first mask layer 320 for mask, remove part Semiconductor substrate along described opening 330 dry etching, form the first groove 341 in described grid structure 310 both sides.
Described first groove 341 is connected with the upper surface of described Semiconductor substrate 300.
In one embodiment of the invention, the technological parameter forming the dry etching of described first groove 341 comprises: etching pressure 10 ~ 200mTorr, HBr flow 100 ~ 1000sccm, O
2flow 2 ~ 20sccm, He flow 100 ~ 1000sccm, Cl
2flow 2 ~ 200sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
Described first groove 341 corresponds to the Part I of the groove of follow-up formation, and the volume of described first groove 341 corresponds to the part compared with prior art increased in the volume of the stressor layers of the doping of follow-up formation.In an embodiment of the present invention, the height h3 scope of described first groove 341 is 2 ~ 40nm, and width d3 scope is 5 ~ 500nm.Particularly, the transistor formed for 45 nanometer technology nodes, in one embodiment of the invention, the height h3 scope of described first groove 341 is 10 ~ 30nm, and width d3 scope is 50 ~ 100nm.
In conjunction with reference to figure 5 and Figure 11, perform step S309 and S311, form the second mask layer 350 covering described first trenched side-wall, and along described first trench dry etch semiconductor substrates, form the second groove 342.
Described second mask layer 350, for protecting the sidewall of described first groove 341 in subsequent etching processes, therefore, only needs on the sidewall of described first groove 341, form described second mask layer 350.
Described second groove 342 is for the Part II of follow-up formation groove; in the technique forming Part II; described second mask layer 350 can protect the part semiconductor substrate that covers by its; namely the pattern of described first groove 341 is protected not change; the semiconductor substrate materials needing to remove for forming described Part II is reduced; namely decrease the time of etching, thus prevent the too small problem even occurring wedge angle of bottom portion of groove floor space that may cause because etch period is long.
For making simple process, workable, in one embodiment of the invention, form structure as shown in figure 11 in the following ways.In conjunction with reference Figure 10 and Figure 11, first adopt and cover deposition (blanketdeposition) technique, formed and cover described first mask layer 320 and the described bottom surface of the first groove 341 and the second mask layer of sidewall, then dry etching is utilized, remove the second mask layer being positioned at described first groove 341 bottom surface, and along described first groove 341 dry etching Semiconductor substrate, form the second groove 342, described second groove 342 is connected with described first groove 341.In this embodiment, the second etching technics removal is utilized to be positioned at the second mask layer of the first trench bottom surfaces and to form the second groove 342, described second etching technics can be plasma etching industrial, by arranging bias voltage, control etching gas and arrive the region of specifying, thus remove part second mask layer that is positioned on described first groove 341 bottom surface and retain part second mask layer be positioned on described first groove 341 sidewall, and along the first trench dry etch semiconductor substrates, thus form described second groove 342.In one embodiment of the invention, plasma process is utilized to remove the second mask layer being positioned at described first groove 341 bottom surface, and form described second groove 342, the parameter of described plasma etching industrial specifically comprises: when described second mask layer 350 is silica, etching pressure 1 ~ 200mTorr, CF
4flow 2 ~ 200sccm, O
2flow 2 ~ 20sccm, He flow 10 ~ 500sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.Or in another embodiment of the present invention, when described second mask layer 350 is silicon nitrides, the parameter of described plasma etching industrial comprises: etching pressure 1 ~ 200mTorr, CF
4or CHF
3flow 2 ~ 200sccm, O
2flow 2 ~ 500sccm, He flow 10 ~ 1000sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
The material of described second mask layer 350 can be silica or silicon nitride, and the scope of thickness is 10 dust to 200 dusts.
In one particular embodiment of the present invention, described second mask layer 350 is different with the material of described first mask layer 320.Not only when described second mask layer 350 of follow-up removal, by controlling the parameter of etching technics, can more easily realize removing described second mask layer 350 but also retain described first mask layer 320.Described first mask layer 320 can protect described grid structure 310 in the techniques such as follow-up ion doping.Further; as mentioned above; in one embodiment of the invention; described grid structure 310 is formed with described protective layer; correspondingly; described protective layer, described first mask layer 320 and described second mask layer 350 can form the stacked structure of oxidenitride oxide (ONO) or Nitride-Oxide-Nitride thing (NON), to protect described grid structure 310 better.
In conjunction with reference to figure 5 and Figure 12, perform step S313, with described second mask layer 350 for mask, the bottom surface of the second groove 342 described in wet etching and sidewall, described second groove is extended below described grid structure and extends to described Semiconductor substrate lower surface, described first groove and the second groove after extending are as groove 343.
Described groove 343 comprises Part I 3431 and Part II 3432, described Part I 3431 is connected with the upper surface of described Semiconductor substrate 300, and described Part II 3432 and described Part I 3431 be through to be connected and to extend to the below of described grid structure 310.
Because described second mask layer 350 protects the part semiconductor substrate be entirely covered, the profile of described first groove does not change, and this part constitutes the Part I 3431 of described groove 343; And the profile of described second groove there occurs change, to extend and lower surface to Semiconductor substrate extends below grid structure, the second groove after extension constitutes the Part II 3432 (going out with dotted line frame in fig. 12) of described groove 343.
Described Part II 3432 can have various shape, and such as, the longitudinal section (section namely in diagram) of described Part II 3432 has to the outstanding wedge angle of the Semiconductor substrate below described grid structure 310.The longitudinal section of described Part II 3432 can also have such as circular arc or other erose profiles, as long as extend to the below of described grid structure 310.Inventor finds, when the longitudinal section of described Part II 3432 has the wedge angle outstanding to the Semiconductor substrate below described grid structure 310, the performance of described transistor is better.
In one embodiment of the invention, utilize wet-etching technology to etch bottom surface and the sidewall of described second groove 342, the etching agent that described wet-etching technology adopts comprises: potassium hydroxide (KOH), ammoniacal liquor (NH
4oH) or tetramethyl aqua ammonia (TMAH) carry out wet method quarter.In one particular embodiment of the present invention, utilize TMAH to carry out wet etching, temperature is 15 ~ 70 degrees Celsius, and the time is 20 ~ 500 seconds.
In an embodiment of the present invention, the height h4 scope of the second groove after extension and described Part II 3432 is 2 ~ 100nm, and width d4 scope is 5 ~ 500nm.
In a particular embodiment of the present invention, the transistor formed for 45 nanometer technology nodes, in one embodiment of the invention, the height h4 scope of described Part II 3432 is 30 ~ 100nm, and width d4 scope is 50 ~ 100nm.
In conjunction with reference to figure 5 and Figure 13, perform step S315, remove described second mask layer 350.
The second mask layer remained in described groove can affect the quality of the stressor layers of follow-up formation, therefore, needs to be removed.
In one embodiment of the invention, described second mask layer 350 is different with the material of described first mask layer 320, such as, be respectively the one in silica and silicon nitride, therefore, remove described second mask layer 350 and the technique retaining described first mask layer 320 has larger process choice window, that is, can be accomplished in several ways.Such as, removing silica and retained nitrogen SiClx can realize by adopting hf etching technique, and removes silicon nitride and retain silica and can realize by adopting phosphoric acid etching technics.Retain described first mask layer 320, described grid structure 310 can be protected in the techniques such as follow-up ion doping.In another embodiment of the present invention; due to described grid structure 310 being coated with described protective layer; alternatively; described protective layer, described first mask layer 320 and described second mask layer 350 form ONO or NON structure; therefore; also both can remove described second mask layer 350, remove again described first mask layer 320.
In conjunction with reference to figure 5 with reference to Figure 14, perform step S317, form the source electrode of transistor at the groove being arranged in described grid structure side, form the drain electrode of transistor at the groove being arranged in described grid structure opposite side.In the specific embodiment of the invention, source electrode and drain electrode are served as by the stressor layers 360 of doping, that is, be arranged in the source electrode of stressor layers 360 as transistor of the doping of the groove of described grid structure side, be arranged in the stressor layers 360 of the doping of the groove of described grid structure opposite side as drain electrode.
The stressor layers 360 of described doping can be formed by epitaxial growth technology.The material of the stressor layers 360 of described doping is selected according to the type of device, and such as, described transistor is PMOS transistor, then the material of the stressor layers 360 of described doping is the SiGe that can produce compression to channel region; If described transistor is nmos pass transistor, then the material of the stressor layers 360 of described doping is the SiC that can produce tension stress to channel region.After being filled with stress material, ion doping technique is carried out to it, thus obtain the stressor layers 360 of described doping.Ion doping technique is well known to those skilled in the art, and does not repeat them here.
So far, the transistor that the embodiment of the present invention provides is defined.
To sum up, embodiments of the invention have the following advantages:
First, in the transistor that embodiments of the invention provide, described groove comprises Part I and Part II, and described Part I is connected with the upper surface of described Semiconductor substrate, and described Part II and described Part I be through to be connected and to extend to the below of described grid structure.And the groove of prior art only comprises the structure that is similar to described Part I or only comprises the structure being similar to described Part II.Therefore, compared with prior art, the source electrode formed in described groove and drain electrode are both near channel region, there is again larger volume (volume of increase corresponds to the volume of described Part I), when source electrode and drain electrode are served as by the stressor layers of adulterating, more significantly effect of stress can be produced to channel region, improve the mobility of charge carrier further.
Further, according to the formation method of the transistor that embodiments of the invention provide, in the process forming described groove, first form the first groove, the Part I of described first groove respective slot, i.e. the part of compared with prior art volume increase; Then, the sidewall and bottom surface of described first groove form the second mask layer; Then, remove the second mask layer of the first channel bottom, and remove Semiconductor substrate along the first groove, form the second groove; Then with remaining second mask layer for mask, the bottom surface of wet etching second groove and sidewall, second groove is extended to the lower surface of Semiconductor substrate, and extend to the below of grid structure, described first groove and the second groove after extending form groove, the Part II of the second groove respective slot after extension.Because the sidewall of described first groove is covered by the second mask layer, in wet-etching technology, the pattern of described first groove does not change, thus make this wet-etching technology only extend described second groove, namely, the semiconductor substrate materials needing in this step to remove is reduced, avoids the too small situation even occurring wedge angle of the bottom portion of groove area caused because etch period is long, improve the performance of device.
Further, in the specific embodiment of the invention, described first mask layer is different with the material of described second mask layer.Not only therefore, by controlling the parameter of etching technics, can more conveniently realize removing described second mask layer but also retain described first mask layer.Described first mask layer can protect described grid structure in the described stressor layers of the follow-up formation carried out and ion doping technique, makes the performance of the final transistor formed better.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a formation method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form grid structure on the semiconductor substrate, described grid structure comprises gate electrode and is positioned at the side wall of described gate electrode both sides;
Described Semiconductor substrate and described grid structure are formed first mask layer with opening;
With described first mask layer for mask, remove part Semiconductor substrate along opening dry etching, form the first groove in grid structure both sides, the altitude range of described first groove is 2 ~ 40nm;
Form the second mask layer covering described first trenched side-wall;
Along the first trench dry etch semiconductor substrates, form the second groove;
With described second mask layer for mask, the bottom surface of wet etching second groove and sidewall, described second groove is extended below described grid structure and extends to described Semiconductor substrate lower surface, the second groove after described extension extends to the below of described grid structure, and having to the outstanding wedge angle of the Semiconductor substrate below described grid structure, described first groove and the second groove after extending are as groove;
Remove described second mask layer; And
In described groove, form the stressor layers of doping, the stressor layers being positioned at the doping of described grid structure side groove, as source electrode, is positioned at the stressor layers of the doping of opposite side groove as drain electrode.
2. the formation method of transistor as claimed in claim 1, is characterized in that, formation covers described second mask layer of described first trenched side-wall and the step of described second groove specifically comprises:
Formed and cover described substrate, described grid structure and the bottom surface of described first groove and the second mask layer of sidewall; And
Utilize dry etching, remove the second mask layer being positioned at described first trench bottom surfaces, and along the first trench dry etch semiconductor substrates, form the second groove.
3. the formation method of transistor as claimed in claim 1, it is characterized in that, the dry etch process parameter forming described first groove comprises: etching pressure 10 ~ 200mTorr, HBr flow 100 ~ 1000sccm, O
2flow 2 ~ 20sccm, He flow 100 ~ 1000sccm, Cl
2flow 2 ~ 200sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
4. the formation method of transistor as claimed in claim 1, it is characterized in that, the dry etch process forming described second groove is plasma etching industrial.
5. the formation method of transistor as claimed in claim 4, it is characterized in that, when described second mask layer is silica, the parameter of described plasma etching industrial comprises: etching pressure 1 ~ 200mTorr, CF
4flow 2 ~ 200sccm, O
2flow 2 ~ 20sccm, He flow 10 ~ 500sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time;
When described second mask layer is silicon nitride, the parameter of described plasma etching industrial comprises: etching pressure 1 ~ 200mTorr, CF
4or CHF
3flow 2 ~ 200sccm, O
2flow 2 ~ 500sccm, He flow 10 ~ 1000sccm, bias voltage 50 ~ 400V, 5 ~ 60 seconds time.
6. the formation method of transistor as claimed in claim 1, is characterized in that, the etching agent that described wet-etching technology adopts comprises: potassium hydroxide, ammoniacal liquor or tetramethyl aqua ammonia.
7. the formation method of transistor as claimed in claim 6, is characterized in that, the etching agent that described wet-etching technology adopts is tetramethyl aqua ammonia, temperature 15 ~ 70 degrees Celsius, 20 ~ 500 seconds time.
8. the formation method of transistor as claimed in claim 1, it is characterized in that, described first mask layer is different with the material of described second mask layer.
9. the formation method of transistor as claimed in claim 8, it is characterized in that, the material of described first mask layer and described second mask layer is respectively the one in silica and silicon nitride.
10. the formation method of transistor as claimed in claim 1, it is characterized in that, the thickness range of described first mask layer and described second mask layer is 10 dust to 200 dusts.
The formation method of 11. transistors as claimed in claim 2; it is characterized in that; before forming described first mask layer; comprise further being formed and cover the upper surface of described grid structure and the protective layer of sidewall, described protective layer, described first mask layer and described second mask layer form NON structure or ONO structure.
The formation method of 12. transistors as claimed in claim 1, it is characterized in that, the altitude range of the second groove after extension is 2 ~ 100nm.
The formation method of 13. transistors as claimed in claim 1, it is characterized in that, the altitude range of described first groove is 10 ~ 30nm, and the altitude range of the second groove after extension is 30 ~ 100nm.
The formation method of 14. transistors as claimed in claim 1, is characterized in that, when described transistor is PMOS transistor, the material of the stressor layers of described doping is SiGe.
The formation method of 15. transistors as claimed in claim 1, is characterized in that, when described transistor is nmos pass transistor, the material of the stressor layers of described doping is SiC.
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| CN107910259B (en) * | 2017-11-08 | 2021-03-12 | 上海华力微电子有限公司 | Method for preparing sigma groove |
| CN110957220B (en) * | 2018-09-27 | 2023-04-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN1675778A (en) * | 2002-08-12 | 2005-09-28 | 艾康技术公司 | Insulated gate field effect transistor having passivated Schottky barriers to the channel |
| CN101154579A (en) * | 2006-09-28 | 2008-04-02 | 海力士半导体有限公司 | Method for fabricating semiconductor device including recess gate |
| CN101872725A (en) * | 2009-04-23 | 2010-10-27 | 中国台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor structure and semiconductor element |
| CN102931232A (en) * | 2011-08-08 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal Oxide Semiconductor) transistor and forming method thereof |
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| US7951657B2 (en) * | 2009-05-21 | 2011-05-31 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
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| CN1675778A (en) * | 2002-08-12 | 2005-09-28 | 艾康技术公司 | Insulated gate field effect transistor having passivated Schottky barriers to the channel |
| CN101154579A (en) * | 2006-09-28 | 2008-04-02 | 海力士半导体有限公司 | Method for fabricating semiconductor device including recess gate |
| CN101872725A (en) * | 2009-04-23 | 2010-10-27 | 中国台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor structure and semiconductor element |
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