CN103367230A - Manufacturing method for structure of extremely thin silicon on insulator and manufacturing method for semiconductor device - Google Patents
Manufacturing method for structure of extremely thin silicon on insulator and manufacturing method for semiconductor device Download PDFInfo
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Abstract
Disclosed are a manufacturing method for a structure of extremely thin silicon on an insulator (ETSOI) and a manufacturing method for a semiconductor device. The manufacturing method for the semiconductor device includes: providing silicon on insulator (SOI); forming a hard-mask layer on a top-silicon layer and carrying out a patterning processing on the hard-mask layer; and measuring real thicknesses of exposed areas of the top-silicon layer; injecting doping ions into the exposed areas of the top-silicon layer with an injection quantity related to corresponding real thicknesses of the injected areas; carrying out an etching processing, and removing part of the exposed areas of the top-silicon layer and forming trenches; forming side walls on flanks of the trenches and forming gate structures on areas defined by the flanks; carrying out a planarization processing so that upper surfaces of the gate structures are flush with an upper surface of the hard-mask layer; removing the hard-mask layer; and injecting ions into the exposed areas of the top-silicon layer and forming elevated source/drain areas. The manufacturing method for the structure of the extremely thin SOI and the manufacturing method for the semiconductor device enable the thicknesses and uniformity of the areas of the top-silicon layer on the extremely thin SOI structure to be controlled precisely so that damages on the top-silicon layer are prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular a kind of manufacture method of ultra-thin silicon-on-insulator and comprise the manufacture method of the semiconductor device of described ultra-thin silicon-on-insulator.
Background technology
Along with the development of semiconductor technology, the integrated level of integrated circuit is more and more higher, and (CD) is more and more less for the characteristic size of device.When the feature size downsizing of device to deep-submicron (0.25 micron hereinafter referred to as deep-submicron), the leakage current of device increases, drain-induced barrier reduces (DIBL, Drain induction barrier lower) effect and short-channel effect (SCE) etc. are more and more obvious, become the subject matter that the needs of device dimensions shrink overcome.
FDSOI (Fully Depleted Silicon On Insulator with the raceway groove that undopes, full depleted silicon on insulator) semiconductor device (hereinafter to be referred as the FD device) of structure can overcome the variety of issue that device dimensions shrink is brought, its concrete advantage is: 1) owing to having super shallow junction, therefore the FD device can suppress leakage current, control SCE effect; 2) eliminated the random fluctuation of mixing owing to raceway groove undopes, so the mutability of FD device is very low; 3) isolate fully with buried oxide layer and body substrate owing to the FD device, so the error rate of FD device is very low; 4) because thick insulator (for example buried oxide layer in the FDSOI) is normally docked in the source of FD device/leakage, so the junction capacitance of FD device is very low.
Developed multiple FD device architecture in the prior art, such as FinFET (FinField-effecttransistor, fin formula field-effect transistor), 3 grid structures, nano wire and ETSOI (Extremely Thin Silicon On Insulator, silicon on the ultrathin insulating body).Although every kind of device architecture has himself special benefits and challenge, ETSOI is noticeable especially because of its planar structure, and it makes ETSOI and main flow planar CMOS manufacture process fully compatible.Be different with fin number quantized FinFET from device widths, ETSOI can have the width of any requirement.In addition, ETSOI exhausts fully, does not have floater effect.As a result, in fact the ETSOI circuit can be similar to conventional body silicon circuit and design like that, therefore can realize the seamless design migration from the body silicon technology to ETSOI.At last, when adopting ultra-thin buried oxide layer (UTBOX) with ETSOI, additional device adjustment and power management can be realized with adding dopant and/or substrate place reverse bias.
More technical schemes about ultra-thin SOI can be the U.S. Patent application of US20090603737 referring to application number.
Fig. 1 to Fig. 4 shows the schematic diagram of available technology adopting smart-cut (smart-cut) fabrication techniques soi structure (comprising the ETSOI structure).
With reference to shown in Figure 1, the first wafer 10 of monocrystalline silicon is provided, under the environment of room temperature, make 10 thermal oxidations of the first wafer, thereby form silicon oxide layer 11 on the surface of the first wafer 10.
With reference to shown in Figure 2, in the first wafer 10, inject doses hydrogen ion H+.
With reference to shown in Figure 3, the second wafer 12 is provided, clean the first wafer 10 and the second wafer 12, and two wafers are carried out low-temperature bonding.
With reference to shown in Figure 4, carrying out smart peeling processes, in the situation that heating, hydrogen ion in the first wafer 10 can form bubble, so that the first wafer 10 is peeled off at hydrogen atom distribution of peaks place, reach the effect of attenuate the first wafer 10, and carry out polishing and flash annealing processing, thereby the second wafer 12, remaining silicon oxide layer 11 and the first wafer 10 residual monocrystalline silicon consist of soi structure together.When the residual monocrystalline silicon of the first wafer 10 was thinner, then the second wafer 12, remaining silicon oxide layer 11 and the first wafer 10 residual skim monocrystalline silicon consisted of the ETSOI structure together.
But the thickness of the monocrystalline silicon 10 of the superiors is not easy accurate control in the soi structure that the employing said method obtains, and it is in uneven thickness.Therefore, thickness and uniformity how accurately to control the top silicon layer in the ETSOI structure just become those skilled in the art's problem demanding prompt solution.
Fig. 5 to Fig. 7 shows the schematic diagram of making the semiconductor device that comprises the ETSOI structure in the prior art.
With reference to shown in Figure 5, the ETSOI structure is provided, described ETSOI structure comprises from top to bottom successively: top silicon layer 20, insulating barrier 21 and substrate 22.
With reference to shown in Figure 6, form gate oxide 23 and grid 24 at top silicon layer 20, and form side wall 25 in the side of gate oxide 23 and grid 24.
With reference to shown in Figure 7, carry out selective epitaxial growth, form the source electrode 26 of raising and the drain electrode 27 of raising at top silicon layer 20 upper surfaces.
Follow-uply also need to carry out ion doping and annealing in process etc.
The performance of the above-mentioned semiconductor device that comprises the ETSOI structure is relevant with the thickness of top silicon layer 20, and the thickness of top silicon layer 20 is generally less than 20nm.Because the top silicon layer 20 of ETSOI structure is in uneven thickness and uncontrollable in the prior art, thereby affected the performance of semiconductor device.
Even top silicon layer 20 is evenly controlled in the semiconductor device, but the etching technics when forming side wall 25 probably can etch away all or part of top silicon layer 20, thereby can't be at the upper epitaxially grown silicon of insulating barrier 21 (being silica) with the formation source electrode 26 of raising and the drain electrode 27 of raising.Therefore, how in comprising the process of semiconductor device of ETSOI structure, formation avoids the infringement of its top silicon layer is also become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of ultra-thin silicon-on-insulator and comprises the manufacture method of the semiconductor device of described ultra-thin silicon-on-insulator, can accurately control thickness and the uniformity of the top silicon layer in the ETSOI structure, and can avoid the top silicon layer to suffer damage.
For addressing the above problem, the invention provides a kind of manufacture method of ultra-thin silicon-on-insulator, comprising:
Silicon-on-insulator is provided, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Described top silicon layer upper surface is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone;
Dopant implant ion in the silicon layer of described top, the implantation dosage of described doping ion is relevant with described each regional corresponding actual (real) thickness;
Carry out etching processing, remove part top silicon layer, form ultra-thin SOI.
Alternatively, the manufacture method of described ultra-thin silicon-on-insulator also comprises: after removing part top silicon layer, remaining top silicon layer is carried out planarization.
Alternatively, the manufacture method of described ultra-thin silicon-on-insulator also comprises: after the dopant implant ion, carry out annealing in process.
Alternatively, the temperature range of described annealing in process comprises: 900 ℃～1300 ℃.
Alternatively, described annealing in process is spike annealing (Spike Anneal) or millisecond laser annealing (Millisecond Anneal).
Alternatively, the thickness range of described top silicon layer comprises before the etching processing: 30nm～80nm; Remaining described top silicon layer thickness scope comprises after the etching processing: 8nm～20nm.
Alternatively, described etching processing comprises: dry etching; Or the combination of dry etching and wet etching.
Alternatively, described doping ion comprises: P or/and As, Ge or/and Si and C; Perhaps, P or/and As and Ge or/and Si.
Alternatively, the implantation dosage scope of described doping ion comprises: 1E
14/ cm
2～1E
16/ cm
2
Alternatively, the Implantation Energy scope of described doping ion comprises: 1KeV～100KeV.
Alternatively, actual (real) thickness corresponding to each zone of described measurement comprises: measure the actual (real) thickness of any point position in each zone, with the actual (real) thickness of this position actual (real) thickness as the corresponding region.
In order to address the above problem, the present invention also provides a kind of manufacture method of semiconductor device, comprising:
Silicon-on-insulator is provided, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Silicon layer forms hard mask layer on described top, and described hard mask layer is carried out patterned process, and the top silicon layer upper surface that will expose is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone;
Dopant implant ion in the described top silicon layer that exposes, the implantation dosage of described doping ion is relevant with described each regional corresponding actual (real) thickness;
Carry out etching processing, remove the top silicon layer that part exposes, form groove;
Sidewall at described groove forms side wall, and forms grid structure in the zone that described side wall surrounds;
Carry out planarization, make the upper surface flush of upper surface and the described hard mask layer of described grid structure;
Remove described hard mask layer;
In the described top silicon layer that exposes, carry out Implantation, form the source/drain region of raising.
Alternatively, the thickness range of described hard mask layer comprises: 10nm～100nm.
Alternatively, the material of described hard mask layer comprises: a kind of or combination in any in silicon nitride, carborundum or the silica.
Alternatively, the material of described side wall comprises successively: silica, silicon nitride and silica; Perhaps silica and silicon nitride.
Alternatively, the silica in the described side wall adopts thermal oxidation technology or chemical vapor deposition method to form.
Alternatively, the manufacture method of described semiconductor device also comprises: after the dopant implant ion, carry out annealing in process.
Alternatively, the temperature range of described annealing in process comprises: 900 ℃～1300 ℃.
Alternatively, described annealing in process is spike annealing or millisecond laser annealing.
Alternatively, the thickness range of described top silicon layer comprises before the etching processing: 30nm～80nm; Remaining described top silicon layer thickness scope comprises after the etching processing: 8nm～20nm.
Alternatively, described etching processing comprises: dry etching; Or the combination of dry etching and wet etching.
Alternatively, described doping ion comprises: P or/and As, Ge or/and Si and C; Perhaps, P or/and As and Ge or/and Si.
Alternatively, the implantation dosage scope of described doping ion comprises: 1E
14/ cm
2～1E
16/ cm
2
Alternatively, the Implantation Energy scope of described doping ion comprises: 1KeV～100KeV.
Alternatively, actual (real) thickness corresponding to each zone of described measurement comprises: measure the actual (real) thickness of any point position in each zone, with the actual (real) thickness of this position actual (real) thickness as the corresponding region.
Alternatively, corresponding tube core in described each zone.
Alternatively, before forming hard mask layer, the top silicon layer upper surface that exposes is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone.
Alternatively, after forming hard mask layer and before the dopant implant ion, the top silicon layer upper surface that exposes is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone.
Compared with prior art, the present invention has the following advantages:
1) manufacture method of ultra-thin silicon-on-insulator provided by the invention, on the basis of conventional silicon-on-insulator, obtain each regional actual (real) thickness of its top silicon layer, in the silicon layer of top, carry out the doping Implantation of various dose according to the actual (real) thickness of top silicon layer, the top silicon layer is thicker, the doping ion dose that injects is more, then carry out etching processing, thereby utilize the proportional relation of etch rate and doping ion dose, the place that the doping ion dose is more, etch rate is larger, namely the speed of thicker local etching is larger, finally under the prerequisite of accurate controlled doping ion dose, can accurately control thickness and the uniformity of remaining top silicon layer, obtain the ETSOI structure.
2) manufacture method of semiconductor device provided by the invention on the basis of conventional silicon-on-insulator, forms the hard mask layer of patterning; And then according to each regional actual (real) thickness in the top silicon layer that exposes, carry out the doping Implantation of various dose, and carry out etching processing, remove the top silicon layer that part exposes, form groove; In groove, form successively side wall and grid structure; After removing hard mask, in the top silicon layer that exposes, carry out Implantation, form the source/drain region of raising.Thereby on the basis that obtains the controlled ETSOI structure of even thickness, the source/drain region of raising directly forms by Implantation, has saved epitaxially grown step, and top layer silicon corresponding to the source/drain region of raising is subjected to the protection of hard mask layer, can not suffer damage.
Description of drawings
Fig. 1 to Fig. 4 is the schematic diagram that prior art is made the ETSOI structure;
Fig. 5 to Fig. 7 is the schematic diagram that prior art is made the semiconductor device that comprises the ETSOI structure;
Fig. 8 is the schematic flow sheet of the manufacture method of ETSOI structure in the embodiment of the present invention;
Fig. 9 to Figure 11 is the schematic diagram of the manufacture method of ETSOI structure in the embodiment of the invention;
Figure 12 be the doping ion is arranged in the embodiment of the invention and the two kinds of situations of ion of not mixing under concern schematic diagram between etch rate and the radio-frequency power;
Figure 13 is doping content and inject the schematic diagram that concerns between the degree of depth in the doping different ions situation in the embodiment of the invention;
Figure 14 mixes simultaneously the ideally doping content of Si ion, C ion and P ion and injects the schematic diagram that concerns between the degree of depth;
Figure 15 is the schematic flow sheet of the manufacture method of semiconductor device in the embodiment of the present invention;
Figure 16 to Figure 24 is the schematic diagram of the manufacture method of semiconductor device in the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, prior art is in the process of making ETSOI, and the thickness of its top layer silicon is not easy accurate control, and it is in uneven thickness; When making comprises the semiconductor device of ETSOI structure, easily damage top layer silicon, affect the performance of semiconductor device.
For defects, the invention provides a kind of manufacture method and the manufacture method that comprises the semiconductor device of ultra-thin silicon-on-insulator of ultra-thin silicon-on-insulator.
When making ultra-thin silicon-on-insulator, because the top layer silicon of conventional silicon-on-insulator is in uneven thickness, for so that remaining top silicon layer thickness is evenly controlled, adopt the technique of etching after mixing first, inject more doping ion in the place that the top silicon layer is thicker, the local etch rate that the doping ion is more is larger, the local etch rate that namely the top silicon layer is thicker is larger, thereby the dosage by the controlled doping ion just can accurately be controlled the thickness that the top silicon layer is etched, and then can guarantee that the even thickness of remaining top silicon layer is controlled.
When making comprises the semiconductor device of ultra-thin silicon-on-insulator, top layer silicon in conventional silicon-on-insulator forms the hard mask layer corresponding with gate pattern first, and then the top silicon layer thickness that adopts said method to expose is decreased to corresponding with ultra-thin SOI, and then in groove, form side wall and grid structure, and removal hard mask layer, this moment, the dopant implant ion just formed the source/drain region of raising in the top silicon layer that exposes, source/the drain region of raising can anyly not damaged, and has finally improved the performance of semiconductor device.
Be elaborated below in conjunction with accompanying drawing.
With reference to shown in Figure 8, the present embodiment provides a kind of manufacture method of ultra-thin silicon-on-insulator, comprising:
Step S1 provides silicon-on-insulator, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Step S2 is divided into a plurality of zones with described top silicon layer upper surface, measures actual (real) thickness corresponding to each zone;
Step S3, dopant implant ion in the silicon layer of described top, the actual (real) thickness that the implantation dosage of described doping ion and injection zone are corresponding is relevant;
Step S4 carries out etching processing, removes part top silicon layer, forms ultra-thin SOI.
The present embodiment carries out the doping Implantation of various dose in the silicon layer of top according to the actual (real) thickness of top silicon layer, the top silicon layer is thicker, the doping ion dose that injects is more, then carry out etching processing, thereby utilize the proportional relation of etch rate and doping ion dose, the place that the doping ion dose is more, etch rate is larger, namely the speed of thicker local etching is larger, finally under the prerequisite of accurate controlled doping ion dose, can accurately control thickness and the uniformity of remaining top silicon layer, obtain the ETSOI structure.
At first execution in step S1 with reference to shown in Figure 9, provides soi structure, and described soi structure comprises: substrate 110, insulating barrier 120 and top silicon layer 130.
The manufacture method of described soi structure is same as the prior art, specifically can adopt the smart-cut technology in the background technology to form, and can also adopt other modes to form, and it does not limit protection scope of the present invention.
Substrate described in the present embodiment 110 can be the Semiconductor substrate of any materials, as: polysilicon.The material of described insulating barrier 120 can be silica.The material of described top silicon layer 130 can be monocrystalline silicon.Can also comprise isolation structure in the described top silicon layer 130, as: sti structure (fleet plough groove isolation structure).
The thickness range of top silicon layer 130 can comprise in the described soi structure: 30nm～80nm, as: 30nm, 50nm or 80nm.
The present embodiment need to attenuate top silicon layer 130, make its thickness be positioned at the scope of 8nm～20nm, thereby soi structure shown in Figure 9 is converted to ultra-thin silicon-on-insulator.
Need to prove, prior art when making soi structure, its top silicon layer 130 in uneven thickness, some positions are thin, some positions are thick.
For the situation in uneven thickness of soi structure top silicon layer 130, then execution in step S2 is divided into a plurality of zones with described top silicon layer 130 upper surfaces, measures actual (real) thickness corresponding to each zone.
Wherein, the technology of measuring top silicon layer 130 thickness is known for those skilled in the art, as: adopt any measured film thickness instrument etc., do not repeat them here.
Particularly, the present embodiment can be in the selected identical zone of a plurality of areas of the upper surface of top silicon layer 130, and the thickness that any point in each zone is corresponding is as the actual (real) thickness of this zone correspondence.Described zone can be irregularly shaped for circular, square, polygon or other.The subregional thickness in the present embodiment middle part is identical, and the thickness of subregion is not identical.In other embodiments of the invention, the area of each zonule can be different.Need to prove, the present embodiment can also be measured a plurality of corresponding thickness in each zonule, with the average of a plurality of thickness as this regional actual (real) thickness.
Then execution in step S3, with reference to shown in Figure 10, dopant implant ion in described top silicon layer 130, the actual (real) thickness that the implantation dosage of described doping ion and injection zone are corresponding is relevant.
The implantation dosage of doping ion is greater than the implantation dosage of doping ion in the less zonule of thickness in the zonule that thickness is larger in the present embodiment.
The implantation dosage scope of described doping ion can comprise: 1E
14/ cm
2～1E
16/ cm
2, as: 1E
14/ cm
2, 5E
14/ cm
2, 1E
15/ cm
2, 7E
15/ cm
2Or 1E
16/ cm
2Particularly, the actual (real) thickness that the implantation dosage of described doping ion can be corresponding with the region, injection phase is proportional.As: the doping Ion Phase with condition under, actual (real) thickness is that the implantation dosage of doping ion is 5E in the zonule of M
14/ cm
2, then actual (real) thickness is that the implantation dosage of doping ion is 7.5E in the zonule of 1.5M
14/ cm
2
Described doping ion can comprise: P or/and As, Ge or/and Si and C.As: P, Ge and C; As, Si and C; P, Si and C; As, Ge and C; P, As, Ge, Si and C; P, As, Ge and C; P, As, Si and C; P, Ge, Si and C; As, Ge, Si and C; P and Ge; As and Si; P and Si; As and Ge; P, As, Ge and Si; P, As and Ge; P, As and Si; P, Ge and Si; As, Ge and Si.The ion of doping described in the present embodiment is Si, P and C.
Need to prove; the present embodiment can inject a plurality of described doping ions (namely injecting simultaneously Si, P and C) simultaneously; can divide yet and successively inject a plurality of described doping ions (as: injecting successively Si, P and C), it does not limit protection scope of the present invention.
The Implantation Energy scope of described doping ion can comprise: 1KeV～100KeV, as: 1KeV, 10KeV, 20KeV, 50KeV, 75KeV or 100KeV.Difference of should the zone behind the Implantation Energy of the described doping ion actual (real) thickness corresponding with kind, implantation dosage, the injection zone (zone of aforementioned detect thickness) of doping ion and the attenuate corresponding thickness etc. all has relation.
The present embodiment can also carry out annealing in process after the dopant implant ion, to eliminate lattice defect, activate the doping ion, improves the performance of soi structure.
The temperature range of described annealing in process can comprise: 900 ℃～1300 ℃, as: 900 ℃, 1000 ℃, 1150 ℃, 1240 ℃ or 1300 ℃.Particularly, can adopt spike annealing or millisecond laser annealing in the present embodiment.
Then execution in step S4 with reference to shown in Figure 11, carries out etching processing, removes part top silicon layer, forms ultra-thin silicon-on-insulator, and remaining top silicon layer 130a is as the top silicon layer of ultra-thin SOI.
Described etching processing can only be dry etching, also can be the combination of dry etching and wet etching, and it does not repeat them here knowing for those skilled in the art.Just can obtain the ultra-thin silicon-on-insulator of even thickness by etching processing.
In conjunction with reference to shown in Figure 12, the etch rate (referring to B curve in Figure 12) of the etch rate when the doping ion is arranged (referring to the A curve among Figure 12) when not mixing ion improves greatly.Since injected the doping ion, can be faster to the etch rate of top silicon layer 130, and the thickness of more easily control residue top silicon layer.
Shown in Figure 13 in conjunction with reference, in top silicon layer 130, only mix P ion (referring to the D curve), only mix As ion (referring to the E curve), simultaneously mix As ion and P ion (referring to C curve), mix in these four kinds of situations of Si ion, C ion and P ion (referring to the F curve) simultaneously, its injection depth disparity in top layer silicon 130 is very large.Especially at the same time mix in the situation of Si ion, C ion and P ion, have an Implantation sudden change layer this moment, ideal situation namely mixes Implantation behind certain depth referring to shown in Figure 14, and the injection degree of depth of doping ion no longer continues to increase.Thereby by etch period reasonably is set, can guarantee in etching process, can stop at last Implantation sudden change layer to the etching of top silicon layer 130, guarantee that finally the even thickness of remaining top silicon layer 130a is controlled.
The thickness range of remaining top silicon layer 130a can comprise described in the present embodiment: 8nm～20nm, as: 8nm, 10nm, 14nm, 17nm or 20nm.
The present embodiment can also carry out planarization to remaining top silicon layer 130a, thereby further guarantee its even thickness after removing part top silicon layer.
For top silicon layer among Figure 10 130 situation in uneven thickness, can be to thicker position with higher etch rate, to thinner position with lower etch rate etching, thereby make remaining top silicon layer 130a reach even.
The present embodiment is when making ultra-thin silicon-on-insulator, because the top layer silicon of conventional silicon-on-insulator is in uneven thickness, for so that remaining top silicon layer thickness is evenly controlled, adopt the technique of etching after mixing first, inject more doping ion in the place that the top silicon layer is thicker, the local etch rate that the doping ion is more is larger, the local etch rate that namely the top silicon layer is thicker is larger, thereby the dosage by the controlled doping ion just can accurately be controlled the thickness that the top silicon layer is etched, and then can guarantee that the even thickness of remaining top silicon layer is controlled.
Correspondingly, with reference to shown in Figure 15, the present embodiment also provides a kind of manufacture method of semiconductor device, comprising:
Step S11 provides silicon-on-insulator, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Step S12, silicon layer forms hard mask layer on described top, and described hard mask layer is carried out patterned process;
Step S13 is divided into a plurality of zones with the top silicon layer upper surface that exposes, and measures actual (real) thickness corresponding to each zone;
Step S14, dopant implant ion in the described top silicon layer that exposes, the actual (real) thickness that the implantation dosage of described doping ion and injection zone are corresponding is relevant;
Step S15 carries out etching processing, removes the top silicon layer that part exposes, and forms groove;
Step S16 at the sidewall formation side wall of described groove, and forms grid structure in the zone that described side wall surrounds;
Step S17 carries out planarization, makes the upper surface flush of upper surface and the described hard mask layer of described grid structure;
Step S18 removes described hard mask layer;
Step S19 carries out Implantation in the described top silicon layer that exposes, form the source/drain region of raising.
The present embodiment is on the basis that obtains the controlled ETSOI structure of even thickness, and the source/drain region of raising directly forms by Implantation, has saved epitaxially grown step, and top layer silicon corresponding to the source/drain region of raising is subjected to the protection of hard mask layer, can not suffer damage.
At first execution in step S11 with reference to shown in Figure 16, provides soi structure, and described soi structure comprises: substrate 210, insulating barrier 220 and top silicon layer 230.
The manufacture method of described soi structure is same as the prior art, specifically can adopt the smart-cut technology in the background technology to form, and can also adopt other modes to form, and it does not limit protection scope of the present invention.
Substrate described in the present embodiment 210 can be the Semiconductor substrate of any materials, as: polysilicon.The material of described insulating barrier 220 can be silica.The material of described top silicon layer 230 can be monocrystalline silicon.
Can also comprise isolation structure in the silicon layer of top described in the present embodiment 230, as: STI (fleet plough groove isolation structure).
The thickness range of top silicon layer 230 can comprise in the described soi structure: 30nm～80nm, as: 30nm, 50nm or 80nm.
The present embodiment need to attenuate top silicon layer 230, make its thickness be positioned at the scope of 8nm～20nm, thereby soi structure shown in Figure 17 is converted to ultra-thin silicon-on-insulator.
Need to prove, prior art when making soi structure, its top silicon layer 230 in uneven thickness, some positions are thin, some positions are thick.
Then execution in step S12 with reference to shown in Figure 17, forms hard mask layer 240 at described top silicon layer 230, and described hard mask layer 240 is carried out patterned process.
The opening of the hard mask layer 240 of patterning is corresponding with grid structure in the present embodiment.
Particularly, the thickness range of described hard mask layer 240 can comprise: 10nm～100nm, as: 10nm, 30nm, 50nm, 70nm or 100nm etc.
Particularly, the material of described hard mask layer 240 can comprise: a kind of or combination in any in silicon nitride, carborundum or the silica.
The concrete formation technique of described hard mask layer 240 is known for those skilled in the art, does not repeat them here.
For the present situation in uneven thickness of soi structure top silicon layer 230, then execution in step S13 is divided into a plurality of zones with top silicon layer 230 upper surfaces that expose, and measures actual (real) thickness corresponding to each zone.
Need to prove, both can measure the actual (real) thickness of more than 230 position of silicon layer, top before forming hard mask layer 240, can measure the actual (real) thickness of more than 230 position of top silicon layer yet after forming hard mask layer 240, it does not limit protection scope of the present invention.
Wherein, the technology of measuring top silicon layer 230 thickness is known for those skilled in the art, as: adopt any measured film thickness instrument etc., do not repeat them here.
Preferably, the corresponding tube core (die) in each zone in the present embodiment.
Then execution in step S14, with reference to shown in Figure 180, dopant implant ion in the described top silicon layer 230 that exposes, the actual (real) thickness that the implantation dosage of described doping ion and injection zone (zone of detect thickness) are corresponding is relevant.
The implantation dosage of doping ion is greater than the implantation dosage of doping ion in the less zonule of thickness in the zonule that thickness is larger in the present embodiment.
The implantation dosage scope of described doping ion can comprise: 1E
14/ cm
2～1E
16/ cm
2, as: 1E
14/ cm
2, 5E
14/ cm
2, 1E
15/ cm
2, 7E
15/ cm
2Or 1E
16/ cm
2Particularly, the actual (real) thickness that the implantation dosage of described doping ion can be corresponding with injection zone is proportional.As: the doping Ion Phase with condition under, actual (real) thickness is that the implantation dosage of doping ion is 5E in the zonule of M
14/ cm
2, then actual (real) thickness is that the implantation dosage of doping ion is 7.5E in the zonule of 1.5M
14/ cm
2
Described doping ion can comprise: P or/and As, Ge or/and Si and C.As: P, Ge and C; As, Si and C; P, Si and C; As, Ge and C; P, As, Ge, Si and C; P, As, Ge and C; P, As, Si and C; P, Ge, Si and C; As, Ge, Si and C; P and Ge; As and Si; P and Si; As and Ge; P, As, Ge and Si; P, As and Ge; P, As and Si; P, Ge and Si; As, Ge and Si.The ion of doping described in the present embodiment is Si, P and C.
Need to prove; the present embodiment can inject a plurality of described doping ions (namely injecting simultaneously Si, P and C) simultaneously; can divide yet and successively inject a plurality of described doping ions (as: injecting successively Si, P and C), it does not limit protection scope of the present invention.
The Implantation Energy scope of described doping ion can comprise: 1KeV～100KeV, as: 1KeV, 10KeV, 20KeV, 50KeV, 75KeV or 100KeV.Thickness corresponding to this position etc. all has relation behind the kind of the Implantation Energy of described doping ion and doping ion, implantation dosage, actual (real) thickness that injection zone (zone of detect thickness) is corresponding, the attenuate.
The present embodiment can also carry out annealing in process after the dopant implant ion, to eliminate lattice defect, activate the doping ion, improves the performance of soi structure.
The temperature range of described annealing in process can comprise: 900 ℃～1300 ℃, as: 900 ℃, 1000 ℃, 1150 ℃, 1240 ℃ or 1300 ℃.Particularly, can adopt spike annealing or millisecond laser annealing in the present embodiment.
Then execution in step S15 with reference to shown in Figure 19, carries out etching processing, removes part top silicon layer 230, forms ultra-thin silicon-on-insulator, and remaining top silicon layer 230a is as the top silicon layer of ultra-thin SOI.At this moment, the top silicon layer part of removal has just formed groove 250.
Described etching processing can only be dry etching, also can be the combination of dry etching and wet etching, and it does not repeat them here knowing for those skilled in the art.Just can obtain the ultra-thin silicon-on-insulator of even thickness by etching processing.
With reference to shown in Figure 13, the inventor finds after deliberation: the etch rate of the etch rate when the doping ion is arranged when not mixing ion improves greatly.Since injected the doping ion, can be faster to the etch rate of top silicon layer, and more controlled.
In conjunction with reference to Figure 13 and shown in Figure 14, the inventor also finds: in the situation that select suitable doping ion, when the doping Implantation behind certain depth, the injection degree of depth of doping ion no longer continues to increase.Thereby by rational etch period is set, can guarantee in etching process, can stop at last Implantation sudden change layer to the etching of top silicon layer, guarantee that finally the Thickness Ratio of remaining top silicon layer is more controlled.
The thickness range of remaining top silicon layer 130a can comprise described in the present embodiment: 8nm～20nm, as: 8nm, 10nm, 14nm, 17nm or 20nm.
The present embodiment can also carry out planarization to remaining top silicon layer 230a, thereby further guarantee its even thickness after removing part top silicon layer.
Follow execution in step S16, with reference to shown in Figure 20, at the sidewall formation side wall of described groove 250.
Side wall comprises two membranes described in the present embodiment, comprising: the second tunic 262 that the first tunic 261 that silica forms and silicon nitride form.Wherein, the first tunic 261 (being silicon oxide layer) can adopt thermal oxidation technology or chemical vapor deposition method to form.Owing in the process that forms side wall, can carry out etching technics, thereby can consume part top silicon layer 230a, therefore when the silicon layer 230 of etching top, can make the thickness of remaining top silicon layer 230a be a bit larger tham the thickness of requirement.
Need to prove, in other embodiments of the invention, described side wall can also only comprise that material is the skim of silica or silicon nitride, can also comprise successively that material is the trilamellar membrane of oxide layer, silicon nitride and silica etc., and the present invention is not restricted this.
With reference to shown in Figure 21, in the zone that described side wall surrounds, form grid structure.
The concrete technology that forms grid structure is known for those skilled in the art, does not repeat them here.
Grid structure can comprise successively in the present embodiment: gate dielectric layer 271 and grid 272.In other embodiments of the invention, described grid structure can also only comprise grid.
Then execution in step S17 with reference to shown in Figure 22, carries out planarization, makes the upper surface flush of upper surface and the described hard mask layer 240 of described grid 272.
Particularly, can make by cmp (CMP) technique the upper surface flush of upper surface and the described hard mask layer 240 of described grid 272.
Then execution in step S18 with reference to shown in Figure 23, removes described hard mask layer 240.
The present embodiment can adopt dry etching or wet etching to remove described hard mask layer 240.
Then execution in step S19 with reference to shown in Figure 24, carries out Implantation in the described top silicon layer 230 that exposes, and forms the source region 281 of raising and the drain region 282 of raising.
The technique that forms source/drain region by Implantation is known for those skilled in the art, does not repeat them here.
Follow-uply in the present embodiment can also form source/drain extension region and HALO injection region, and form electric contact structure in the source region 281 of raising and the drain region 282 of raising, all repeat no more at this.
The channel thickness of each tube core is identical in the semiconductor device that employing the present embodiment method forms, and namely the raceway groove of each tube core is consistent, thereby guarantees the consistent of chip performance; And the thickness of each raceway groove is very even, thereby has improved the performance of semiconductor device.
When the present embodiment comprises the semiconductor device of ultra-thin silicon-on-insulator in making, top layer silicon in conventional silicon-on-insulator forms the hard mask layer corresponding with gate pattern first, and then the top silicon layer thickness that adopts said method to expose is decreased to corresponding with ultra-thin SOI, and then in groove, form side wall and grid structure, and removal hard mask layer, this moment, dopant implant ion in the top silicon layer that exposes just formed the source/drain region of raising, can there be any infringement in the source/drain region of raising, has finally improved the performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (28)
1. the manufacture method of a ultra-thin silicon-on-insulator is characterized in that, comprising:
Silicon-on-insulator is provided, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Described top silicon layer upper surface is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone;
Dopant implant ion in the silicon layer of described top, the implantation dosage of described doping ion is relevant with described each regional corresponding actual (real) thickness;
Carry out etching processing, remove part top silicon layer, form ultra-thin SOI.
2. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1 is characterized in that, also comprises: after removing part top silicon layer, remaining top silicon layer is carried out planarization.
3. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1 is characterized in that, also comprises: after the dopant implant ion, carry out annealing in process.
4. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 3 is characterized in that, the temperature range of described annealing in process comprises: 900 ℃～1300 ℃.
5. such as the manufacture method of claim 3 or 4 described ultra-thin silicon-on-insulator, it is characterized in that, described annealing in process is spike annealing or millisecond laser annealing.
6. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1 is characterized in that, the thickness range of described top silicon layer comprises before the etching processing: 30nm～80nm; Remaining described top silicon layer thickness scope comprises after the etching processing: 8nm～20nm.
7. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1 is characterized in that, described etching processing comprises: dry etching; Or the combination of dry etching and wet etching.
8. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1 is characterized in that, described doping ion comprises: P or/and As, Ge or/and Si and C; Perhaps, P or/and As and Ge or/and Si.
9. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 8 is characterized in that, the implantation dosage scope of described doping ion comprises: 1E
14/ cm
2～1E
16/ cm
2
10. such as the manufacture method of claim 1 or 8 described ultra-thin silicon-on-insulator, it is characterized in that, the Implantation Energy scope of described doping ion comprises: 1KeV～100KeV.
11. the manufacture method of ultra-thin silicon-on-insulator as claimed in claim 1, it is characterized in that, actual (real) thickness corresponding to each zone of described measurement comprises: measure the actual (real) thickness of any point position in each zone, with the actual (real) thickness of this position actual (real) thickness as the corresponding region.
12. the manufacture method of a semiconductor device is characterized in that, comprising:
Silicon-on-insulator is provided, and described silicon-on-insulator comprises successively: substrate, insulating barrier and top silicon layer;
Silicon layer forms hard mask layer on described top, and described hard mask layer is carried out patterned process, and the top silicon layer upper surface that will expose is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone;
Dopant implant ion in the described top silicon layer that exposes, the implantation dosage of described doping ion is relevant with described each regional corresponding actual (real) thickness;
Carry out etching processing, remove the top silicon layer that part exposes, form groove;
Sidewall at described groove forms side wall, and forms grid structure in the zone that described side wall surrounds;
Carry out planarization, make the upper surface flush of upper surface and the described hard mask layer of described grid structure;
Remove described hard mask layer;
In the described top silicon layer that exposes, carry out Implantation, form the source/drain region of raising.
13. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the thickness range of described hard mask layer comprises: 10nm～100nm.
14. the manufacture method such as claim 12 or 13 described semiconductor device is characterized in that, the material of described hard mask layer comprises: a kind of or combination in any in silicon nitride, carborundum or the silica.
15. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the material of described side wall comprises successively: silica, silicon nitride and silica; Perhaps silica and silicon nitride.
16. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, the silica in the described side wall adopts thermal oxidation technology or chemical vapor deposition method to form.
17. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, also comprises: after the dopant implant ion, carry out annealing in process.
18. the manufacture method of semiconductor device as claimed in claim 17 is characterized in that, the temperature range of described annealing in process comprises: 900 ℃～1300 ℃.
19. the manufacture method such as claim 17 or 18 described semiconductor device is characterized in that, described annealing in process is spike annealing or millisecond laser annealing.
20. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the thickness range of described top silicon layer comprises before the etching processing: 30nm～80nm; Remaining described top silicon layer thickness scope comprises after the etching processing: 8nm～20nm.
21. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, described etching processing comprises: dry etching; Or the combination of dry etching and wet etching.
22. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, described doping ion comprises: P or/and As, Ge or/and Si and C; Perhaps, P or/and As and Ge or/and Si.
23. the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, the implantation dosage scope of described doping ion comprises: 1E
14/ cm
2～1E
16/ cm
2
24. the manufacture method such as claim 12 or 23 described semiconductor device is characterized in that, the Implantation Energy scope of described doping ion comprises: 1KeV～100KeV.
25. the manufacture method of semiconductor device as claimed in claim 12, it is characterized in that, actual (real) thickness corresponding to each zone of described measurement comprises: measure the actual (real) thickness of any point position in each zone, with the actual (real) thickness of this position actual (real) thickness as the corresponding region.
26. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the corresponding tube core in described each zone.
27. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, before forming hard mask layer, the top silicon layer upper surface that exposes is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone.
28. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, after forming hard mask layer and before the dopant implant ion, the top silicon layer upper surface that exposes is divided into a plurality of zones, measures actual (real) thickness corresponding to each zone.
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| CN104752503A (en) * | 2013-12-27 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Mechanisms for forming finfets with different fin heights |
| CN105097584A (en) * | 2014-05-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method for ion implantation dosage |
| CN106024868A (en) * | 2015-03-27 | 2016-10-12 | 三星电子株式会社 | Semiconductor device |
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| US20110095366A1 (en) * | 2009-10-22 | 2011-04-28 | International Business Machines Corporation | Forming an extremely thin semiconductor-on-insulator (etsoi) layer |
| US20110097824A1 (en) * | 2009-10-22 | 2011-04-28 | International Business Machines Corporation | Method of creating an extremely thin semiconductor-on- insulator (etsoi) layer having a uniform thickness |
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| CN1744298A (en) * | 2005-07-29 | 2006-03-08 | 上海新傲科技有限公司 | Method for manufacturing silicon of insulator |
| US20110095366A1 (en) * | 2009-10-22 | 2011-04-28 | International Business Machines Corporation | Forming an extremely thin semiconductor-on-insulator (etsoi) layer |
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| CN104752503A (en) * | 2013-12-27 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Mechanisms for forming finfets with different fin heights |
| CN104752503B (en) * | 2013-12-27 | 2018-01-26 | 台湾积体电路制造股份有限公司 | Method for forming the FINFET with different fin height |
| CN105097584A (en) * | 2014-05-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method for ion implantation dosage |
| CN106024868A (en) * | 2015-03-27 | 2016-10-12 | 三星电子株式会社 | Semiconductor device |
| US10867997B2 (en) | 2015-03-27 | 2020-12-15 | Samsung Electronics Co., Ltd. | Semiconductor device |
| CN106024868B (en) * | 2015-03-27 | 2021-04-13 | 三星电子株式会社 | Semiconductor device with a plurality of semiconductor chips |
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| CN103367230B (en) | 2016-05-25 |
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