CN103367128A - Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method - Google Patents
Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN103367128A CN103367128A CN2012100887567A CN201210088756A CN103367128A CN 103367128 A CN103367128 A CN 103367128A CN 2012100887567 A CN2012100887567 A CN 2012100887567A CN 201210088756 A CN201210088756 A CN 201210088756A CN 103367128 A CN103367128 A CN 103367128A
- Authority
- CN
- China
- Prior art keywords
- ion
- semiconductor substrate
- semiconductor device
- region
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The application discloses an ultra steep inverted doped channel forming method, a semiconductor device comprising an ultra steep inverted doped channel, and a semiconductor device manufacturing method. The method comprises the steps of forming a mask which exposes a semiconductor substrate region corresponding to a channel region and source/drain extension regions of the semiconductor device, performing first ion implantation operation by using the mask, and injecting in the semiconductor substrate first ions which are of the same electric conduction type as the semiconductor substrate; performing second ion implantation operation by using the mask, injecting in the semiconductor substrate second ions which are of the same electric conduction type as the semiconductor substrate, and forming an ultra steep inverted doped region by superposing injection regions formed through the first ion implantation operation and second ion implantation operation.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof, more specifically, relate to super steep formation method of falling doped channel, comprise super steep semiconductor device and the manufacture method thereof of doped channel.
Background technology
A dimensions scale downward that the important development direction is mos field effect transistor (MOSFET) of integrated circuit technique is to improve integrated level and to reduce manufacturing cost.Yet well-known is that size reduction along with MOSFET can produce short-channel effect.Along with the dimensions scale downward of MOSFET, the effective length of grid reduces, so that in fact reduced by the ratio of the depletion layer charge of grid voltage control, descends thereby threshold voltage reduces with channel length.
On the one hand, in order to suppress short-channel effect, can improve the doping content of raceway groove to improve the threshold voltage of semiconductor device.Yet, if the doping content of raceway groove is greater than 6 * 10
18/ cm
3, then adopt conventional channel doping method will bring a series of serious problems, for example threshold voltage is too high, junction capacitance obviously increases, charge carrier effective mobility μ
EffDegradation.As a result, the circuit performance of MOSFET is deteriorated on the contrary, and operating frequency and driving force all reduce.
On the other hand, in application, may need to reduce the threshold voltage of semiconductor device.For example, in 20 nanometers and following semiconductor device, the supply voltage of employing is reduced to about 0.8V.Correspondingly, the threshold voltage of semiconductor device should be controlled at ± 0.2V about, to obtain little OFF leakage current I
OffAnd the logic appearance (noise tolerance) of making an uproar.In order to reduce threshold voltage, can reduce the doping content of raceway groove.Yet the doping content that reduces raceway groove may cause above-mentioned short-channel effect again.
In the method that adopts the channel doping adjusting threshold voltage, a kind of improved technology is included in the channel region below and forms super steep doped region, utilizes super steep doping method to form precipitous doping concentration distribution at channel region.The super steep doping content of doped region is higher than channel region.Channel region and super steep doped region have formed super steep doped channel together, and its advantage comprises the inhibition short-channel effect, improves the carrier mobility of channel region, reduces parasitic capacitance.Thereby can in the threshold voltage of regulating semiconductor device, improve operating frequency and driving force.
Form difficulty that super steep when falling the doped channel faces be the alloy of super steep doped region to outdiffusion, the result is difficult to realize required precipitous doping concentration distribution.
Summary of the invention
The purpose of this invention is to provide a kind of improved super steep manufacture method of falling doped channel, comprise super steep semiconductor device and the manufacture method thereof of doped channel.
According to an aspect of the present invention, provide a kind of super steep method of doped channel that forms, comprising: form mask, this mask exposes the semiconductor substrate region corresponding to channel region and the source/drain extension region of semiconductor device; Adopt mask to carry out for the first time Implantation, in Semiconductor substrate, inject first ion identical with the conduction type of Semiconductor substrate; And adopt mask to carry out the Implantation second time, and injection second ion identical with the conduction type of Semiconductor substrate in Semiconductor substrate, wherein the injection region partial stack of Implantation and for the second time Implantation formation forms super steep doped region for the first time.
According to a further aspect in the invention, provide a kind of method of making semiconductor device, comprising: form isolation structure in Semiconductor substrate, to limit the active region of semiconductor device; Form super steep doped channel according to above-mentioned method; Form the gate stack that comprises gate-dielectric and grid conductor above channel region, wherein gate-dielectric is clipped between grid conductor and the channel region; Form the first side wall in the gate stack both sides; Adopt gate stack and the first side wall and isolation structure as hard mask, carry out pre-amorphous to Semiconductor substrate; Adopt gate stack and the first side wall and isolation structure as hard mask, Semiconductor substrate is carried out extension area inject; Form the second side wall at the first side wall; Adopt gate stack and the first side wall, the second side wall and isolation structure as hard mask, Semiconductor substrate is carried out source/leakage inject.
According to a further aspect in the invention, provide a kind of semiconductor device, comprising: Semiconductor substrate; Source/the drain region that in Semiconductor substrate, forms and source/drain extension region; In Semiconductor substrate, form and be clipped in the channel region between source/drain extension region; In Semiconductor substrate, form and be positioned at super steep doped region below channel region and the source/drain extension region; Be positioned at the gate-dielectric of channel region top; And the grid conductor that is positioned at the gate-dielectric top, wherein, the described super steep doping ion of doped region comprises first ion and second ion identical with the conduction type of Semiconductor substrate, wherein the atomic weight of the second ion ratio the first ion is larger.
The present invention utilizes the doping of two kinds of ions to form super steep doped region, and wherein the diffusion coefficient of heavy ion is low, mainly is gathered near the channel region, has formed precipitous doping concentration distribution.The doping content of channel region near surface can enough be hanged down to obtain suitable low threshold voltage, obtains simultaneously high carrier mobility.Super steep doped region below channel region suppresses admirably serious short-channel effect (SCE) and DIBL effect and occurs in the surface near channel region.Utilize mask can also limit the super steep horizontal expansion scope of doped region, to reduce junction capacitance, be conducive to the raising of speed.
Further, semiconductor device of the present invention can utilize halo region further to suppress serious short-channel effect (SCE) and the generation in vivo of DIBL effect.
Description of drawings
Fig. 1 to 8 shows to make according to an embodiment of the invention and comprises the super steep schematic sectional view of the different phase of the semiconductor device of doped channel.
Fig. 9 shows the super steep analog result of the doping concentration distribution of doped channel that forms according to embodiments of the invention.
Figure 10 shows the analog result of the Sub-Threshold Characteristic of the semiconductor device that forms according to the embodiment of the invention.
Embodiment
Hereinafter with reference to accompanying drawing the present invention is described in more detail.In each accompanying drawing, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in the accompanying drawing is not drawn in proportion.
For brevity, the semiconductor structure that obtains after several steps of process can be described in a width of cloth figure.
Be to be understood that, when the structure of outlines device, when one deck, zone are called be positioned at another layer, another zone " above " or when " top ", can refer to be located immediately at another layer, another is above zone, perhaps its and another layer, also comprise other layer or regional between another zone.And if with the device upset, this one deck, a zone will be positioned at another layer, another zone " following " or " below ".
If for describe be located immediately at another layer, another the zone above situation, this paper will adopt " directly existing ... top " or " ... top and with it the adjacency " form of presentation.
In this application, term " semiconductor structure " refers to the general designation of the whole semiconductor structure that forms in making each step of semiconductor device, comprise all layers or the zone that have formed.
Described hereinafter many specific details of the present invention, for example structure of device, material, size, treatment process and technology are in order to more clearly understand the present invention.But such just as the skilled person will understand, can realize the present invention not according to these specific details.
Unless particularly point out hereinafter, the various piece in the semiconductor device can be made of the known material of those skilled in the art.Semi-conducting material for example comprises III-V family semiconductor, such as GaAs, InP, GaN, SiC, and IV family semiconductor, such as Si, Ge.Gate conductor layer can be formed by the various materials that can conduct electricity, for example metal level, doped polysilicon layer or comprise metal level and the stack gate conductor of doped polysilicon layer or other electric conducting materials, for example be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni
3The combination of Si, Pt, Ru, Ir, Mo, HfRu, RuOx| and described various electric conducting materials.Gate dielectric layer can be by SiO
2Or dielectric constant is greater than SiO
2Material consist of, for example comprise oxide, nitride, oxynitride, silicate, aluminate, titanate, wherein, oxide for example comprises SiO
2, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, nitride for example comprises Si
3N
4, silicate for example comprises HfSiOx, aluminate for example comprises LaAlO
3, titanate for example comprises SrTiO
3, oxynitride for example comprises SiON.And gate dielectric layer not only can be formed by the known material of those skilled in the art, also can adopt the material that is used for gate dielectric layer of in the future exploitation.
According to embodiments of the invention, the following steps shown in the execution graph 1 to 8 comprise the super steep semiconductor device of doped channel with manufacturing, show in the drawings the sectional view of the semiconductor structure of different phase.
As shown in Figure 1, by known depositing operation, such as electron beam evaporation (EBM), chemical vapour deposition (CVD) (CVD), ald (ALD), sputter etc., form pad oxide layer 102 and pad nitride layer 103 in Semiconductor substrate 101.In an example, form pad oxide layer 102 by thermal oxidation, and form pad nitride layer 103 by chemical vapour deposition (CVD).Pad oxide layer 102 can alleviate the stress between substrate 101 and the pad nitride layer 103, and thickness for example is the 2-15 nanometer.Underlayer nitriding thing layer 103 is used as stop-layer in chemico-mechanical polishing (CMP) technique subsequently, thickness for example is the 50-150 nanometer.Then, form photoresist layer 201 on the underlayer nitriding thing layer 103 by being spin-coated on, and by the photoetching process comprising exposure and development photoresist layer 201 is formed patterns.
Then, utilize photoresist layer 201 as mask, pass through dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation, perhaps by wherein using the wet etching of etchant solutions, remove successively from top to bottom the expose portion of pad nitride layer 103 and pad oxide layer 102, and the part of Semiconductor substrate 101, in Semiconductor substrate 101, form groove.The control etching period is so that the certain depth place that is etched in the Semiconductor substrate 101 stops.Then, remove photoresist layer 201 by dissolving or ashing in solvent.By above-mentioned known depositing operation, form the oxide skin(coating) that covers on the whole surface of semiconductor structure.Then, as stop-layer, whole semiconductor structure is carried out chemical-mechanical planarization with pad oxide layer 103, obtain even curface.This chemical-mechanical planarization has been removed the oxide of the groove outside that is arranged in Semiconductor substrate 101, forms shallow trench isolation from (STI) 104, as shown in Figure 2 so that stay the oxide of groove inside.
Then, for example remove pad nitride layer 103 by the wet etching that uses hot phosphoric acid (for example, 160 ℃), and remove pad oxide layer 102 by the wet etching that uses buffered hydrofluoric acid solution.For example by thermal oxidation about protective oxide film of 5 nanometers (screen layer) 105 of growth thickness on the surface of Semiconductor substrate 101, as shown in Figure 3.Protective oxide film 105 is injury-free for the crystal structure on the surface of protecting Semiconductor substrate 101 in Implantation step subsequently.Protective oxide film 105 has uniform thickness, so that can pass the identical degree of depth in the protective oxide film 105 arrival Semiconductor substrate 101 at Implantation step intermediate ion subsequently.
Then, by formation photoresist layer 202 on the whole surface that is spin-coated on semiconductor structure, and by comprising the photoetching process of exposing and developing photoresist layer 202 being formed patterns.Photoresist layer 202 comprises the channel region of the semiconductor device that at least exposure will form and the window of source/drain extension region.Adopt photoresist layer 202 as mask, carry out for the first time Implantation.Implantation injects the conventional ion identical with the conduction type of Semiconductor substrate 101 via the window in the photoresist layer 202 in Semiconductor substrate 101 for the first time, as shown in Figure 4.For nmos device, the conduction type of Semiconductor substrate 101 is P types, and for the first time Implantation uses P type conventional ion, for example the boron ion (
11B), energy 40-50KeV, dosage 1-1.4E13cm
-2For the PMOS device, the conduction type of Semiconductor substrate 101 is N-types, and for the first time Implantation uses the N-type conventional ion, for example phosphonium ion (
31P) inject energy 100-120KeV, dosage 1-1.4E13cm
-2
Formed the first injection region 106 below the channel region that Implantation will form for the first time in Semiconductor substrate 101.Then, still adopt light to resist layer 202 as mask, carry out for the second time Implantation.Implantation injects the heavy ion identical with the conduction type of Semiconductor substrate 101 via the window in the photoresist layer 202 in Semiconductor substrate 101 for the second time, as shown in Figure 5.For nmos device, the conduction type of Semiconductor substrate 101 is P types, and for the second time Implantation uses P type heavy ion, for example indium ion (
115In), energy 170-210KeV, dosage 1-1.4E13cm
-2For the PMOS device, the conduction type of Semiconductor substrate 101 is N-types, and for the second time Implantation uses the N-type heavy ion, for example antimony ion (
123Sb), energy 170-210KeV, dosage 1-1.4E13cm
-2In this application, heavy ion refers to that atomic weight is greater than the ion of routine doping ion.
After second time Implantation, remove photoresist layer 202 by dissolving or ashing in solvent.
The energy of the energy Ratios of the Implantation Implantation first time is larger for the second time, so that the injection region partial stack of twice Implantation forms super steep doped region 106, as shown in Figure 6.Semiconductor substrate 101 is positioned at the part of super steep doped region 107 tops as the channel region (not shown) of the semiconductor device that will form.
Then, remove protective oxide film 105 by the wet etching that uses buffered hydrofluoric acid solution, with the surface of exposing semiconductor substrate 101.By above-mentioned known technique, on the whole surface of semiconductor structure, form successively conformal dielectric layer and the polysilicon layer of covering, patterned, thus form the gate stack that comprises gate-dielectric 108 and grid conductor 109.Then, by above-mentioned known technique, deposit for example nitride layer of 10-50 nanometer on the whole surface of semiconductor structure, then form the first side wall 110 that is positioned at the gate stack both sides by anisotropic etching, as shown in Figure 7.
Then, adopt gate stack and the first side wall and shallow trench isolation from 104 as hard mask, carry out pre-amorphous to the expose portion of Semiconductor substrate 101.In an example, inject the Ge ion, energy 15-25KeV, dosage 4-9E14 pre-amorphous comprising in Semiconductor substrate 101.Pre-amorphously in Semiconductor substrate 101, formed amorphized areas, be conducive in implantation step subsequently, form shallow junction.
Further, adopt gate stack and the first side wall 110 and shallow trench isolation from the hard mask of 104 conducts, Semiconductor substrate 101 is carried out extension area inject, thus formation source/drain extension region 111.Extension area injects to the ion of Semiconductor substrate 101 injections with the conductivity type opposite of Semiconductor substrate 101.For nmos device, extension area inject to use the N-type dopant, As ion for example, Implantation Energy 1-3KeV, dosage 6-10E14.For the PMOS device, extension area inject to use P type dopant, BF2 ion for example, Implantation Energy 1-3KeV, dosage 2-6E14.
Further, adopt gate stack and the first side wall 110 and shallow trench isolation from the hard mask of 104 conducts, Semiconductor substrate 101 is carried out haloing (halo) inject, thus formation source/leakage haloing 112.Inject at haloing, in Semiconductor substrate 101, inject the ion identical with the conduction type of Semiconductor substrate 101 in the inclination angle mode.For nmos device, haloing injects and uses P type dopant, for example BF
2Ion, Implantation Energy 40-60KeV, dosage 4-8E13,25-30 degree inclination angle.For the PMOS device, haloing inject to use the N-type dopant, As ion for example, Implantation Energy 50-60KeV, dosage 2-5E13,25-30 degree inclination angle.
Because haloing injects and to carry out in the inclination angle mode, and the degree of depth injected greater than extension area of the degree of depth injected of haloing, so haloing 112 is positioned at extension area 111 belows, and more near the center of raceway groove.
Further, according to the first side wall 110 similar modes, form the second side wall 113 at the first side wall 110.Adopt gate stack and the first side wall 110, the second side wall 113 and shallow trench isolation from the hard mask of 104 conducts, Semiconductor substrate 101 is carried out source/leakage inject, thus formation source/drain region 114.
Then, for example approximately carrying out the 3-5 spike annealing (spike anneal) of second under 1000-1080 ℃ the temperature, to activate the doping ionic agent that injects by previous implantation step and to eliminate and inject the damage that causes.
The semiconductor device that forms according to above-mentioned steps comprises source/drain region 114, source/drain extension region 111 and source/leakage haloing 112, as shown in Figure 8.Yet just as understood by the skilled person in the art, source/drain extension region 111 and source/leakage haloing 112 is optional.In the embodiment that substitutes, semiconductor device can only comprise source/drain region 114, thereby can save the formation of the first side wall, the step that pre-amorphous, extension area injects and haloing injects in above-mentioned step.In the embodiment that substitutes, semiconductor device can only comprise source/drain region 114 and source/drain extension region 111.Thereby in above-mentioned step, can save the step that haloing injects.
Show in the above-described embodiment semiconductor device and comprise shallow trench isolation from 104, be used for limiting the active area of semiconductor device.Yet, in the embodiment that substitutes, can adopt the LOCOS isolation replace shallow trench isolation from.
Illustrate in the above-described embodiment for the first time and inject conventional ion in the Implantation, inject heavy ion in the second time in the Implantation, to form super steep doped region 106.Yet, in the embodiment that substitutes, can inject heavy ion in the Implantation in the first time, inject conventional ion in the second time in the Implantation.Although the embodiment that should substitute not is most preferred mode, it still can provide favourable precipitous doping concentration distribution.
Fig. 9 shows the super steep analog result of the doping concentration distribution of doped channel that forms according to embodiments of the invention.Curve c1 is illustrated in and forms before the super steep doped region 107, adopt trap injection and high temperature to advance the distribution of the doping content of the P type trap that forms, curve c2 is illustrated in and forms super steep doped region 107 doping concentration distribution afterwards, wherein abscissa represents the degree of depth that begins from the first type surface of Semiconductor substrate 101, and ordinate represents doping content.
Trap injects and can or carry out simultaneously before the Implantation step that is used to form super steep doped region 107.
Shown in curve c2, because the diffusion coefficient of heavy ion is low, the super steep peak concentration of doped region 107 appears at the degree of depth apart from about 64 nanometers of the first type surface of Semiconductor substrate 101, thereby has realized precipitous doping concentration distribution.
Figure 10 shows the analog result of the Sub-Threshold Characteristic of the semiconductor device that forms according to the embodiment of the invention.Owing to using above-mentioned super steep doped channel, for the NMOS (grid are about 20nm) and PMOS (grid the are about 15nm) device that adopt metal gate/high K dielectric, at different voltage V
DAll obtained suitable low threshold voltage and controlled well short-channel effect down.
Above description just illustrates for example and describes the present invention, but not is intended to exhaustive and restriction the present invention.Therefore, the present invention is not limited to described embodiment.For obvious modification or the change as can be known of those skilled in the art, all within protection scope of the present invention.
Claims (16)
1. one kind forms the super steep method of doped channel, comprising:
Form mask, this mask exposes the semiconductor substrate region corresponding to channel region and the source/drain extension region of semiconductor device;
Adopt mask to carry out for the first time Implantation, in Semiconductor substrate, inject first ion identical with the conduction type of Semiconductor substrate; And
Adopt mask to carry out for the second time Implantation, in Semiconductor substrate, inject second ion identical with the conduction type of Semiconductor substrate,
Wherein the injection region partial stack of Implantation and for the second time Implantation formation forms super steep doped region for the first time.
2. method according to claim 1, wherein the atomic weight of the first ion is less than the atomic weight of the second ion.
3. method according to claim 1, wherein the atomic weight of the first ion is greater than the atomic weight of the second ion.
4. method according to claim 1, wherein the energy of Implantation is 30-60KeV for the first time, the energy of Implantation is 160-210KeV for the second time.
5. method according to claim 2, wherein said semiconductor device is nmos device, and the first ion is the boron ion, the second ion is indium ion.
6. method according to claim 3, wherein said semiconductor device is nmos device, and the first ion is indium ion, the second ion is the boron ion.
7. method according to claim 2, wherein said semiconductor device is the PMOS device, and the first ion is phosphonium ion, the second ion is antimony ion.
8. method according to claim 3, wherein said semiconductor device is the PMOS device, and the first ion is antimony ion, the second ion is phosphonium ion.
9. method according to claim 1 wherein before forming mask, also is included on the surface of half substrate and forms protective oxide film.
10. method of making semiconductor device comprises:
Form isolation structure in Semiconductor substrate, to limit the active region of semiconductor device;
Form super steep doped channel according to each described method in the claim 1 to 9;
Form the gate stack that comprises gate-dielectric and grid conductor above channel region, wherein gate-dielectric is clipped between grid conductor and the channel region;
Form the first side wall in the gate stack both sides;
Adopt gate stack and the first side wall and isolation structure as hard mask, carry out pre-amorphous to Semiconductor substrate;
Adopt gate stack and the first side wall and isolation structure as hard mask, Semiconductor substrate is carried out extension area inject;
Form the second side wall at the first side wall;
Adopt gate stack and the first side wall, the second side wall and isolation structure as hard mask, Semiconductor substrate is carried out source/leakage inject.
11. method according to claim 10, carrying out the step that extension area injects and forming between the step of the second side wall, also comprise and adopt gate stack and the first side wall and isolation structure as hard mask, Semiconductor substrate is carried out haloing in the inclination angle mode inject.
12. a semiconductor device comprises:
Semiconductor substrate;
Source/the drain region that in Semiconductor substrate, forms and source/drain extension region;
In Semiconductor substrate, form and be clipped in the channel region between source/drain extension region;
In Semiconductor substrate, form and be positioned at super steep doped region below channel region and the source/drain extension region;
Be positioned at the gate-dielectric of channel region top; And
Be positioned at the grid conductor of gate-dielectric top,
Wherein, the described super steep doping ion of doped region comprises first ion and second ion identical with the conduction type of Semiconductor substrate, and wherein the atomic weight of the second ion ratio the first ion is larger.
13. semiconductor device according to claim 12, wherein near super steep doped region has doping content channel region the peak value that falls.
14. semiconductor device according to claim 12, wherein said semiconductor device is nmos device, and the first ion is the boron ion, and the second ion is indium ion.
15. semiconductor device according to claim 12, wherein said semiconductor device are the PMOS devices, and the first ion is phosphonium ion, the second ion is antimony ion.
16. semiconductor device according to claim 12 also comprises source/leakage halo region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100887567A CN103367128A (en) | 2012-03-29 | 2012-03-29 | Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100887567A CN103367128A (en) | 2012-03-29 | 2012-03-29 | Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103367128A true CN103367128A (en) | 2013-10-23 |
Family
ID=49368226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100887567A Pending CN103367128A (en) | 2012-03-29 | 2012-03-29 | Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103367128A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514169A (en) * | 2016-01-13 | 2016-04-20 | 西安电子科技大学 | 65nm technology-based super-steep reverse-doping radiation-proof MOS field-effect tube |
| CN116504612A (en) * | 2023-02-09 | 2023-07-28 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360342A (en) * | 2000-12-19 | 2002-07-24 | 中国科学院微电子中心 | Method for realizing technological section structure of 70-nm device |
| CN1890798A (en) * | 2003-10-02 | 2007-01-03 | 英特尔公司 | Method and apparatus for improving stability of a 6T CMOS sram cell |
| CN101414647A (en) * | 2007-10-17 | 2009-04-22 | 北京中科信电子装备有限公司 | Diffusion method for high-efficiency solar battery local depth junction |
| US20100084732A1 (en) * | 2008-10-06 | 2010-04-08 | Hynix Semiconductor Inc. | Semiconductor Device and Method of Manufacturing the Same |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
| US20120252198A1 (en) * | 2010-08-31 | 2012-10-04 | Institute of Microelectronics Chinese Academy of Sciences | Method for manufacturing semiconductor structure |
-
2012
- 2012-03-29 CN CN2012100887567A patent/CN103367128A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360342A (en) * | 2000-12-19 | 2002-07-24 | 中国科学院微电子中心 | Method for realizing technological section structure of 70-nm device |
| CN1890798A (en) * | 2003-10-02 | 2007-01-03 | 英特尔公司 | Method and apparatus for improving stability of a 6T CMOS sram cell |
| CN101414647A (en) * | 2007-10-17 | 2009-04-22 | 北京中科信电子装备有限公司 | Diffusion method for high-efficiency solar battery local depth junction |
| US20100084732A1 (en) * | 2008-10-06 | 2010-04-08 | Hynix Semiconductor Inc. | Semiconductor Device and Method of Manufacturing the Same |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
| US20120252198A1 (en) * | 2010-08-31 | 2012-10-04 | Institute of Microelectronics Chinese Academy of Sciences | Method for manufacturing semiconductor structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514169A (en) * | 2016-01-13 | 2016-04-20 | 西安电子科技大学 | 65nm technology-based super-steep reverse-doping radiation-proof MOS field-effect tube |
| CN105514169B (en) * | 2016-01-13 | 2018-08-10 | 西安电子科技大学 | Super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor based on 65nm techniques |
| CN116504612A (en) * | 2023-02-09 | 2023-07-28 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116504612B (en) * | 2023-02-09 | 2023-11-21 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6921691B1 (en) | Transistor with dopant-bearing metal in source and drain | |
| US9245975B2 (en) | Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length | |
| US8329566B2 (en) | Method of manufacturing a high-performance semiconductor device | |
| US9018739B2 (en) | Semiconductor device and method of fabricating the same | |
| US6051470A (en) | Dual-gate MOSFET with channel potential engineering | |
| US8815690B2 (en) | Tunneling device and method for forming the same | |
| US8901616B2 (en) | Gate stack including a high-K gate dielectric that is optimized for low voltage applications | |
| CN103311247A (en) | Semiconductor device and manufacturing method thereof | |
| CN106328589A (en) | FinFET channel on oxide structures and related methods | |
| US8980718B2 (en) | PMOS transistors and fabrication method | |
| WO2012116529A1 (en) | Tunneling device and method for forming the same | |
| US20130043517A1 (en) | Semiconductor Structure And Method For Manufacturing The Same | |
| CN103311281A (en) | Semiconductor device and manufacturing method thereof | |
| EP1927128A2 (en) | Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current | |
| CN102315265B (en) | Semiconductor device and making method thereof | |
| CN103390637B (en) | FinFET and manufacture method thereof | |
| WO2014071754A1 (en) | Semiconductor structure and manufacturing method therefor | |
| CN103050526A (en) | MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and manufacturing method thereof | |
| CN109216192B (en) | Semiconductor device and method of forming the same | |
| CN109285778B (en) | Semiconductor device and method of forming the same | |
| CN103367128A (en) | Ultra steep inverted doped channel forming method, semiconductor device and semiconductor device manufacturing method | |
| CN102956703B (en) | Semiconductor device and manufacture method thereof | |
| CN102956647B (en) | Semiconductor device and manufacture method thereof | |
| CN110718463A (en) | Tunneling field effect transistor and forming method thereof | |
| CN103985712B (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131023 |