CN103366817B - NOR flash memory - Google Patents
NOR flash memory Download PDFInfo
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- CN103366817B CN103366817B CN201310332165.4A CN201310332165A CN103366817B CN 103366817 B CN103366817 B CN 103366817B CN 201310332165 A CN201310332165 A CN 201310332165A CN 103366817 B CN103366817 B CN 103366817B
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Abstract
The invention discloses an NOR flash memory. The NOR flash memory comprises a memory cell array and a peripheral circuit. The peripheral circuit comprises 2P row decoding circuits, 2P column decoding circuits and P source line driving circuits. The memory cell array comprises P double-array units. Each one of the P double-array units comprises 2 subarrays. P is positive integer. The subarrays are correspondingly connected to the row decoding circuits by word lines. The subarrays are correspondingly connected to the column decoding circuits by bit lines. The double-array units are in a one-to-one correspondence relationship with the source line driving circuits. The subarrays are connected to the source line driving circuits corresponding to the double-array units comprising the subarrays by source lines. The memory cell array is divided into an even number of the subarrays and each two of the subarrays use one source line driving circuit in common. Compared with the prior art, the NOR flash memory reduces the number of the source line driving circuits, reduces a memory occupation area and solves the existing technical problems.
Description
Technical field
The application is related to technical field of data storage, more particularly, to a kind of NOR flash memory.
Background technology
NOR-type (NOR-logic type, also known as Linear technology) flash memory type memorizer is a kind of non-volatility semiconductor storage
Device, is mainly made up of memory cell array and peripheral circuit.Peripheral circuit mainly includes row decoding circuit (X-Decoder), row
Decoding circuit (YMUX) and source line driving circuit (SL-driver), wherein, row decoding circuit is used for driving memory cell array
Wordline, array decoding circuit is used for driving the bit line of memory cell array.
For improving reading speed, the memory cell array of existing NOR flash memory is generally divided into mutually only
Vertical multiple subarrays (Cell Array), multiple subarrays are in line, and each subarray is owned by respective row decoding
Circuit, array decoding circuit and source line driving circuit are so that memory usage area is excessive.
Content of the invention
In view of this, the application purpose is to provide a kind of NOR flash memory, to solve existing NOR-type flash memory
The excessive problem of formula memorizer peripheral drive circuit area occupied.
For achieving the above object, the application provides following technical scheme：
A kind of NOR flash memory, including memory cell array and peripheral circuit；
Described peripheral circuit includes 2P row decoding circuit, 2P array decoding circuit and P source line driving circuit；Described deposit
Storage unit array includes P double array element, and each described pair of array element includes 2 subarrays；P is positive integer；
Described subarray is connected one to one by wordline with described row decoding circuit；Described subarray and described column decoding
Circuit is connected one to one by bit line；Each described pair of array element corresponds to a described source line driving circuit, described submatrix
Row are connected to the source line driving circuit corresponding with the double array elements belonging to described subarray by source line.
Preferably, described P double array elements press the matrix form arrangement that n row k arranges；K, n are positive integer.
Preferably, work as n>When 1, described array decoding circuit includes local array decoding circuit；
Described peripheral circuit also includes an overall array decoding circuit；Described overall situation array decoding circuit and sense amplifier electricity
Road connects, and described overall situation array decoding circuit is connected with described local array decoding circuit by global bit line；Described overall situation column decoding
Circuit is used for entering row decoding to column address, to obtain and to gate the corresponding global bit line of described column address.
Preferably, described memorizer carries out digital independent in the following manner：
The source line of described subarray is grounded by source line driving circuit simultaneously；
Described row decoding circuit enters row decoding to the row address of data to be read, and obtains word corresponding with described row address
Line；
Described local array decoding circuit enters row decoding to the column address of described data to be read, and gate that decoding obtains with
The corresponding bit line of described column address, described overall situation array decoding circuit enters row decoding to the column address of described data to be read, and selects
The global bit line corresponding with described column address that interpreter's code obtains；
To described and described row address, corresponding wordline is charged, and passes through described sensitive amplifier circuit sensing logical simultaneously
Cross the described global bit line being strobed conveying, the current value of the described bit line being strobed；
The current value I and reference current value I of sensitive amplifier circuit sensing at the end of charging0It is compared, according to institute
State comparative result and obtain described data to be read.
It can be seen from above-mentioned technical scheme that, memory cell array is divided into even number subarray by the application, and often
Two subarrays share a source line driving circuit.With respect to prior art, memory cell array total capacity certain, ensure to read
On the premise of taking speed, the embodiment of the present application greatly reduces the number of source line driving circuit, thus greatly reducing memorizer
Area occupied, solve problem of the prior art.
Brief description
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of application, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
The structure principle chart of the NOR flash memory that Fig. 1 provides for the embodiment of the present application one；
Single pair of array element of the NOR flash memory that Fig. 2 provides for the embodiment of the present application one and its periphery electricity
The structural representation on road；
The structure principle chart of the NOR flash memory that Fig. 3 provides for the embodiment of the present application two；
Single pair of array element of the NOR flash memory that Fig. 4 provides for the embodiment of the present application two and its periphery electricity
The structural representation on road.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of the application protection.
The embodiment of the present application discloses a kind of NOR flash memory, is accounted for solving existing NOR flash memory
With the excessive problem of area.
The NOR flash memory providing with reference to Fig. 1, the embodiment of the present application one, by memory cell array and periphery electricity
Road forms.
Wherein, peripheral circuit includes 2P row decoding circuit 21 (i.e. X-decoder), 2P array decoding circuit 22 (i.e.
YMUX) and P source line driving circuit 23 (i.e. Common SL-driver), P is positive integer.Memory cell array includes P pair
Array element, each double array element is made up of 2 identical subarrays 1 (i.e. Cell Array), i.e. memory cell array bag
Include 2P subarray 1；Each double array element corresponds to a source line driving circuit 23, and two submatrixs in this pair of cell array
Row 1 are connected with source line driving circuit 23 by source line respectively；Subarray 1 is corresponded even by wordline with row decoding circuit 21
Connect；Subarray 1 is connected one to one by bit line with array decoding circuit 22.Single pair of array element and peripheral circuit associated therewith
Structural representation as shown in Figure 2.
When reading data in memorizer, data address includes row address (X address) and column address (Y address) two
Part.Assume the data (X1 is row address, and Y1 is column address) of storage in address to be read (X1, Y1), the NOR to said structure
When type flash memory type memorizer carries out data read operation, process is as follows：Source line is connected to ground potential by source line driving circuit 23, drives
Corresponding subarray；Meanwhile, row decoding circuit 21 and array decoding circuit 22 response address change simultaneously：Row decoding circuit 21
Row decoding is entered to row address X1, obtains the corresponding wordline of this row address X1 and choose；Array decoding circuit 22 is carried out to column address Y1
Decoding, obtains the corresponding bit line of this column address Y1 and chooses；The bit line that array decoding circuit 22 is chosen is connected to sense amplifier
Circuit input end mouth.The wordline that row decoding circuit 21 is chosen is charged, simultaneously sensitive amplifier circuit input port sensing
Electric current on connected bit line；When wordline charging complete when current stabilization () on selected bit line, will be sensitive
The current value I and reference current value I of amplifier circuit input port sensing0It is compared, obtain storage in address (X1, Y1)
Data D；As I>I0, then D=0；I<I0, then D=1.
From said structure and data read process, memory cell array is divided into even number height by the embodiment of the present invention
Array, and each two subarray (a double array element) shares a source line driving circuit.With respect to prior art, in storage
Cell array total capacity is certain, ensure reading speed on the premise of, the embodiment of the present application greatly reduces source line driving circuit
Number, thus greatly reducing the area occupied of memorizer, solves problem of the prior art.
Specifically, in above-described embodiment, the double array element of source line driver source line driver P can be arranged as the matrix of n row k row
(k, n are positive integer, and P=k*n).The long width values of the occurrence of k, n NOR flash memory according to actual needs and
Fixed.
The NOR flash memory providing referring to Fig. 3, the embodiment of the present application two, by memory cell array and periphery electricity
Road forms.Peripheral circuit includes 2P row decoding circuit 21,2P local array decoding circuit 22 ' (i.e. Local YMUX), P source
Line drive circuit 23 and 1 overall array decoding circuit 24 (i.e. Global YMUX), P is positive integer.Memory cell array includes P
Individual pair of array element, each double array element is made up of 2 identical subarrays 1 (i.e. Cell Array), i.e. memory element battle array
Row include 2P subarray 1.P double array elements are arranged as the matrix (i.e. P=k*n) of n row k row, and k, and n is positive integer, n>
1；Depending on the occurrence of n and k needs according to application.
Wherein, each double array element corresponds to a source line driving circuit 23, and two submatrixs in this pair of cell array
Row 1 are connected with source line driving circuit 23 by source line respectively；Subarray 1 is corresponded even by wordline with row decoding circuit 21
Connect；Subarray 1 is connected one to one by bit line with local array decoding circuit 22 '.Overall array decoding circuit 24 passes through overall position
Line (i.e. Global bit line) is connected with local array decoding circuit 22 '；Overall array decoding circuit 24 is gone back and sense amplifier
(Sense Amplifier, abbreviation SA) circuit 3 connects.The structure of the circuit of single pair of array element and periphery associated therewith is shown
It is intended to as shown in Figure 4.
Assume the data (X2 is row address, and Y2 is column address) of storage in address to be read (X2, Y2), to said structure
When NOR flash memory carries out data read operation, process is as follows：Source line is connected to ground potential by source line driving circuit 23,
Drive corresponding subarray；Meanwhile, row decoding circuit 21, local array decoding circuit 22 ' and overall array decoding circuit 24 are same
When response address change：Row decoding circuit 21 enters row decoding to row address X2, obtains the corresponding wordline of this row address X2 and chooses；
Local array decoding circuit 22 ' enters row decoding to column address Y2, obtains the corresponding bit line of this column address Y2 and chooses this bit line, the overall situation
Array decoding circuit 24 enters row decoding to column address Y2, obtains the corresponding global bit line of this column address Y2, and chooses this global bit line,
Electric current on selected bit line is by the selected overall array decoding circuit 24 of global bit line input, and finally enters sensitive putting
The input port of big device circuit 3.The wordline that row decoding circuit 21 is chosen is charged, and sensitive amplifier circuit 3 inputs simultaneously
Electric current on port sensing and selected bit line；(the current stabilization on selected bit line when wordline charging complete
When), by the current value I and reference current value I of sensitive amplifier circuit 3 input port sensing0Be compared, obtain address (X2,
Y2 data D of storage in)；As I>I0, then D=0；I<I0, then D=1.
For n>1 situation obtains the common j bar of the corresponding bit line of column address, then it is assumed that often going local array decoding circuit decoding
The selected bit line sum of memory array is n*j>J, that is, column address corresponding bit line sum is more than the quantity of data channel；This
Embodiment is passed through to link the quantity of the global bit line increase data channel of local array decoding circuit and overall array decoding circuit, makes position
Data in the bit line of same row different rows is all exported.
From said structure and reading process, the application is by the dimensional requirement according to memorizer, single by P for source line driver
Identical permutation is the matrix of n row k row, simultaneously by the overall decoding circuit of increase and by global bit line, each subarray is local
Array decoding circuit is connected with this overall decoding circuit respectively, so that the data of the bit line positioned at same row different rows is all exported；
Can be only positioned in same a line with respect to the multiple subarray of prior art, the embodiment of the present application can more fully utilization space so that
The certain memorizer of capacity has multiple possible long width values, meets different application demands.
One of ordinary skill in the art will appreciate that realizing all or part of flow process in above-described embodiment method, it is permissible
Instruct related hardware to complete by computer program, described program can be stored in a computer read/write memory medium
In, described program is upon execution, it may include as the flow process of the embodiment of above-mentioned each method.Wherein, described storage medium can be
Magnetic disc, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the application.
Multiple modifications to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can be realized in the case of without departing from spirit herein or scope in other embodiments.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and be to fit to and principles disclosed herein and features of novelty phase one
The scope the widest causing.
Claims (1)
1. a kind of NOR flash memory is it is characterised in that include memory cell array and peripheral circuit；
Described peripheral circuit includes 2P row decoding circuit, 2P array decoding circuit and P source line driving circuit；Described storage is single
Element array includes P double array element, and each described pair of array element includes 2 subarrays；P is positive integer；
Described subarray is connected one to one by wordline with described row decoding circuit；Described subarray and described array decoding circuit
Connected one to one by bit line；Each described pair of array element corresponds to a described source line driving circuit, and described subarray leads to
The source line of mistake is connected to the source line driving circuit corresponding with the double array elements belonging to described subarray；
Wherein, described P double array elements press the matrix form arrangement that n row k arranges；K, n are positive integer；
And, work as n>When 1, described array decoding circuit includes local array decoding circuit；
Described peripheral circuit also includes an overall array decoding circuit；Described overall situation array decoding circuit is with sensitive amplifier circuit even
Connect, described overall situation array decoding circuit is connected with described local array decoding circuit by global bit line；Described overall situation array decoding circuit
For row decoding is entered to column address, to obtain and to gate the corresponding global bit line of described column address；
Described memorizer carries out digital independent in the following manner：
The source line of described subarray is grounded by source line driving circuit simultaneously；
Described row decoding circuit enters row decoding to the row address of data to be read, and obtains wordline corresponding with described row address；
Described local array decoding circuit enters row decoding to the column address of described data to be read, and gate that decoding obtains with described
The corresponding bit line of column address, described overall situation array decoding circuit enters row decoding to the column address of described data to be read, and gates and translate
The global bit line corresponding with described column address that code obtains；
To described and described row address, corresponding wordline is charged, and passes through described sensitive amplifier circuit sensing simultaneously and passes through institute
State the global bit line conveying, current value of the described bit line being strobed being strobed；
The current value I and reference current value I of sensitive amplifier circuit sensing at the end of charging0It is compared, according to described comparison
Result obtains described data to be read.
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| CN201310332165.4A CN103366817B (en) | 2013-08-01 | 2013-08-01 | NOR flash memory |
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|---|---|---|---|
| CN201310332165.4A CN103366817B (en) | 2013-08-01 | 2013-08-01 | NOR flash memory |
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| CN103366817B true CN103366817B (en) | 2017-02-08 |
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| CN105097031A (en) * | 2014-05-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Data reading method and circuit of nonvolatile memory, and nonvolatile memory |
Citations (2)
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| CN1540759A (en) * | 2003-04-25 | 2004-10-27 | ��ʽ���綫֥ | Semiconductor memory contg MOS transistor therewith flating grid and controlling grid |
| CN103177758A (en) * | 2011-12-22 | 2013-06-26 | 华邦电子股份有限公司 | Semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW546840B (en) * | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
| JP4143287B2 (en) * | 2001-11-08 | 2008-09-03 | エルピーダメモリ株式会社 | Semiconductor memory device and data read control method thereof |
| JP4805733B2 (en) * | 2006-06-21 | 2011-11-02 | 株式会社東芝 | Semiconductor memory device and test method thereof |
| IT1404183B1 (en) * | 2011-02-28 | 2013-11-15 | St Microelectronics Srl | ADDRESS DECODING DEVICE |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540759A (en) * | 2003-04-25 | 2004-10-27 | ��ʽ���綫֥ | Semiconductor memory contg MOS transistor therewith flating grid and controlling grid |
| CN103177758A (en) * | 2011-12-22 | 2013-06-26 | 华邦电子股份有限公司 | Semiconductor memory device |
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