CN103365976B

CN103365976B - XDL level netlist is described and carries out application oriented test modifications method and method of testing

Info

Publication number: CN103365976B
Application number: CN201310268650.XA
Authority: CN
Inventors: 俞洋; 刘旺; 陈诚
Original assignee: Harbin Institute of Technology
Current assignee: Harbin Institute of Technology
Priority date: 2013-06-28
Filing date: 2013-06-28
Publication date: 2016-06-15
Anticipated expiration: 2033-06-28
Also published as: CN103365976A

Abstract

Use Perl language that circuit XDL level netlist is described and carry out application oriented test modifications method and method of testing, relate to a kind of circuit XDL level netlist is described and carry out application oriented test modifications method and method of testing. It is to solve the existing problem that circuit XDL level netlist describes the correctness carrying out application oriented test modifications and effectiveness difference. The present invention uses the Xilinx XDL instrument provided that NCD file is converted to XDL file, then the Perl language amendment XDL file being applicable to text-processing is used, finally by XDL instrument, amended XDL file is changed into NCD file, obtain last configuration file, complete circuit XDL level netlist is described to carry out application oriented test modifications. The present invention is applicable to circuit XDL level netlist is described carry out application oriented test modifications and test.

Description

XDL level netlist is described and carries out application oriented test modifications method and method of testing

Technical field

The present invention relates to a kind of circuit XDL level netlist is described and carry out application oriented test modifications method and method of testing.

Background technology

In general, the basic procedure of one FPGA design is divided into following a few step, as shown in Figure 1: herein above in several steps, by synthesis tool by HDL language, the design input such as schematic diagram translate into by with or, the logic that forms of the gate such as non-and the basic logic unit such as RAM, trigger be connected (netlist), and the logic connection generated is optimized according to target and requirement, thus generating EDF file (EDA industry-standard file). Then functional simulation is carried out, the function of checking design, use, after meeting function, (Implement) instrument of realization, the logic netlist comprehensively exported is translated into the hardware primitive of the bottom module of selected device, by in design map to device architecture, it is laid out wiring, reaches to realize the purpose of design on selected device. Make design reach the temporal constraint of requirement thereafter through timing verification, ultimately produce the download programming file that can download in FPGA accordingly, it is achieved chip programming.

Summary of the invention

The present invention is to solve the existing problem that circuit XDL level netlist describes the correctness carrying out application oriented test modifications and effectiveness difference, uses Perl language that the description of circuit XDL level netlist is carried out application oriented test modifications method thus providing a kind of.

Use Perl language that circuit XDL level netlist is described and carry out application oriented test modifications method, it is characterized in that: its method is:

Use the Xilinx XDL instrument provided that NCD file is converted to XDL file, then the Perl language amendment XDL file being applicable to text-processing is used, finally by XDL instrument, amended XDL file is changed into NCD file, obtain last configuration file, complete circuit XDL level netlist is described to carry out application oriented test modifications.

XDL file is the readable documents of text formatting.

Use Perl language to circuit XDL level netlist describe carry out application oriented test modifications method particularly as follows:

Comprehensive rear netlist NCD file is converted to readable XDL file by step one, use ISE;

Step 2, analyze XDL file and by FPGAEditor instrument extract placement-and-routing, CLB configuration information;

Step 3, make user's unbound document according to the information of placement-and-routing, it may be assumed that UCF file, it is intended that the position of CLB;

Step 4, to circuit XDL level netlist describe modify, it is thus achieved that be ultimately used to the NCD file of test.

Based on the Perl language that uses described in said method, circuit XDL level netlist is described the interconnecting test method carrying out application oriented test modifications method,

The configuration of the LUT in circuit to be tested is respectively modified and helps and logic or complete or logic, and then realize interconnecting test.

Described interconnecting test method particularly as follows:

The configuration of the LUT in circuit to be tested is respectively modified and helps and logic,

Use XDL instrument that amended XDL file is converted to NCD file, as the configuration file of first time test configurations in interconnecting test;

Again the configuration of the LUT in circuit to be tested is respectively modified and helps or logic,

After having revised all of LUT, convert NCD file to, as the configuration file of second time test configurations, and then the description of circuit XDL level netlist is carried out application oriented interconnecting test.

Based on using Perl language that circuit XDL level netlist describes the logic test method carrying out application oriented test modifications method,

Untapped CLB adds test vector generator and response analyzer, and the output of test vector generator is connected to the input of LUT to be measured, the outfan of LUT is connected on corresponding analysis device, and then circuit XDL level netlist is described the programmable logic resource test carrying out application oriented test modifications method.

LUT is for having n input, and n is positive integer, to circuit XDL level netlist describe carry out application oriented test modifications method programmable logic resource test method particularly as follows:

Adopt the enumerator of a n position as test vector generator, use Verilog hardware design language to realize;

Enumerator be added in source code add, particularly as follows:

The module built with Verilog code is added in source code, and in original design code, increases a clock signal and a reset signal for enumerator;

Then it is compiled comprehensive, enumerator is placed in untapped slice; It is XDL file by the NCD file translations after comprehensive, deletes the wiring of the input of LUT to be measured;

Subsequently by creating annexation, counter signals is connected on LUT, and revises XDL file, create the connection between counter output and LUT input to be measured; And then realize circuit XDL level netlist describes the programmable logic resource test carrying out application oriented test modifications method.

The present invention improves existing correctness and effectiveness circuit XDL level netlist being described and carrying out application oriented test modifications.

Accompanying drawing explanation

Fig. 1 is the basic flow sheet of the FPGA design described in background of invention;

Fig. 2 is the principle schematic of automatic PAR of the present invention;

Fig. 3 uses the UCF principle schematic specifying slice position;

Fig. 4 is the principle schematic adding enumerator;

Fig. 5 is the principle schematic deleting the wiring of LUT input;

Fig. 6 creates catenation principle schematic diagram between enumerator output and LUT input;

Fig. 7 is wiring philosophy schematic diagram between enumerator output and LUT input;

Fig. 8 is artificial circuit schematic diagram;

Fig. 9 is the primary circuit output result in direct fault location emulation;

Figure 10 is that 0 type fault output result is fixed in the net4 injection in direct fault location emulation;

Figure 11 is that 1 type fault output result is fixed in the net4 injection in direct fault location emulation;

The output result after complete and configuration in the emulation of Figure 12 interconnecting test configuration;

The output result after complete or configuration in the emulation of Figure 13 interconnecting test configuration;

On Figure 14 interconnection line, " 0 " type fault output result is fixed in the detection in fault detect;

On Figure 15 interconnection line, " 1 " type fault output result is fixed in the detection in fault detect;

Output result before direct fault location in the test of Figure 16 FPGA;

Output result after direct fault location in the test of Figure 17 FPGA.

Detailed description of the invention

Circuit XDL level netlist is described and carries out application oriented test modifications method by detailed description of the invention one, use Perl language, and its method is:

Use Perl language that circuit XDL level netlist is described to carry out application oriented test modifications method and be distinctive in that described in detailed description of the invention two, this detailed description of the invention and detailed description of the invention one, use Perl language circuit XDL level netlist is described carry out application oriented test modifications method particularly as follows:

Owing to original design file is not revised in test, do not change original design function, so in order to realize application oriented method of testing, so the step that realizes in above step can only being operated. Realization is broadly divided into three steps, and translation (Translate) logic netlist, mapping (Map) are to device cell and placement-and-routing (Place&Route). The instrument of FPGA and offer thereof by comparing order the first two main flow FPGA Xilinx company of manufacturer and altera corp, the present invention selects the FPGA of Xilinx company as object of study, and reason is as follows:

(1) FPGA structure of the Xilinx FPGA structure than Altera is more open;

(2) FPGA of Xilinx develops software I SE and can provide more FPGA information;

(3) the ISE software of Xilinx allows user revise configuration file as required and provide corresponding tool;

(4) research platform of most of FPGA method of testings is all the FPGA of Xilinx, has comparability.

Realizing in process based on ISE, the Main Function of translation is fabric and hardware primitive that the logic netlist comprehensively exported is translated as Xilinx certain device, in translation process, design document and unbound document will be merged into the files such as NGD (initial form data base) output file, and wherein NGD file contains whole logical descriptions of current design. The Main Function mapped is by design map to the device of concrete model (LUT, FF, Carry etc.), in mapping process, the NGD file generated by flow path switch will be mapped as the specific physical logic units of target devices, and it is maintained in NCD file, NCD file contains the physical mapping information of current design, additionally can export the files such as the PCF (physical constraint file) that comprises all physics constraint informations.And placement-and-routing's step can call Xilinx placement-and-routing device, according to user's constraint and physical constraint, design module is carried out the layout of reality, and connect according to design, module after layout is connected up, produce FPGA configuration file, placement-and-routing's process is by reading the NCD file of current design, the physical logic units generated after mapping is placed and line in goal systems, and it being extracted into corresponding time parameter, output file includes the associated documents such as NCD and DLY (time delay file).

In the method for testing realization that invention uses, mainly it is through amendment NCD file and obtains corresponding test configurations. Using the Xilinx XDL instrument provided that NCD file is converted to XDL file, this file is the readable documents of text formatting, and the grammer of use is Xilinxdesignlanguage. Then use the Perl language being applicable to text-processing to revise XDL file on request, again through XDL instrument, amended XDL file is changed into NCD file, obtain last configuration file.

Explaining with a simply example circuit for each step, this circuit is 5 inputs (i1, i2, i3, i4, i5), 2 output (o1, o2) combinational circuit, it is achieved logic be

O1=i1&i2 | i3

O2=o1&i4& (! I5)

Circuit uses Verilog language to describe, and objective chip model is XC5VFX100T, encapsulates FF1738.

Detailed description of the invention three, based on using Perl language that circuit XDL level netlist is described to carry out the interconnecting test method of application oriented test modifications method described in detailed description of the invention one,

Content described in present embodiment is the realization of interconnecting test.

Use Perl language that circuit XDL level netlist is described to carry out the interconnecting test method of application oriented test modifications method and be distinctive in that described in detailed description of the invention four, this detailed description of the invention and detailed description of the invention four, described interconnecting test method particularly as follows:

For example circuit, use the result after the comprehensive also automatic placement and routing of ISE as shown in Figure 2. Real resource in the FPGA that in figure, different square frames are corresponding from left to right respectively overall situation cross bar switch, localized chiasma switch, buffer, I/O port and slice (programmable logic resource in Xilinx). Wherein, the resource of the box indicating of dark blacking is hardware FPGA resource actually used in design. Fine rule in figure is the interconnection line connecting each functional device used in design in actual FPGA, namely now needs those interconnection lines of test.

As can be seen from Figure 2 this circuit employs two LUT, it is respectively present in two slice, in order to prove that user's unbound document can effectively retrain the position of slice, the two slice is assigned to the slice in the upper right corner of present position by use UCF file, as shown in Figure 3.

Then the configuration logic of LUT is revised, it is achieved the test of interconnection.Here will to through UCF file specify after circuit be operated because practical application design in order to meet some timing requirements all can use UCF file to design add constraint. Use the XDL instrument in ISE, the NCD file after placement-and-routing (PAR) is converted to the XDL file of text formatting, XDL file finds the slice of correspondence. The slice such as used in this circuit, its being described as in XDL file:

In order to the configuration of LUT being changed into complete and logic, by statement therein

D6LUT:oLgc11:#LUT:O6=((A2*A4)+A6)

It is revised as:

D6LUT:oLgc11:#LUT:O6=((A2*A4) * A6)

It is in like manner complete and logic by the configuration modification of other LUT. Reuse XDL instrument and amended XDL file is converted to NCD file, as the configuration file of first time test configurations in interconnecting test. Second time for interconnecting test configures, it is necessary to by the configuration modification of LUT that uses in design for entirely or logic, method is similar, for upper example, by statement

D6LUT:oLgc11:#LUT:O6=((A2*A4)+A6)

It is revised as:

D6LUT:oLgc11:#LUT:O6=((A2+A4)+A6)

After having revised all of LUT, convert NCD file to, as the configuration file of second time test configurations.

In order to verify the effectiveness of this amending method, it is possible to open amended NCD file in FPGAEditor, checked by attribute observation window. By above operation, it is possible to complete the test configurations of interconnection.

Detailed description of the invention five, based on using Perl language that circuit XDL level netlist is described to carry out the logic test method of application oriented test modifications method described in detailed description of the invention one,

The realization of the FPGA test described in present embodiment.

Use Perl language that circuit XDL level netlist is described to carry out the logic test method of application oriented test modifications method and be distinctive in that described in detailed description of the invention six, this detailed description of the invention and detailed description of the invention five, circuit XDL level netlist is described the method for the programmable logic resource test carrying out application oriented test modifications method particularly as follows:

Adopt the enumerator of 6 as test vector generator, use Verilog hardware design language to realize;

Enumerator be added in source code add, particularly as follows:

In order to test programmable logic resource, configure under the premise of logic and position inside the CLB not changing original design use, needs untapped CLB in the design adds test vector generator and response analyzer, and the output of test vector generator is connected to the input of LUT to be measured, the outfan of LUT is connected on corresponding analysis device.Here only describing the adding method of test vector generator, the adding method of response analyzer is similar.

Owing to the LUT of objective chip has 6 inputs, so the enumerator of use one 6 is as test vector generator, Verilog hardware design language is used to realize. Enumerator be added with two kinds of methods, design source code in add counter module form add and add with the form of IP kernel after placement-and-routing. Used here as the method added in source code. The module built with Verilog code is added in source code, and in original design code, increases a clock signal and a reset signal for enumerator. Note add time need to counter module add KEEP constraint, with ensure be comprehensively not optimised fall. Because counter module simply calls in source code but does not use.

Then compiling is comprehensive, is placed into by enumerator in untapped slice, and as shown in Figure 4, in figure, two slice in the lower left corner are that the main part of enumerator, clock and reset signal do not show in the drawings.

Then this NCD file after comprehensive is transferred to XDL file, the wiring of the input of LUT to be measured is deleted in amendment, result is as shown in Figure 5, compared with Fig. 4, wiring between input and the chip input pin of two LUT to be measured in right side is all deleted, and on the downside of LUT input on the upside of the right and the right, the wiring of LUT outfan is also deleted. Two LUT all only remaining lines between respective outfan and chip output pin. The precondition that the output signal of enumerator is added to LUT input has just been possessed after disconnecting.

Then, in order to realize being connected on LUT by counter signals, first must create annexation, then realize wiring. Amendment XDL file, creates the connection between counter output and LUT input to be measured. Fig. 6 illustrates the result of this step, and the fly line in figure represents there is annexation between 2 but also do not connect up.

FPGAEditor instrument use self routing function complete the wiring between the connection that previous step creates, obtain the configuration file for FPGA test, Fig. 7 is the result after wiring, can be clearly seen that the outfan of enumerator is connected to the input of LUT to be measured already by ICR interconnection resource from figure.

So far, three configuration files for whole test complete, and including for interconnecting the complete of first time configuration and logical profile, the complete or logical profile of second time configuration, for the configuration file of programmable logic resource test.

To sum up, the application oriented test to ICR interconnection resource in FPGA and programmable logic resource can be realized by above-mentioned steps. Realize in process in method of testing, sizable FPGA resource can be used when designing very big, then the workload manually revising XDL file on request will be quite huge, therefore in invention, employ Perl program and completes the amendment to XDL file.

Below with another one example circuit, the correctness of the mode validation test method by emulating:

In simulations, the circuit of use is that 6 inputs 2 export, and employs the combinational circuit of 4 LUT. The logic function that each LUT realizes is as follows:

Net1=(iLgc1 | iLgc4) ^iLgc3

Net2=(iLgc4&iLgc5) | iLgc6

Net3=net4^net2

Net1

Wherein iLgc1～iLgc6 is the input of circuit, and net1～net4 is the output of each LUT, and net2 and net3 is respectively as the output of whole circuit, and circuit structure is as shown in Figure 8.

The simulating, verifying of interconnecting test and analysis:

The method of testing used in the present invention is for fixing 0 type fault and fixing 1 type fault and carry out testing on interconnection line, then for the effectiveness of validation test method, it is necessary to artificially inject fault in circuit. Here by the artificial logic configuring LUT4, make net4 be always maintained at " 0 " or " 1 " respectively, the injection of fault can be realized.

When making net4 to occur fix 0 type fault, the configuration logic of LUT4 is artificially revised as

Net4=net1& (! Net1)

So no matter why the input of LUT4 is worth, and the value of net4 is all fixed on " 0 ". In like manner injecting the method fixing 1 type fault on net4 is artificially the logic of LUT4 be configured to

Net4=net1 | (! Net1)

Why the input that so can realize no matter LUT4 is worth, and the value on net4 is all " 1 ".

Fig. 9 is to the simulation result obtained after 6 inputs applying counter signals of used circuit in experiment, using as reference. Figure 10 injects the circuit output figure after fixing 0 type fault at net4, the input of circuit remains counter signals, as can be seen from the figure the result of oLgc1 is identical with primary circuit, and the result of outfan oLgc2 is different with primary circuit, from primary circuit structural analysis, output oLgc1 draws from net2, output oLgc2 draws from net3, output for LUT3, and the logic function that LUT3 realizes is the XOR of net2 and net4, this it appears that the value of the XOR result oLgc2 just of oLgc1 and " 0 " from Figure 10, it can be said that bright circuit is filled with on net4 and fix 0 type fault. in like manner still applying counter signals at input in Figure 11, the value of oLgc2 is being just the XOR result of oLgc1 and " 1 ", it can be said that to be filled with on net4 in bright circuit and fixes 1 type fault.

The output result that what Figure 12 to 13 provided is is undertaken circuit after test configurations under counter signals. Figure 12 fixes the complete of 0 type fault and logic configuration on test interconnection line, the logic realized in LUT be all LUT input signal with. From primary circuit structure it can be seen that output oLgc1 be input iLgc4～iLgc6 with, output oLgc2 be input iLgc1～iLgc6 with. The result of Figure 12 is just corresponding with input, and oLgc1 is just only " 1 " when iLgc4～iLgc6 is " 1 ", and oLgc2 is " 1 " when iLgc1～iLgc6 is " 1 ". The result of Figure 13 is also corresponding with input, and oLgc1 is just only " 0 " when iLgc4～iLgc6 is " 0 ", and oLgc2 is " 0 " when iLgc1～iLgc6 is " 0 ". Figure 12 to 13 demonstrate configuration help with and complete or logic after the correctness of result.

Net4 is injected separately into 0 type of fixing and fixes 1 type fault, and use corresponding method of testing to test respectively, what provide in Figure 14 is that 0 type fault is fixed in circuit injection, use complete and configuration, input applies all-1 test vector, as can be seen from the figure, after 200ns place applies all-1 test vector, outfan oLgc1 is output as " 1 ", illustrate the front-end circuit of oLgc1 does not break down, oLgc2 is output as " 0 ", illustrates that detecting that circuit exists fixes 0 type fault, and this fault occurs on the circuit relevant with oLgc2. In fig .15, circuit injects fixes 1 type fault, input at circuit applies all-0 test vector, as can be seen from the figure, after 200ns place test vector applies, oLgc1 is output as " 0 ", illustrates that 0 type fault normally do not fixed by the front-end circuit of oLgc1, and oLgc2 is output as " 1 ", illustrates the front-end circuit of oLgc2 there occurs and fix 0 type fault.The front end of the position, position of net4 and oLgc2 in this circuit arrangement, and with oLgc1 without influence on oLgc1.

The simulating, verifying of FPGA test and analysis:

What Figure 16 provided is the simulation result before injection logic fault, and the signal that the input of each LUT adds is provided by the test vector generator used in enumerator and emulation. The output of each LUT is guided on the IO of FPGA respectively, and corresponding relation is that LUT1 is output as oLgc3, LUT2 and is output as oLgc1, LUT3 and is output as oLgc2, LUT4 and is output as oLgc4, with observed result. In emulation, the LUT that the output result (oLgc1～oLgc4) of primary circuit LUT and emulation obtain being exported result (oLgc1_R～oLgc4_R) and compares, fault display signal is (fault1～fault4) respectively. By as can be seen from Figure 16, it does not have the primary circuit LUT output injecting fault is identical with the LUT of emulation output, and all of fault display signal always remains as " 0 ", does not namely break down.

Injecting fault on the programmable logic resource that primary circuit uses to be used for testing, in emulation, the logic realized in LUT3 was XOR originally, is artificially revised as now or logic, namely achieves the direct fault location on programmable logic resource. The input of each LUT connects the corresponding output signal encouraging maker, and as can be seen from Figure 17, difference occurs after about 2us in oLgc2 and oLgc2_R, and fault display signal fault2 also becomes " 1 " simultaneously, it was shown that corresponding LUT3 has logic fault. Thus can illustrating by simulation result, this method of testing can detect the logic fault of LUT.

At this in emulation, directly output signal is immediately directed against on the IO of FPGA, is constructed such that the benefit of response analyzer is simple easily realization, it is possible to compare and directly obtain the position of the LUT broken down very easily with simulation result. But IO belongs to scarce resource in practice, so needing the response analyzer within structure, correct result being stored in inside FPGA, compares inside FPGA, after result of the comparison being compressed, use a small amount of IO to export. Although the cost in using IO reduces, but the structure of response analyzer is complicated, it is achieved difficulty of getting up, and can take substantial amounts of memory resource. Choosing comprehensively, in this confirmatory emulation, that emulate it is important that verify correctness and the effectiveness of the application oriented method of testing of chapter 2, response analyzer is not the emphasis of emulation, and the circuit that emulates employing is simple, the LUT of use is less, and the quantity of IO can meet, directly the output of LUT is drawn out on the IO of FPGA so adopting in simulations, to facilitate the carrying out of experiment.

Claims

1. using Perl language that circuit XDL level netlist is described and carry out application oriented test modifications method, its method is:

Use the Xilinx XDL instrument provided that NCD file is converted to XDL file, then the Perl language amendment XDL file being applicable to text-processing is used, finally by XDL instrument, amended XDL file is changed into NCD file, obtain last configuration file, complete circuit XDL level netlist is described to carry out application oriented test modifications;

It is characterized in that: use Perl language to circuit XDL level netlist describe carry out application oriented test modifications method particularly as follows:

2. based on the Perl language that uses described in claim 1, circuit XDL level netlist is described the interconnecting test method carrying out application oriented test modifications method, it is characterized in that:

3. according to claim 2 use Perl language that circuit XDL level netlist is described to carry out the interconnecting test method of application oriented test modifications method, it is characterised in that described interconnecting test method particularly as follows:

4. based on the Perl language that uses described in claim 1, circuit XDL level netlist is described the logic test method carrying out application oriented test modifications method, it is characterized in that:

5. circuit XDL level netlist is described the logic test method carrying out application oriented test modifications method by use Perl language according to claim 4, it is characterized in that LUT is for having n input, n is positive integer, to circuit XDL level netlist describe carry out application oriented test modifications method programmable logic resource test method particularly as follows:

Enumerator be added in source code add, particularly as follows: