CN103346773A - Level conversion circuit - Google Patents
Level conversion circuit Download PDFInfo
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- CN103346773A CN103346773A CN2013102885058A CN201310288505A CN103346773A CN 103346773 A CN103346773 A CN 103346773A CN 2013102885058 A CN2013102885058 A CN 2013102885058A CN 201310288505 A CN201310288505 A CN 201310288505A CN 103346773 A CN103346773 A CN 103346773A
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Abstract
A level conversion circuit comprises a reference voltage generation circuit, a difference circuit and a difference to single-end conversion circuit. The reference voltage generation circuit is suitable for obtaining the reference voltage according to a first target voltage and a second target voltage, wherein the reference voltage is the average value of the first target voltage and the second target voltage. The difference circuit is suitable for obtaining a first drive signal and a second drive signal according to a first input signal, a second input signal and the reference voltage. The difference to single-end conversion circuit is driven by the first drive signal and the second drive signal. The level conversion circuit can achieve conversion between different levels and has strong universality.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of level shifting circuit.
Background technology
Level shifting circuit is a kind of interface circuit very important in the integrated circuit, and its function is that a kind of supply voltage/ground voltage is changed into another kind of supply voltage/ground voltage.By level shifting circuit, signal can be transformed into another kind of power domain from a kind of power domain, make things convenient for signal in the power domain that is fit to separately, to carry out various calculation process.
For example, the high-frequency digital signal interference with high voltage amplitude is very strong, be adapted at doing the various logic computing in the low-tension supply territory, and analog signal is adapted at handling in the high voltage source territory in order to obtain high s/n ratio.Generally, the digital circuit of low pressure need with the analog circuit of high pressure between carry out communicating by letter of control signal, the low-voltage signal of digital circuit being exported by low pressure commentaries on classics high voltage level change-over circuit converts high-voltage signal to analog circuit, the high-voltage signal of analog circuit being exported by high pressure commentaries on classics low voltage level change-over circuit converts low-voltage signal to digital circuit, the former is called shift circuit on the level, and the latter is called shift circuit under the level.
In the prior art, on the common level shift circuit comprise inverter, by two high pressure NMOS pipes and the drive circuit of high voltage source power supply.When carrying out level conversion, low-voltage signal can obtain the opposite signal of two-way phase place through after the inverter drive, the signal that the two-way phase place is opposite is respectively as the driving signal of two high pressure NMOS tube grids, under the control of described driving signal, the drain electrode of high pressure NMOS pipe output namely obtains high-voltage signal through overdrive circuit.
Shift circuit has two classes under the common level: a class comprises high pressure NMOS pipe and low-voltage driving circuit, when carrying out level conversion, with the driving signal of high-voltage signal as the high pressure NMOS tube grid of being powered by low-tension supply, under the control of described driving signal, the drain electrode of high pressure NMOS pipe output namely obtains low-voltage signal through low-voltage driving circuit; Another kind of resistance, source follower and the diode of comprising realized the conversion of level by dividing potential drop, gate source voltage displacement, the diode translocation of resistance.
Yet, being subjected to the restriction of factors such as driving force deficiency, high-low pressure metal-oxide-semiconductor threshold voltage, circuit structure, level shifting circuit of the prior art can't be realized the conversion between any two absolute levels, versatility is lower.
More technical schemes about level shifting circuit can be that US2008054941, denomination of invention are Voltage Level Shifter Circuit(level shift circuit with reference to publication number) the U.S. Patent application file.
Summary of the invention
What the present invention solved is the low problem of existing level shifting circuit versatility.
For addressing the above problem, the invention provides a kind of level shifting circuit, comprising:
Generating circuit from reference voltage is suitable for obtaining reference voltage according to first target voltage and second target voltage, and described reference voltage is the mean value of described first target voltage and second target voltage, and described first target voltage is higher than described second target voltage;
Difference by described first target voltage and the power supply of described second target voltage is changeed single-end circuit, comprise the first load metal-oxide-semiconductor and the second load metal-oxide-semiconductor that the cross-coupled positive feedback connects, the first input metal-oxide-semiconductor that is connected with the described first load metal-oxide-semiconductor, the second input metal-oxide-semiconductor that is connected with the described second load metal-oxide-semiconductor; The grid of the described first input metal-oxide-semiconductor is suitable for importing first and drives signal, and the grid of the described second input metal-oxide-semiconductor is suitable for importing second and drives signal, and the threshold voltage of the described first input metal-oxide-semiconductor and the second input metal-oxide-semiconductor equates;
Difference channel, be suitable for obtaining described first according to first input signal, second input signal and described reference voltage and drive signal and the second driving signal, described first input signal and second input signal are differential signal, it is differential signal that the described first driving signal and second drives signal, the high level voltage of the described first driving signal and the difference of described reference voltage equal the difference that described reference voltage and described first drives the low level voltage of signal, and the described first driving signal is suitable for making the described first input metal-oxide-semiconductor conducting or ends.
Optionally, described generating circuit from reference voltage comprises first divider resistance, second divider resistance, the 3rd input metal-oxide-semiconductor and the first biasing metal-oxide-semiconductor; Wherein, an end of described first divider resistance is suitable for importing described first target voltage, and the other end of described first divider resistance connects an end of described second divider resistance and the grid of described the 3rd input metal-oxide-semiconductor; The other end of described second divider resistance is suitable for importing described second target voltage; The drain electrode of described the 3rd input metal-oxide-semiconductor is suitable for importing described first target voltage, and the source electrode of described the 3rd input metal-oxide-semiconductor connects the drain electrode of the described first biasing metal-oxide-semiconductor and exports the output of described reference voltage as described generating circuit from reference voltage; The grid of the described first biasing metal-oxide-semiconductor is suitable for importing first conducting voltage that makes the described first biasing metal-oxide-semiconductor saturation conduction, and the source electrode of the described first biasing metal-oxide-semiconductor is suitable for importing described second target voltage; The resistance of described first divider resistance and described second divider resistance is according to Vss1+(Vdd1-Vss1) * r2/(r1+r2)=(Vdd1+Vss1)/2+Vthn+(2*I
D* L/ μ
n* C
Ox* W)
1/2Determine that wherein, Vdd1 represents described first target voltage, Vss1 represents described second target voltage, and r1 represents the resistance of described first divider resistance, and r2 represents the resistance of described second divider resistance, and Vthn represents the threshold voltage of described the 3rd input metal-oxide-semiconductor, I
DThe drain current of representing described the 3rd input metal-oxide-semiconductor, L are represented the channel length of described the 3rd input metal-oxide-semiconductor, μ
nThe carrier mobility of representing described the 3rd input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 3rd input metal-oxide-semiconductor, W are represented the channel width of described the 3rd input metal-oxide-semiconductor.
Optionally, described generating circuit from reference voltage comprises the 3rd divider resistance, the 4th divider resistance, the second biasing metal-oxide-semiconductor and the 4th input metal-oxide-semiconductor; Wherein, an end of described the 3rd divider resistance is suitable for importing described first target voltage, and the other end of described the 3rd divider resistance connects an end of described the 4th divider resistance and the grid of described the 4th input metal-oxide-semiconductor; The other end of described the 4th divider resistance is suitable for importing described second target voltage; The grid of the described second biasing metal-oxide-semiconductor is suitable for importing second conducting voltage that makes the described second biasing metal-oxide-semiconductor saturation conduction, the source electrode of the described second biasing metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described second biasing metal-oxide-semiconductor connects the source electrode of described the 4th input metal-oxide-semiconductor and exports the output of described reference voltage as described generating circuit from reference voltage; The drain electrode of described the 4th input metal-oxide-semiconductor is suitable for importing described second target voltage; The resistance of described the 3rd divider resistance and described the 4th divider resistance is according to Vss1+(Vdd1-Vss1) * r4/(r3+r4)=(Vdd1+Vss1)/2-Vthp-(2*I
D* L/ μ
p* C
Ox* W)
1/2Determine that wherein, Vdd1 represents described first target voltage, Vss1 represents described second target voltage, and r3 represents the resistance of described the 3rd divider resistance, and r4 represents the resistance of described the 4th divider resistance, and Vthp represents the threshold voltage of described the 4th input metal-oxide-semiconductor, I
DThe drain current of representing described the 4th input metal-oxide-semiconductor, L are represented the channel length of described the 4th input metal-oxide-semiconductor, μ
pThe carrier mobility of representing described the 4th input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 4th input metal-oxide-semiconductor, W are represented the channel width of described the 4th input metal-oxide-semiconductor.
Optionally, the described first load metal-oxide-semiconductor and the described second load metal-oxide-semiconductor are the NMOS pipe, the described first input metal-oxide-semiconductor and the described second input metal-oxide-semiconductor are the PMOS pipe, the difference of the high level voltage of described first target voltage and the described first driving signal is less than the threshold voltage of the described first input metal-oxide-semiconductor, and the difference of the low level voltage of described first target voltage and the described first driving signal is greater than the threshold voltage of the described first input metal-oxide-semiconductor.
Optionally, described difference channel comprises the first constant current metal-oxide-semiconductor, the second constant current metal-oxide-semiconductor, the first common mode sample resistance, the second common mode sample resistance, first difference input metal-oxide-semiconductor, second difference input metal-oxide-semiconductor and the first tail current source metal-oxide-semiconductor; Wherein, the described first common mode sample resistance is identical with the resistance of the described second common mode sample resistance; The grid of the described first constant current metal-oxide-semiconductor connects the grid of the described second constant current metal-oxide-semiconductor and is suitable for importing the 3rd conducting voltage that makes the described first constant current metal-oxide-semiconductor and the described second constant current metal-oxide-semiconductor saturation conduction, the source electrode of the described first constant current metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described first constant current metal-oxide-semiconductor connects the drain electrode of described first difference input metal-oxide-semiconductor and exports first output of the described first driving signal as described difference channel; The source electrode of the described second constant current metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described second constant current metal-oxide-semiconductor connects the drain electrode of described second difference input metal-oxide-semiconductor and exports second output of the described second driving signal as described difference channel; One end of the described first common mode sample resistance connects the drain electrode of the described first constant current metal-oxide-semiconductor, and the other end connects an end of the described second common mode sample resistance and imports the input of described reference voltage as described difference channel; The other end of the described second common mode sample resistance connects the drain electrode of the described second constant current metal-oxide-semiconductor; The grid of described first difference input metal-oxide-semiconductor is suitable for importing described first input signal, and the source electrode of described first difference input metal-oxide-semiconductor connects the source electrode of described second difference input metal-oxide-semiconductor and the drain electrode of the described first tail current source metal-oxide-semiconductor; The grid of described second difference input metal-oxide-semiconductor is suitable for importing described second input signal; The grid of the described first tail current source metal-oxide-semiconductor is suitable for importing the 4th conducting voltage that makes the described first tail current source metal-oxide-semiconductor saturation conduction, and the source electrode of the described first tail current source metal-oxide-semiconductor is suitable for importing first supply voltage that is lower than described first target voltage.
Optionally, the described first load metal-oxide-semiconductor and the described second load metal-oxide-semiconductor are the PMOS pipe, the described first input metal-oxide-semiconductor and the described second input metal-oxide-semiconductor are the NMOS pipe, the high level voltage of the described first driving signal and the difference of described second target voltage are greater than the threshold voltage of the described first input metal-oxide-semiconductor, and the low level voltage of the described first driving signal and the difference of described second target voltage are less than the threshold voltage of the described first input metal-oxide-semiconductor.
Optionally, described difference channel comprises the second tail current source metal-oxide-semiconductor, the 3rd difference input metal-oxide-semiconductor, the 4th difference input metal-oxide-semiconductor, the 3rd common mode sample resistance, the 4th common mode sample resistance, the 3rd constant current metal-oxide-semiconductor and the 4th constant current metal-oxide-semiconductor; Wherein, described the 3rd common mode sample resistance is identical with the resistance of described the 4th common mode sample resistance, the grid of the described second tail current source metal-oxide-semiconductor is suitable for importing the 5th conducting voltage that makes the described second tail current source metal-oxide-semiconductor saturation conduction, the source electrode of the described second tail current source metal-oxide-semiconductor is suitable for importing the second source voltage that is higher than described second target voltage, and the drain electrode of the described second tail current source metal-oxide-semiconductor connects the source electrode of described the 3rd difference input metal-oxide-semiconductor and the source electrode of described the 4th difference input metal-oxide-semiconductor; The grid of described the 3rd difference input metal-oxide-semiconductor is suitable for importing described first input signal, and the drain electrode of described the 3rd difference input metal-oxide-semiconductor connects the drain electrode of described the 3rd constant current metal-oxide-semiconductor and exports first output of the described first driving signal as described difference channel; The grid of described the 4th difference input metal-oxide-semiconductor is suitable for importing described second input signal, and the drain electrode of described the 4th difference input metal-oxide-semiconductor connects the drain electrode of described the 4th constant current metal-oxide-semiconductor and exports second output of the described second driving signal as described difference channel; One end of described the 3rd common mode sample resistance connects the drain electrode of described the 3rd difference input metal-oxide-semiconductor, and the other end connects an end of described the 4th common mode sample resistance and imports the input of described reference voltage as described difference channel; The other end of described the 4th common mode sample resistance connects the drain electrode of described the 4th difference input metal-oxide-semiconductor; The grid of described the 3rd constant current metal-oxide-semiconductor connects the grid of described the 4th constant current metal-oxide-semiconductor and is suitable for importing the 6th conducting voltage that makes described the 3rd constant current metal-oxide-semiconductor and described the 4th constant current metal-oxide-semiconductor saturation conduction, and the source electrode of described the 3rd constant current metal-oxide-semiconductor is suitable for importing described second target voltage; The source electrode of described the 4th constant current metal-oxide-semiconductor is suitable for importing described second target voltage.
Optionally, described level shifting circuit comprises that also the input of described CMOS inverter connects the link of the described second load metal-oxide-semiconductor and the described second input metal-oxide-semiconductor by the CMOS inverter of described first target voltage and the power supply of described second target voltage.
Compared with prior art, technical scheme of the present invention has the following advantages:
Producing magnitude of voltage by generating circuit from reference voltage is the reference voltage of the mean value of first target voltage and second target voltage, and with described reference voltage input difference circuit.Under the control of first input signal and second input signal, utilize two common mode sample resistances that resistance equates in the described difference channel, the first driving signal of forcing to make described difference channel output follow described reference voltage variation and second drives signal.It is differential signal that the described first driving signal and second drives signal, and the high level voltage of the described first driving signal and the difference of described reference voltage equal the difference that described reference voltage and described first drives the low level voltage of signal.
When described first target voltage and the variation of described second target voltage, described reference voltage changes thereupon, thereby make described first high-low level that drives signal and the described second driving signal follow described first target voltage and the variation of described second target voltage, can drive by the difference of described first target voltage and the power supply of described second target voltage and change single-end circuit, realize the conversion between the varying level, therefore, level shifting circuit provided by the invention has very strong versatility.
Description of drawings
Fig. 1 is the structural representation of the level shifting circuit of embodiment of the present invention;
Fig. 2 is a kind of circuit diagram of the generating circuit from reference voltage of the embodiment of the invention 1;
Fig. 3 is the another kind of circuit diagram of the generating circuit from reference voltage of the embodiment of the invention 1;
Fig. 4 is the partial circuit figure of the level shifting circuit of the embodiment of the invention 1;
Fig. 5 is the signal waveforms in level shifting circuit when work of the embodiment of the invention 1;
Fig. 6 is the partial circuit figure of the level shifting circuit of the embodiment of the invention 2.
Embodiment
Just as described in the background art, existing level shifting circuit is owing to the conversion that can not realize between any two absolute levels, and the versatility of level shifting circuit is lower.The inventor provides a kind of level shifting circuit of highly versatile through research.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing specific embodiments of the invention are described in detail.
Fig. 1 is the structural representation of the level shifting circuit of embodiment of the present invention.With reference to figure 1, described level shifting circuit comprises generating circuit from reference voltage 11, difference channel 12 and difference commentaries on classics single-end circuit 13.
Described generating circuit from reference voltage 11 is suitable for obtaining reference voltage Vcm according to the first target voltage Vdd1 and the second target voltage Vss1, described reference voltage Vcm is the mean value of the described first target voltage Vdd1 and the described second target voltage Vss1, be Vcm=(Vdd1+Vss1)/2, the described first target voltage Vdd1 is higher than the described second target voltage Vss1.
The described first target voltage Vdd1 and the described second target voltage Vss1 are respectively high level voltage and the low level voltage of the signal that needs acquisition, under the transistorized withstand voltage condition, the described first target voltage Vdd1 and the described second target voltage Vss1 can arrange arbitrarily according to the actual requirements in satisfying circuit.
Described difference is changeed single-end circuit 13 by the described first target voltage Vdd1 and described second target voltage Vss1 power supply, comprises the first load metal-oxide-semiconductor, the second load metal-oxide-semiconductor, the first input metal-oxide-semiconductor and the second input metal-oxide-semiconductor (Fig. 1 is not shown).
The described first load metal-oxide-semiconductor becomes the cross-coupled positive feedback to be connected with the described second load metal-oxide-semiconductor, and the described first input metal-oxide-semiconductor is connected with the described first load metal-oxide-semiconductor, and the described second input metal-oxide-semiconductor is connected with the described second load metal-oxide-semiconductor.The grid of the described first input metal-oxide-semiconductor is suitable for importing first and drives signal Von, and the grid of the described second input metal-oxide-semiconductor is suitable for importing second and drives signal Vop, and the threshold voltage of the described first input metal-oxide-semiconductor and the second input metal-oxide-semiconductor equates.
Those skilled in the art know, level shifting circuit comprises that with low transition be shift circuit and high level is converted to shift circuit under the low level level on the level of high level, therefore, the transistor that constitutes described difference commentaries on classics single-end circuit 13 can be the PMOS transistor, also can be nmos pass transistor, the concrete annexation between each transistor is referring to the detailed description in following examples.
Described difference channel 12 is suitable for obtaining the described first driving signal Von and the described second driving signal Vop according to the first input signal Vin1, the second input signal Vin2 and described reference voltage Vcm.The described first input signal Vin1 and the described second input signal Vin2 are differential signal, and it also is differential signal that the described first driving signal Von and described second drives signal Vop, and differential signal refers to equal and opposite in direction, opposite polarity a pair of signal.
The described first input signal Vin1 or the described second input signal Vin2 signal for changing, namely by described level shifting circuit the high level voltage of the described first input signal Vin1 is converted to the described first target voltage Vdd1, the low level voltage of the described first input signal Vin1 is converted to the described second target voltage Vss1; Perhaps, by described level shifting circuit the high level voltage of the described second input signal Vin2 is converted to the described first target voltage Vdd1, the low level voltage of the described second input signal Vin2 is converted to the described second target voltage Vss1.
If the described first input signal Vin1 is for needing the signal of conversion, the described second input signal Vin2 can be by the described first input signal Vin1 being carried out anti-phase acquisition; If the described second input signal Vin2 is for needing the signal of conversion, the described first input signal Vin1 can be by the described second input signal Vin2 is carried out anti-phase acquisition.
Because the effect of described difference channel 12, the high level voltage of the described first driving signal Von and the difference of described reference voltage Vcm equal the difference that described reference voltage Vcm and described second drives the low level voltage of signal Vop, and namely described reference voltage Vcm is the high level voltage of the described first driving signal Von and the average of low level voltage.It is differential signal that the described first driving signal Von and described second drives signal Vop, and therefore, described reference voltage Vcm also is the high level voltage of the described second driving signal Vop and the average of low level voltage.
In the technical program, the described first driving signal Von is suitable for making the described first input metal-oxide-semiconductor conducting or ends, because it is differential signal that the described first driving signal Von and described second drives signal Vop, and the threshold voltage of the described first input metal-oxide-semiconductor and the described second input metal-oxide-semiconductor equates, therefore, when the described first driving signal Von made described first to import the metal-oxide-semiconductor conducting, described second drives signal Vop ended the described second input metal-oxide-semiconductor; When the described first driving signal Von ended the described first input metal-oxide-semiconductor, described second drives signal Vop made the described second input metal-oxide-semiconductor conducting.
When the described first target voltage Vdd1 and described second target voltage Vss1 variation, described reference voltage Vcm changes thereupon, thereby make described first level and the amplitude of oscillation that drives signal Von and the described second driving signal Vop follow the described first target voltage Vdd1 and described second target voltage Vss1 variation, can drive by the difference of the described first target voltage Vdd1 and described second target voltage Vss1 power supply changes single-end circuit 13, realizes the conversion between the varying level.
Level shifting circuit comprises on the level shift circuit under the shift circuit and level, and structure and operation principle for understanding level shifting circuit provided by the invention better are described in detail below in conjunction with accompanying drawing and specific embodiment.
Embodiment 1
In the present embodiment, be that shift circuit is that example describes on the level of high level to realize low transition.Fig. 2 is a kind of circuit diagram of present embodiment generating circuit from reference voltage.With reference to figure 2, described generating circuit from reference voltage comprises the first divider resistance R1, the second divider resistance R2, the 3rd input metal-oxide-semiconductor N1 and the first biasing metal-oxide-semiconductor N2, and described the 3rd input metal-oxide-semiconductor N1 and the described first biasing metal-oxide-semiconductor N2 form source follower.
The end of the described first divider resistance R1 is suitable for importing the described first target voltage Vdd1, and the other end of the described first divider resistance R1 connects the end of the described second divider resistance R2 and the grid of described the 3rd input metal-oxide-semiconductor N1.The other end of the described second divider resistance R2 is suitable for importing the described second target voltage Vss1.
The drain electrode of described the 3rd input metal-oxide-semiconductor N1 is suitable for importing the described first target voltage Vdd1, and the source electrode of described the 3rd input metal-oxide-semiconductor N1 connects the drain electrode of the described first biasing metal-oxide-semiconductor N2 and exports the output of described reference voltage Vcm as described generating circuit from reference voltage.
The grid of the described first biasing metal-oxide-semiconductor N2 is suitable for importing the first conducting voltage V1 that makes the described first biasing metal-oxide-semiconductor N2 saturation conduction, and the source electrode of the described first biasing metal-oxide-semiconductor N2 is suitable for importing the described second target voltage Vss1.
The described first conducting voltage V1 is the voltage that makes the described first biasing metal-oxide-semiconductor N2 saturation conduction, and concrete magnitude of voltage can arrange according to the threshold voltage of the described first biasing metal-oxide-semiconductor N2.
Be the reference voltage Vcm of the mean value of the described first target voltage Vdd1 and the described second target voltage Vss1 for making described generating circuit from reference voltage output voltage values, the resistance of the described first divider resistance R1 and the described second divider resistance R2 is according to Vss1+(Vdd1-Vss1) * r2/(r1+r2)=(Vdd1+Vss1)/2+Vthn+(2*I
D* L/ μ
n* C
Ox* W)
1/2Determine that wherein, r1 represents the resistance of the described first divider resistance R1, r2 represents the resistance of the described second divider resistance R1, and Vthn represents the threshold voltage of described the 3rd input metal-oxide-semiconductor N1, I
DThe drain current of representing described the 3rd input metal-oxide-semiconductor, L are represented the channel length of described the 3rd input metal-oxide-semiconductor, μ
nThe carrier mobility of representing described the 3rd input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 3rd input metal-oxide-semiconductor, W are represented the channel width of described the 3rd input metal-oxide-semiconductor.
Source follower in the described generating circuit from reference voltage also can adopt the PMOS pipe to realize, with reference to the another kind of circuit diagram of present embodiment generating circuit from reference voltage shown in Figure 3.Described generating circuit from reference voltage comprises the 3rd divider resistance R3, the 4th divider resistance R4, the second biasing metal-oxide-semiconductor P1 and the 4th input metal-oxide-semiconductor P2, and the concrete annexation between each device can not repeat them here with reference to figure 3.
Similar with the description to Fig. 2, the described second conducting voltage V2 is the voltage that makes the described second biasing metal-oxide-semiconductor P1 saturation conduction, concrete magnitude of voltage can arrange according to the threshold voltage of the described second biasing metal-oxide-semiconductor P1, and the resistance of described the 3rd divider resistance R3 and described the 4th divider resistance R4 is according to Vss1+(Vdd1-Vss1) * r4/(r3+r4)=(Vdd1+Vss1)/2-Vthp-(2*I
D* L/ μ
p* C
Ox* W)
1/2Determine that wherein, r3 represents the resistance of described the 3rd divider resistance R3, r4 represents the resistance of described the 4th divider resistance R4, and Vthp represents the threshold voltage of described the 4th input metal-oxide-semiconductor P2, I
DThe drain current of representing described the 4th input metal-oxide-semiconductor, L are represented the channel length of described the 4th input metal-oxide-semiconductor, μ
pThe carrier mobility of representing described the 4th input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 4th input metal-oxide-semiconductor, W are represented the channel width of described the 4th input metal-oxide-semiconductor.
Need to prove, for increasing the driving force of described reference voltage Vcm, Fig. 2 and generating circuit from reference voltage shown in Figure 3 have included the source follower of being made up of input metal-oxide-semiconductor and biasing metal-oxide-semiconductor, in other embodiments, described generating circuit from reference voltage also can not comprise source follower.Those skilled in the art also can adopt other forms of circuit according to the spirit of present embodiment, as long as can realize producing the reference voltage Vcm that magnitude of voltage is the mean value of the described first target voltage Vdd1 and the described second target voltage Vss2.Therefore, the generating circuit from reference voltage in the present embodiment should be as limitation of the present invention.
With reference to figure 4, the level shifting circuit of the embodiment of the invention also comprises difference channel 41 and difference commentaries on classics single-end circuit 42.
Described difference channel 41 comprises the first constant current metal-oxide-semiconductor P3, the second constant current metal-oxide-semiconductor P4, the first common mode sample resistance R5, the second common mode sample resistance R6, first difference input metal-oxide-semiconductor N3, second difference input metal-oxide-semiconductor N4 and the first tail current source metal-oxide-semiconductor N5.
Wherein, the described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4 are the PMOS pipe, described first difference input metal-oxide-semiconductor N3, described second difference input metal-oxide-semiconductor N4 and the described first tail current source metal-oxide-semiconductor N5 are the NMOS pipe, and the described first common mode sample resistance R5 is identical with the resistance of the described second common mode sample resistance R6.
The grid of the described first constant current metal-oxide-semiconductor P3 connects the grid of the described second constant current metal-oxide-semiconductor P4 and is suitable for importing the 3rd conducting voltage V3 that makes the described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4 saturation conduction, the source electrode of the described first constant current metal-oxide-semiconductor P3 is suitable for importing the described first target voltage Vdd1, and the drain electrode of the described first constant current metal-oxide-semiconductor P3 connects the drain electrode of described first difference input metal-oxide-semiconductor N3 and drives first output of signal Von as described difference channel 41 outputs described first.
The source electrode of the described second constant current metal-oxide-semiconductor P4 is suitable for importing the described first target voltage Vdd1, and the drain electrode of the described second constant current metal-oxide-semiconductor P4 connects the drain electrode of described second difference input metal-oxide-semiconductor N4 and drives second output of signal Vop as described difference channel 41 outputs described second.
The described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4 are current source loads, when circuit working, increase the impedance of first output and second output of described difference channel 41, make it become high-impedance node, swing up and down centered by described reference voltage Vcm thereby make the described first driving signal Von and described second drive signal Vop.
The end of the described first common mode sample resistance R5 connects the drain electrode of the described first constant current metal-oxide-semiconductor P3, and the other end connects the end of the described second common mode sample resistance R6 and imports the input of described reference voltage Vcm as described difference channel 41; The other end of the described second common mode sample resistance R6 connects the drain electrode of the described second constant current metal-oxide-semiconductor P4.
The grid of described first difference input metal-oxide-semiconductor N3 is suitable for importing the first input signal Vin1, and the source electrode of described first difference input metal-oxide-semiconductor N3 connects the source electrode of described second difference input metal-oxide-semiconductor N4 and the drain electrode of the described first tail current source metal-oxide-semiconductor N5.The grid of described second difference input metal-oxide-semiconductor N4 is suitable for importing the second input signal Vin2.
The grid of the described first tail current source metal-oxide-semiconductor N5 is suitable for importing the 4th conducting voltage V4 that makes the described first tail current source metal-oxide-semiconductor N5 saturation conduction, and the source electrode of the described first tail current source metal-oxide-semiconductor N5 is suitable for importing the first supply voltage Vss2 that is lower than the described first target voltage Vdd1.In the present embodiment, the described first supply voltage Vss2 is ground voltage.
Described the 4th conducting voltage V4 is the voltage that makes the described first tail current source metal-oxide-semiconductor N5 saturation conduction, and concrete magnitude of voltage can arrange according to the threshold voltage of the described first tail current source metal-oxide-semiconductor N5.The described first tail current source metal-oxide-semiconductor N5 can improve the common-mode rejection ratio of described differential amplifier 41, simultaneously, provides stable quiescent current, guarantees that late-class circuit can steady operation.
Described difference is changeed single-end circuit 42 and is comprised the first load metal-oxide-semiconductor N6, the second load metal-oxide-semiconductor N7, the first input metal-oxide-semiconductor P5 and the second input metal-oxide-semiconductor P6.
Wherein, the described first load metal-oxide-semiconductor N6 and the described second load metal-oxide-semiconductor N7 are the NMOS pipe, and the described first input metal-oxide-semiconductor P5 and the described second input metal-oxide-semiconductor P6 are the PMOS pipe.
The grid of the described first input metal-oxide-semiconductor P5 is suitable for importing described first and drives signal Von, the source electrode of the described first input metal-oxide-semiconductor P5 is suitable for importing the described first target voltage Vdd1, and the drain electrode of the described first input metal-oxide-semiconductor P5 connects the drain electrode of the described first load metal-oxide-semiconductor N6 and the grid of the described second load metal-oxide-semiconductor N7.
The grid of the described second input metal-oxide-semiconductor P6 is suitable for importing described second and drives signal Vop, the source electrode of the described second input metal-oxide-semiconductor P6 is suitable for importing the described first target voltage Vdd1, the drain electrode of the described second input metal-oxide-semiconductor P6 connects the drain electrode of the described second load metal-oxide-semiconductor N7 and the grid of the described first load metal-oxide-semiconductor N6, and the drain electrode of the described second input metal-oxide-semiconductor P6 is as the output that produces output signal Vout.
The source electrode of the source electrode of the described first load metal-oxide-semiconductor N6 and the described second load metal-oxide-semiconductor N7 is suitable for importing the described second target voltage Vss1.
In order to strengthen the driving force of described level shifting circuit, in the present embodiment, described level shifting circuit also comprises the CMOS inverter 43 by the described first target voltage Vdd1 and described second target voltage Vss2 power supply.
Described CMOS inverter 43 comprises that first drives PMOS pipe P7 and the first driving N metal-oxide-semiconductor N8.Described first grid that drives PMOS pipe P7 is connected and imports as described CMOS inverter 43 input of described output signal Vout with the grid of the described first driving N metal-oxide-semiconductor N8, described first source electrode that drives PMOS pipe P7 is suitable for importing the described first target voltage Vdd1, and described first drain electrode that drives PMOS pipe P7 is connected the output as the inversion signal Vout1 that produces described output signal Vout with the drain electrode of the described first driving N metal-oxide-semiconductor N8.The source electrode of the described first driving N metal-oxide-semiconductor N8 is suitable for importing the described second target voltage Vss1.
Be the principle of level switching circuit that the embodiment of the invention is described better, the signal waveforms when Fig. 5 has provided described level switching circuit work.
With reference to figure 5, the described first input signal Vin1 and the described second input signal Vin2 are differential signal, and the described second input signal Vin2 can be advanced that inverter is anti-phase to be obtained by the described first input signal Vin1.In the present embodiment, the high level voltage of the described first input signal Vin1 is second source voltage Vdd2, and low level voltage is the described first supply voltage Vss2, and described second source voltage Vdd2 is not higher than the described first target voltage Vdd1.
When the described first input signal Vin1 be high level signal, when the described second input signal Vin2 is low level signal, with reference to figure 4, described first difference input metal-oxide-semiconductor N3 conducting, the drain electrode of the described first constant current metal-oxide-semiconductor P3 is pulled to electronegative potential; Described second difference input metal-oxide-semiconductor N4 ends, and the drain electrode of the described second constant current metal-oxide-semiconductor P4 is pulled to high potential.Therefore, the described first driving signal Von is low level signal, and the described second driving signal Vop is high level signal.
When the described first input signal Vin1 be low level signal, when the described second input signal Vin2 is high level signal, described first difference input metal-oxide-semiconductor N3 ends, the drain electrode of the described first constant current metal-oxide-semiconductor P3 is pulled to high potential; Described second difference input metal-oxide-semiconductor N4 conducting, the drain electrode of the described second constant current metal-oxide-semiconductor P4 is pulled to electronegative potential.Therefore, the described first driving signal Von is high level signal, and the described second driving signal Vop is low level signal.
Because described reference voltage Vcm is by the described first common mode sample resistance R5 and the described second common mode sample resistance R6, be added in first output of the described first driving signal Von of described difference channel 41 outputs and export described second and drive between second output of signal Vop, therefore, there is relation: Von-Vcm=Vcm-Vop, i.e. 2Vcm=Von+Vop.With reference to figure 5, the described first driving signal Von and described second drives signal Vop point centered by described reference voltage and swings up and down.
And, described reference voltage Vcm is the mean value of the described first target voltage Vdd1 and the described second target voltage Vss1, the described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4 work in the saturation region, increased the impedance of first output and second output of described difference channel 41, thereby making the described first driving signal Von and described second drive signal Vop swings up and down centered by described reference voltage Vcm, therefore, import the drop-down effect of metal-oxide-semiconductor N4 by drawing effect and described first difference input metal-oxide-semiconductor N3 and described second difference on the described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4, first of described difference channel 41 outputs drive the high level voltage of signal Von and the described second driving signal Vop close to the described first target voltage Vdd1, and low level voltage is close to the described second target voltage Vss1.
Continuation is with reference to figure 4, as mentioned above, first of described difference channel 41 outputs drive signal Von and described second and drive the high level voltage of signal Vop close to the described first target voltage Vdd1, therefore, the difference of the high level voltage of the described first target voltage Vdd1 and the described first driving signal Von is less than the threshold voltage of the described first input metal-oxide-semiconductor P5, and the difference of the low level voltage of the described first target voltage Vdd1 and the described first driving signal Von is greater than the threshold voltage of the described first input metal-oxide-semiconductor P5.
The threshold voltage of the described second input metal-oxide-semiconductor P6 equates with the threshold voltage of the described first input metal-oxide-semiconductor P5, therefore, the difference of the high level voltage of the described first target voltage Vdd1 and the described first driving signal Von is less than the threshold voltage of the described second input metal-oxide-semiconductor P6, and the difference of the low level voltage of the described first target voltage Vdd1 and the described first driving signal Von is greater than the threshold voltage of the described second input metal-oxide-semiconductor P6.
To drive signal Von be that low level signal, described second is when driving signal Vop and being high level signal when described first, the described second input metal-oxide-semiconductor P6 ends, the described first input metal-oxide-semiconductor P5 conducting, make the grid of the described second load metal-oxide-semiconductor N7 be pulled to high potential, the described second load metal-oxide-semiconductor N7 conducting, described output signal Vout is low level signal, and magnitude of voltage is the described second target voltage Vss1.Simultaneously, described output signal Vout is that low level signal turn-offs the described first load metal-oxide-semiconductor N6, forms positive feedback.
To drive signal Von be that high level signal, described second is when driving signal Vop and being low level signal when described first, the described first input metal-oxide-semiconductor P5 ends, the described second input metal-oxide-semiconductor P6 conducting, described output signal Vout is high level signal, magnitude of voltage is the described first target voltage Vdd1.Simultaneously, described output signal Vout is that high level signal makes the described first load metal-oxide-semiconductor N6 conducting, and the described second load metal-oxide-semiconductor N7 ends, and forms positive feedback.
Through the effect of described difference commentaries on classics single-end circuit 42, the high level voltage of the output signal Vout of acquisition is the described first target voltage Vdd1, and low level voltage is the described second target voltage Vss1, and shorten the rising of signal/fall time.
Further, described CMOS inverter 43 can strengthen the driving force of described output signal Vout, and the inversion signal Vout1(waveform that produces described output signal Vout is not shown).
In the present embodiment, shift circuit is that example describes under the low level level to realize high level is converted to.But the generating circuit from reference voltage reference example 1 of present embodiment does not repeat them here.With reference to figure 6, the level shifting circuit of the embodiment of the invention also comprises difference channel 61, difference commentaries on classics single-end circuit 62 and CMOS inverter 63.
Particularly, described difference channel 61 comprises the second tail current source metal-oxide-semiconductor P8, the 3rd difference input metal-oxide-semiconductor P9, the 4th difference input metal-oxide-semiconductor P10, the 3rd common mode sample resistance R7, the 4th common mode sample resistance R8, the 3rd constant current metal-oxide-semiconductor N9 and the 4th constant current metal-oxide-semiconductor N10.
Wherein, the described second tail current source metal-oxide-semiconductor P8, the 3rd difference input metal-oxide-semiconductor P9 and the 4th difference input metal-oxide-semiconductor P10 are the PMOS pipe, the 3rd constant current metal-oxide-semiconductor N9 and the 4th constant current metal-oxide-semiconductor N10 are the NMOS pipe, and the 3rd common mode sample resistance R7 is identical with the resistance of the 4th common mode sample resistance R8.
The grid of the described second tail current source metal-oxide-semiconductor P8 is suitable for importing the 5th conducting voltage V5, described the 5th conducting voltage V5 is the voltage that makes the described second tail current source metal-oxide-semiconductor P8 saturation conduction, and concrete magnitude of voltage can arrange according to the threshold voltage of the described second tail current source metal-oxide-semiconductor P8.
The grid of described the 3rd constant current metal-oxide-semiconductor N9 and described the 4th constant current metal-oxide-semiconductor N10 is suitable for importing the 6th conducting voltage V6, described the 6th conducting voltage V6 is the voltage that makes described the 3rd constant current metal-oxide-semiconductor N9 and described the 4th constant current metal-oxide-semiconductor N10 saturation conduction, and concrete magnitude of voltage can arrange according to the threshold voltage of described the 3rd constant current metal-oxide-semiconductor N9 and described the 4th constant current metal-oxide-semiconductor N10.
Described difference is changeed single-end circuit 62 and is comprised the 3rd load metal-oxide-semiconductor P11, the 4th load metal-oxide-semiconductor P12, the 5th input metal-oxide-semiconductor N11 and the 6th input metal-oxide-semiconductor N12.Wherein, described the 5th input metal-oxide-semiconductor N11 and described the 6th input metal-oxide-semiconductor N12 are the NMOS pipe, and described the 3rd load metal-oxide-semiconductor P11 and described the 4th load metal-oxide-semiconductor P12 are the PMOS pipe.
Described CMOS inverter 63 comprises that second drives PMOS pipe P13 and the second driving N metal-oxide-semiconductor N13.
Described difference channel 61, described difference are changeed circuit structure and the description of circuit function reference example 1 and the description of Fig. 6 of single-end circuit 62 and described CMOS inverter 63, do not repeat them here.
In the present embodiment, the high level voltage of the described first input signal Vin1 is second source voltage Vdd2, and low level voltage is the described first supply voltage Vss2, and described second source voltage Vdd2 is not less than the described first target voltage Vdd1.
Similar to Example 1, first of described difference channel 61 outputs drive signal Von and described second and drive the high level voltage of signal Vop close to the described first target voltage Vdd1, therefore, the high level voltage of the described first driving signal Von and the difference of the described second target voltage Vss1 are greater than the threshold voltage of described the 5th input metal-oxide-semiconductor N11, and the low level voltage of the described first driving signal Von and the difference of the described second target voltage Vss1 are less than the threshold voltage of described the 5th input metal-oxide-semiconductor N11.
The threshold voltage of described the 6th input metal-oxide-semiconductor N12 equates with the threshold voltage of described the 5th input metal-oxide-semiconductor N11, therefore, the high level voltage of the described first driving signal Von and the difference of the described second target voltage Vss1 are greater than the threshold voltage of described the 6th input metal-oxide-semiconductor N12, and the low level voltage of the described first driving signal Von and the difference of the described second target voltage Vss1 are less than the threshold voltage of described the 6th input metal-oxide-semiconductor N12.
The working signal waveform of the level shifting circuit of embodiment 2 can be with reference to shown in Figure 5, and concrete operation principle is similar to Example 1, does not repeat them here.
In sum, level shifting circuit provided by the invention, by the equal common mode sample resistance of two resistance values, be that the reference voltage of the average of first target voltage and second target voltage is added in difference channel output first and drives first output of signal and export second and drive between second output of signal with magnitude of voltage, make described first to drive signal and described second and drive signal point centered by described reference voltage and swing up and down.And described first high level voltage that drives signal and the described second driving signal is close to described first target voltage, and low level voltage is close to described second target voltage.
Therefore, when described first target voltage and the variation of described second target voltage, described reference voltage changes thereupon, thereby make described first high-low level that drives signal and the described second driving signal follow described first target voltage and the variation of described second target voltage, can drive by the difference of described first target voltage and the power supply of described second target voltage and change single-end circuit, realize the conversion between the varying level, improved the versatility of level shifting circuit.
Though the present invention discloses as above, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. a level shifting circuit is characterized in that, comprising:
Generating circuit from reference voltage is suitable for obtaining reference voltage according to first target voltage and second target voltage, and described reference voltage is the mean value of described first target voltage and second target voltage, and described first target voltage is higher than described second target voltage;
Difference by described first target voltage and the power supply of described second target voltage is changeed single-end circuit, comprise the first load metal-oxide-semiconductor and the second load metal-oxide-semiconductor that the cross-coupled positive feedback connects, the first input metal-oxide-semiconductor that is connected with the described first load metal-oxide-semiconductor, the second input metal-oxide-semiconductor that is connected with the described second load metal-oxide-semiconductor; The grid of the described first input metal-oxide-semiconductor is suitable for importing first and drives signal, and the grid of the described second input metal-oxide-semiconductor is suitable for importing second and drives signal, and the threshold voltage of the described first input metal-oxide-semiconductor and the second input metal-oxide-semiconductor equates;
Difference channel, be suitable for obtaining described first according to first input signal, second input signal and described reference voltage and drive signal and the second driving signal, described first input signal and second input signal are differential signal, it is differential signal that the described first driving signal and second drives signal, the high level voltage of the described first driving signal and the difference of described reference voltage equal the difference that described reference voltage and described first drives the low level voltage of signal, and the described first driving signal is suitable for making the described first input metal-oxide-semiconductor conducting or ends.
2. level shifting circuit according to claim 1 is characterized in that, described generating circuit from reference voltage comprises first divider resistance, second divider resistance, the 3rd input metal-oxide-semiconductor and the first biasing metal-oxide-semiconductor; Wherein, an end of described first divider resistance is suitable for importing described first target voltage, and the other end of described first divider resistance connects an end of described second divider resistance and the grid of described the 3rd input metal-oxide-semiconductor; The other end of described second divider resistance is suitable for importing described second target voltage; The drain electrode of described the 3rd input metal-oxide-semiconductor is suitable for importing described first target voltage, and the source electrode of described the 3rd input metal-oxide-semiconductor connects the drain electrode of the described first biasing metal-oxide-semiconductor and exports the output of described reference voltage as described generating circuit from reference voltage; The grid of the described first biasing metal-oxide-semiconductor is suitable for importing first conducting voltage that makes the described first biasing metal-oxide-semiconductor saturation conduction, and the source electrode of the described first biasing metal-oxide-semiconductor is suitable for importing described second target voltage; The resistance of described first divider resistance and described second divider resistance is according to Vss1+(Vdd1-Vss1) * r2/(r1+r2)=(Vdd1+Vss1)/2+Vthn+(2*I
D* L/ μ
n* C
Ox* W)
1/2Determine that wherein, Vdd1 represents described first target voltage, Vss1 represents described second target voltage, and r1 represents the resistance of described first divider resistance, and r2 represents the resistance of described second divider resistance, and Vthn represents the threshold voltage of described the 3rd input metal-oxide-semiconductor, I
DThe drain current of representing described the 3rd input metal-oxide-semiconductor, L are represented the channel length of described the 3rd input metal-oxide-semiconductor, μ
nThe carrier mobility of representing described the 3rd input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 3rd input metal-oxide-semiconductor, W are represented the channel width of described the 3rd input metal-oxide-semiconductor.
3. level shifting circuit according to claim 1 is characterized in that, described generating circuit from reference voltage comprises the 3rd divider resistance, the 4th divider resistance, the second biasing metal-oxide-semiconductor and the 4th input metal-oxide-semiconductor; Wherein, an end of described the 3rd divider resistance is suitable for importing described first target voltage, and the other end of described the 3rd divider resistance connects an end of described the 4th divider resistance and the grid of described the 4th input metal-oxide-semiconductor; The other end of described the 4th divider resistance is suitable for importing described second target voltage; The grid of the described second biasing metal-oxide-semiconductor is suitable for importing second conducting voltage that makes the described second biasing metal-oxide-semiconductor saturation conduction, the source electrode of the described second biasing metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described second biasing metal-oxide-semiconductor connects the source electrode of described the 4th input metal-oxide-semiconductor and exports the output of described reference voltage as described generating circuit from reference voltage; The drain electrode of described the 4th input metal-oxide-semiconductor is suitable for importing described second target voltage; The resistance of described the 3rd divider resistance and described the 4th divider resistance is according to Vss1+(Vdd1-Vss1) * r4/(r3+r4)=(Vdd1+Vss1)/2-Vthp-(2*I
D* L/ μ
p* C
Ox* W)
1/2Determine that wherein, Vdd1 represents described first target voltage, Vss1 represents described second target voltage, and r3 represents the resistance of described the 3rd divider resistance, and r4 represents the resistance of described the 4th divider resistance, and Vthp represents the threshold voltage of described the 4th input metal-oxide-semiconductor, I
DThe drain current of representing described the 4th input metal-oxide-semiconductor, L are represented the channel length of described the 4th input metal-oxide-semiconductor, μ
pThe carrier mobility of representing described the 4th input metal-oxide-semiconductor, C
OxThe grid unit are oxide layer electric capacity of representing described the 4th input metal-oxide-semiconductor, W are represented the channel width of described the 4th input metal-oxide-semiconductor.
4. level shifting circuit according to claim 1, it is characterized in that, the described first load metal-oxide-semiconductor and the described second load metal-oxide-semiconductor are the NMOS pipe, the described first input metal-oxide-semiconductor and the described second input metal-oxide-semiconductor are the PMOS pipe, the difference of the high level voltage of described first target voltage and the described first driving signal is less than the threshold voltage of the described first input metal-oxide-semiconductor, and the difference of the low level voltage of described first target voltage and the described first driving signal is greater than the threshold voltage of the described first input metal-oxide-semiconductor.
5. level shifting circuit according to claim 4, it is characterized in that described difference channel comprises the first constant current metal-oxide-semiconductor, the second constant current metal-oxide-semiconductor, the first common mode sample resistance, the second common mode sample resistance, first difference input metal-oxide-semiconductor, second difference input metal-oxide-semiconductor and the first tail current source metal-oxide-semiconductor; Wherein, the described first common mode sample resistance is identical with the resistance of the described second common mode sample resistance; The grid of the described first constant current metal-oxide-semiconductor connects the grid of the described second constant current metal-oxide-semiconductor and is suitable for importing the 3rd conducting voltage that makes the described first constant current metal-oxide-semiconductor and the described second constant current metal-oxide-semiconductor saturation conduction, the source electrode of the described first constant current metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described first constant current metal-oxide-semiconductor connects the drain electrode of described first difference input metal-oxide-semiconductor and exports first output of the described first driving signal as described difference channel; The source electrode of the described second constant current metal-oxide-semiconductor is suitable for importing described first target voltage, and the drain electrode of the described second constant current metal-oxide-semiconductor connects the drain electrode of described second difference input metal-oxide-semiconductor and exports second output of the described second driving signal as described difference channel; One end of the described first common mode sample resistance connects the drain electrode of the described first constant current metal-oxide-semiconductor, and the other end connects an end of the described second common mode sample resistance and imports the input of described reference voltage as described difference channel; The other end of the described second common mode sample resistance connects the drain electrode of the described second constant current metal-oxide-semiconductor; The grid of described first difference input metal-oxide-semiconductor is suitable for importing described first input signal, and the source electrode of described first difference input metal-oxide-semiconductor connects the source electrode of described second difference input metal-oxide-semiconductor and the drain electrode of the described first tail current source metal-oxide-semiconductor; The grid of described second difference input metal-oxide-semiconductor is suitable for importing described second input signal; The grid of the described first tail current source metal-oxide-semiconductor is suitable for importing the 4th conducting voltage that makes the described first tail current source metal-oxide-semiconductor saturation conduction, and the source electrode of the described first tail current source metal-oxide-semiconductor is suitable for importing first supply voltage that is lower than described first target voltage.
6. level shifting circuit according to claim 1, it is characterized in that, the described first load metal-oxide-semiconductor and the described second load metal-oxide-semiconductor are the PMOS pipe, the described first input metal-oxide-semiconductor and the described second input metal-oxide-semiconductor are the NMOS pipe, the high level voltage of the described first driving signal and the difference of described second target voltage are greater than the threshold voltage of the described first input metal-oxide-semiconductor, and the low level voltage of the described first driving signal and the difference of described second target voltage are less than the threshold voltage of the described first input metal-oxide-semiconductor.
7. level shifting circuit according to claim 6, it is characterized in that described difference channel comprises the second tail current source metal-oxide-semiconductor, the 3rd difference input metal-oxide-semiconductor, the 4th difference input metal-oxide-semiconductor, the 3rd common mode sample resistance, the 4th common mode sample resistance, the 3rd constant current metal-oxide-semiconductor and the 4th constant current metal-oxide-semiconductor; Wherein, described the 3rd common mode sample resistance is identical with the resistance of described the 4th common mode sample resistance, the grid of the described second tail current source metal-oxide-semiconductor is suitable for importing the 5th conducting voltage that makes the described second tail current source metal-oxide-semiconductor saturation conduction, the source electrode of the described second tail current source metal-oxide-semiconductor is suitable for importing the second source voltage that is higher than described second target voltage, and the drain electrode of the described second tail current source metal-oxide-semiconductor connects the source electrode of described the 3rd difference input metal-oxide-semiconductor and the source electrode of described the 4th difference input metal-oxide-semiconductor; The grid of described the 3rd difference input metal-oxide-semiconductor is suitable for importing described first input signal, and the drain electrode of described the 3rd difference input metal-oxide-semiconductor connects the drain electrode of described the 3rd constant current metal-oxide-semiconductor and exports first output of the described first driving signal as described difference channel; The grid of described the 4th difference input metal-oxide-semiconductor is suitable for importing described second input signal, and the drain electrode of described the 4th difference input metal-oxide-semiconductor connects the drain electrode of described the 4th constant current metal-oxide-semiconductor and exports second output of the described second driving signal as described difference channel; One end of described the 3rd common mode sample resistance connects the drain electrode of described the 3rd difference input metal-oxide-semiconductor, and the other end connects an end of described the 4th common mode sample resistance and imports the input of described reference voltage as described difference channel; The other end of described the 4th common mode sample resistance connects the drain electrode of described the 4th difference input metal-oxide-semiconductor; The grid of described the 3rd constant current metal-oxide-semiconductor connects the grid of described the 4th constant current metal-oxide-semiconductor and is suitable for importing the 6th conducting voltage that makes described the 3rd constant current metal-oxide-semiconductor and described the 4th constant current metal-oxide-semiconductor saturation conduction, and the source electrode of described the 3rd constant current metal-oxide-semiconductor is suitable for importing described second target voltage; The source electrode of described the 4th constant current metal-oxide-semiconductor is suitable for importing described second target voltage.
8. according to each described level shifting circuit of claim 1 to 7, it is characterized in that, comprise that also the input of described CMOS inverter connects the link of the described second load metal-oxide-semiconductor and the described second input metal-oxide-semiconductor by the CMOS inverter of described first target voltage and the power supply of described second target voltage.
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| CN110958031A (en) * | 2019-12-26 | 2020-04-03 | 上海贝岭股份有限公司 | RS485 receiver circuit, integrated circuit and transceiver |
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Address after: Room 508-511, building a, Modern Plaza, No. 18, Weiye Road, Kunshan Development Zone, Suzhou, Jiangsu Patentee after: Ruixin Microelectronics Co., Ltd Address before: Room 508-511, block A, Modern Plaza, 18 Weiye Road, Kunshan, Jiangsu, Suzhou, 215300 Patentee before: BRIGATES MICROELECTRONICS (KUNSHAN) Co.,Ltd. |
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