CN103337513A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN103337513A CN103337513A CN2013102044601A CN201310204460A CN103337513A CN 103337513 A CN103337513 A CN 103337513A CN 2013102044601 A CN2013102044601 A CN 2013102044601A CN 201310204460 A CN201310204460 A CN 201310204460A CN 103337513 A CN103337513 A CN 103337513A
- Authority
- CN
- China
- Prior art keywords
- beryllium oxide
- semiconductor
- semiconductor structure
- semiconductor layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention proposes a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a beryllium oxide insulation layer formed on the substrate, a single-crystal semiconductor layer formed on the beryllium oxide insulation layer, and a semiconductor active component formed in the single-crystal semiconductor layer. According to the semiconductor structure and the forming method thereof, beryllium oxide is used for manufacturing a semiconductor structure which has good heat radiation performance. The semiconductor structure helps to highly efficiently radiate the heat in the component, substantially reduce difficulty in isolation of manufacturing SOI by using the single crystal characteristic of the beryllium oxide and improve the quality of a semiconductor thin film, and thus further improves performance of a chip and the component.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of semiconductor structure and forming method thereof.
Background technology
Along with further developing of semiconductor technology, the device integration density improves makes the power flash-up of unit are, the increase of chip power density and power consumption makes that its heat dissipation problem is a serious day by day and problem demanding prompt solution, especially for power semiconductor and power management integrated circuit, heat dissipation problem is the bottleneck of development always.Form now just, heat dissipation problem is not only to be to need one of factor of considering in high pressure, high-power chip and the device, and the significant design that has become the high integration logic chip one of is considered.Yet in the chip fabrication techniques of existing body material and SOI substrate, not only the thermal conductivity of semi-conducting material is low, and the insulating barrier among the SOI (is generally SiO
2) having lower thermal conductivity as a kind of electrical insulator, heat radiation is difficulty relatively, makes that heat is difficult to dissipate, and chip temperature is too high.
Therefore, this patent utilizes the characteristics of the high heat conductance of beryllium oxide insulating material, has formed a kind of high-efficiency heat radiation structure, and the passage of heat from device to outside heat abstractor can be provided.In addition, have benefited from the mono-crystalline structures that beryllium oxide has, this radiator structure can also significantly improve the electrology characteristic of semiconductor film material, significantly simplifies the manufacturing process of SOI substrate.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, and good semiconductor structure of a kind of heat dispersion and forming method thereof particularly is provided.
For achieving the above object, the semiconductor structure according to the embodiment of the invention comprises: substrate; Be formed on the beryllium oxide insulating barrier on the described substrate; Be formed on the single-crystal semiconductor layer on the described beryllium oxide insulating barrier; And be formed on semiconductor active device in the described single-crystal semiconductor layer.
In one embodiment of the invention, the material of described substrate is single crystalline Si, metal or pottery.
In one embodiment of the invention, when substrate was single crystalline Si, the indices of crystallographic plane of described substrate were (100), (110) or (111).
In one embodiment of the invention, described beryllium oxide insulating barrier is mono-crystalline structures.
In one embodiment of the invention, it is characterized in that the thickness of described beryllium oxide insulating barrier is the 0.1-500 micron.
In one embodiment of the invention, described single-crystal semiconductor layer is single crystalline Si, single crystalline Si Ge, monocrystalline Ge or monocrystalline III-V family semi-conducting material.
In one embodiment of the invention, described single-crystal semiconductor layer is the semi-conducting material with strain.
In one embodiment of the invention, described single-crystal semiconductor layer is the strain SiGe thin-film material.
In one embodiment of the invention, the thickness of described single-crystal semiconductor layer is the 0.005-200 micron.
In one embodiment of the invention, described beryllium oxide insulating barrier and described single-crystal semiconductor layer are and form by epitaxy technique growth.
In one embodiment of the invention, described semiconductor active device is power semiconductor.
For achieving the above object, the formation method according to the semiconductor structure of the embodiment of the invention comprises: substrate is provided; Form the beryllium oxide insulating barrier at described substrate; Form single-crystal semiconductor layer at described beryllium oxide insulating barrier; And in described single-crystal semiconductor layer, form the semiconductor active device.
In one embodiment of the invention, the material of described substrate is single crystalline Si, metal or pottery.
In one embodiment of the invention, when substrate was single crystalline Si, the indices of crystallographic plane of described substrate were (100), (110) or (111).
In one embodiment of the invention, described beryllium oxide insulating barrier is mono-crystalline structures.
In one embodiment of the invention, the thickness of described beryllium oxide insulating barrier is the 0.1-500 micron.
In one embodiment of the invention, described single-crystal semiconductor layer is single crystalline Si, single crystalline Si Ge, monocrystalline Ge or monocrystalline III-V family semi-conducting material.
In one embodiment of the invention, described single-crystal semiconductor layer is the semi-conducting material with strain.
In one embodiment of the invention, described single-crystal semiconductor layer is the strain SiGe thin-film material.
In one embodiment of the invention, the thickness of described single-crystal semiconductor layer is the 0.005-200 micron.
In one embodiment of the invention, form described beryllium oxide insulating barrier and described single-crystal semiconductor layer by the epitaxy technique growth.
In one embodiment of the invention, described semiconductor active device is power semiconductor.
In sum, the core concept of semiconductor structure of the present invention and forming method thereof is to utilize beryllium oxide to make a kind of semiconductor structure of perfect heat-dissipating, this structure not only can shed the heat in the device efficiently, and the monocrystalline character that can utilize beryllium oxide reduces the difficulty of making the SOI isolation greatly, improve the quality of semiconductive thin film, and then improve the performance of chip and device.The present invention has the following advantages at least:
1. good heat dissipation effect.The thermal conductivity of monocrystalline beryllium oxide is a lot of than oxidation object heights such as traditional silicon dioxide or silicon oxynitrides, close to metallic aluminium, thereby can improve heat dissipation problem between the device significantly, improves the performance of device.Use the BeO of high heat conductance, the heat that semiconductor active device especially power device can be produced efficiently, directly conduction is come out, and has very high radiating efficiency.
2. manufacture craft is simple.By monocrystalline beryllium oxide and single-crystal semiconductor layer priority extension, form beryllium oxide insulating barrier and single-crystal semiconductor layer.Because beryllium oxide crystal and common semi-conducting material such as Si, Ge, SiGe, GaAs etc. are all cubic system, simultaneously, the lattice constant of silicon single crystal
Monocrystalline beryllium oxide lattice constant
Be approximately half of Si monocrystalline, namely the unit cell of a Si crystal just in time is complementary with two beryllium oxide crystal unit cells, be that its lattice constant is basic coupling, so can on the Si matrix, direct extension form monocrystalline beryllium oxide film, also can on the monocrystalline beryllium oxide, extension form single-crystal semiconductor layer.The single-crystal semiconductor layer of the BeO of mono-crystalline structures and making device can pass through multiple extensional mode growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), these epitaxy techniques are compatible mutually with traditional semiconductor preparing process, be simple and easy to realize that cost is low.
3. device performance is good, the reliability height.Because BeO insulate, form single-crystal semiconductor layer on it and namely be equivalent to soi structure, the active semiconductor device that adopts this structure to form has the premium properties that a series of SOI devices such as operating voltage height, little, the anti-irradiation of electric leakage, reliability height have.
4. good insulation preformance.The energy gap of monocrystalline beryllium oxide is 10.6eV, and relative dielectric constant is 6.8, has excellent insulation property.
The aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the schematic diagram of the semiconductor structure of the embodiment of the invention;
Fig. 2 is the schematic diagram of the semiconductor active device in the semiconductor structure of the embodiment of the invention; With
Fig. 3 is the flow chart of formation method of the semiconductor structure of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical or similar label is represented identical or similar elements or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " " center "; " vertically "; " laterally "; " on "; D score; " preceding ", " back ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", close the orientation of indications such as " outward " or position is based on orientation shown in the drawings or position relation, only be that the present invention for convenience of description and simplification are described, rather than device or the element of indication or hint indication must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.Further, in description of the invention, except as otherwise noted, the implication of " a plurality of " is two or more, the implication of " multilayer " be two-layer or two-layer more than.
Fig. 1 is the schematic diagram of the semiconductor structure of the embodiment of the invention.As shown in Figure 1, this semiconductor structure comprises substrate 100 from bottom to up successively; Be formed on the beryllium oxide insulating barrier 200 on the substrate 100; Be formed on the single-crystal semiconductor layer 300 on the beryllium oxide insulating barrier 200, be formed on the semiconductor active device 400 in the single-crystal semiconductor layer 300.Need to prove, structure in the semiconductor active device 400 among Fig. 1 is only as a kind of example, rather than the semiconductor active device among the present invention is limited to this structure, concrete semiconductor active device structures can be according to the application demand flexible design of device in actual applications, and the present invention repeats no more.
The material of substrate 100 can be single crystalline Si, metal or pottery.When substrate 100 was single crystalline Si, the indices of crystallographic plane of substrate were (100), (110) or (111).The single crystalline Si crystal mates mutually with the lattice with beryllium oxide insulating barrier 200 of monocrystalline character.Particularly, the lattice constant of silicon single crystal
Monocrystalline beryllium oxide lattice constant
Be approximately half of Si monocrystalline, namely the unit cell of a Si crystal just in time is complementary with two beryllium oxide crystal unit cells, be that its lattice constant is basic coupling, thus can be on the Si matrix directly extension form monocrystalline beryllium oxide film, simultaneously also can be on the monocrystalline beryllium oxide epitaxy Si monocrystalline.
The beryllium oxide insulating barrier 200 preferred beryllium oxide that adopt mono-crystalline structures.This beryllium oxide insulating barrier 200 can pass through multiple epitaxy technique growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE) and form, and thickness is about the 0.1-500 micron.
The material of single-crystal semiconductor layer 300 is single crystalline Si, single crystalline Si Ge or monocrystalline Ge or monocrystalline III-V family semi-conducting material.This single-crystal semiconductor layer 300 can pass through multiple epitaxy technique growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE) and form, and thickness is about the 0.005-200 micron.Preferably, single-crystal semiconductor layer 300 has strain.For example, single-crystal semiconductor layer 300 adopts the strain SiGe film, utilizes the fine difference of SiGe and Si lattice, can make the SiGe film have strain.Semiconductor layer 300 with strain may have different advantages in different components is used.For example, in the MOSFET device, can improve the mobility of charge carrier in the raceway groove effectively by in raceway groove, introducing strain, improve the performance of device.
In a preferred embodiment of the invention, have the beryllium oxide insulating barrier 200 of mono-crystalline structures and single-crystal semiconductor layer 300 all by the epitaxy technique formation of successively growing, adopt conventional semiconductor technology to finish, technology is simple.
In one embodiment of the invention, semiconductor active device 400 is power semiconductor, comprising LDMOS(lateral double-diffused metal-oxide semiconductor, Laterally Diffused Metal Oxide Semiconductor) multiple power device such as device (as shown in Figure 2), Schottky diode.In a preferred embodiment, the semiconductor active device is the LDMOS device, and its raceway groove is the strain SiGe material, has than the more excellent carrier mobility of conventional Si raceway groove, be that its carrier drift speed is faster, so strain SiGe LDMOS device is better than the electric property of conventional SiLDMOS.
Fig. 3 is the flow chart of formation method of the semiconductor structure of the embodiment of the invention.As shown in Figure 3, the formation method of this semiconductor structure comprises successively:
S1., substrate 100 is provided.
S2. form beryllium oxide insulating barrier 200 at substrate 100.
Be preferably formed the beryllium oxide insulating barrier 200 of mono-crystalline structures.This beryllium oxide insulating barrier 200 can pass through multiple epitaxy technique growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE) and form, and thickness is about the 0.1-500 micron.
S3. form single-crystal semiconductor layer 300 at beryllium oxide insulating barrier 200.
The material of single-crystal semiconductor layer 300 is single crystalline Si, single crystalline Si Ge or monocrystalline Ge or monocrystalline III-V family semiconductor material.This single-crystal semiconductor layer 300 can pass through multiple epitaxy technique growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE) and form, and thickness is about the 0.005-200 micron.Preferably, single-crystal semiconductor layer 300 has strain.For example, single-crystal semiconductor layer 300 adopts the strain SiGe film, utilizes the fine difference of SiGe and Si lattice, can make the SiGe film have strain.Semiconductor layer 300 with strain may have different advantages in different components is used.For example, in the MOSFET device, can improve the mobility of charge carrier in the raceway groove effectively by in raceway groove, introducing strain, improve the performance of device.
S4. in single-crystal semiconductor layer 300, form semiconductor active device 400.Concrete formation method is selected flexibly according to the designs demand, and the present invention repeats no more.
Need to prove, after forming semiconductor active device 400, can also be bonded to then on metal or the ceramic substrate further with silicon substrate attenuate even removal, can further improve its heat dispersion like this.
In sum, the core concept of semiconductor structure of the present invention and forming method thereof is to utilize beryllium oxide to make a kind of semiconductor structure of perfect heat-dissipating, this structure not only can shed the heat in the device efficiently, and the monocrystalline character that can utilize beryllium oxide reduces the difficulty of making the SOI isolation greatly, improve the quality of semiconductive thin film, and then improve the performance of chip and device.The present invention has the following advantages at least:
1. good heat dissipation effect.The thermal conductivity of monocrystalline beryllium oxide is a lot of than oxidation object heights such as traditional silicon dioxide or silicon oxynitrides, close to metallic aluminium, thereby can improve heat dissipation problem between the device significantly, improves the performance of device.Use the BeO of high heat conductance, the heat that semiconductor active device especially power device can be produced efficiently, directly conduction is come out, and has very high radiating efficiency.
2. manufacture craft is simple.By monocrystalline beryllium oxide and single-crystal semiconductor layer priority extension, form beryllium oxide insulating barrier and single-crystal semiconductor layer.Because beryllium oxide crystal and common semi-conducting material such as Si, Ge, SiGe, GaAs etc. are all cubic system, simultaneously, the lattice constant of silicon single crystal
Monocrystalline beryllium oxide lattice constant
Be approximately half of Si monocrystalline, namely the unit cell of a Si crystal just in time is complementary with two beryllium oxide crystal unit cells, be that its lattice constant is basic coupling, so can on the Si matrix, direct extension form monocrystalline beryllium oxide film, also can on the monocrystalline beryllium oxide, extension form single-crystal semiconductor layer.The single-crystal semiconductor layer of the BeO of mono-crystalline structures and making device can pass through multiple extensional mode growth such as ald (ALD), metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), these epitaxy techniques are compatible mutually with traditional semiconductor preparing process, be simple and easy to realize that cost is low.
3. device performance is good, the reliability height.Because BeO insulate, form single-crystal semiconductor layer on it and namely be equivalent to soi structure, the active semiconductor device that adopts this structure to form has the premium properties that a series of SOI devices such as operating voltage height, little, the anti-irradiation of electric leakage, reliability height have.
4. good insulation preformance.The energy gap of monocrystalline beryllium oxide is 10.6eV, and relative dielectric constant is 6.8, has excellent insulation property.
In the description of this specification, concrete feature, structure, material or characteristics that the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example description are contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete feature, structure, material or the characteristics of description can be with the suitable manner combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment that scope of the present invention is by claims and be equal to and limit.
Claims (22)
1. a semiconductor structure is characterized in that, comprising:
Substrate;
Be formed on the beryllium oxide insulating barrier on the described substrate;
Be formed on the single-crystal semiconductor layer on the described beryllium oxide insulating barrier; And
Be formed on the semiconductor active device in the described single-crystal semiconductor layer.
2. semiconductor structure as claimed in claim 1 is characterized in that, the material of described substrate is single crystalline Si, metal or pottery.
3. as claim 1 and 2 described semiconductor structures, it is characterized in that when substrate was single crystalline Si, the indices of crystallographic plane of described substrate were (100), (110) or (111).
4. as the described semiconductor structure of claim 1 to 3, it is characterized in that described beryllium oxide insulating barrier is mono-crystalline structures.
5. semiconductor structure as claimed in claim 1 is characterized in that, the thickness of described beryllium oxide insulating barrier is the 0.1-500 micron.
6. semiconductor structure as claimed in claim 1 is characterized in that, described single-crystal semiconductor layer is single crystalline Si, single crystalline Si Ge, monocrystalline Ge or monocrystalline III-V family semi-conducting material.
7. as claim 1 and 6 described semiconductor structures, it is characterized in that described single-crystal semiconductor layer is the semi-conducting material with strain.
8. semiconductor structure as claimed in claim 7 is characterized in that, described single-crystal semiconductor layer is the strain SiGe thin-film material.
9. semiconductor structure as claimed in claim 1 is characterized in that, the thickness of described single-crystal semiconductor layer is the 0.005-200 micron.
10. semiconductor structure as claimed in claim 4 is characterized in that, described beryllium oxide insulating barrier and described single-crystal semiconductor layer are and form by epitaxy technique growth.
11. semiconductor structure as claimed in claim 1 is characterized in that, described semiconductor active device is power semiconductor.
12. the formation method of a semiconductor structure is characterized in that, comprising:
Substrate is provided;
Form the beryllium oxide insulating barrier at described substrate;
Form single-crystal semiconductor layer at described beryllium oxide insulating barrier; And
In described single-crystal semiconductor layer, form the semiconductor active device.
13. semiconductor structure as claimed in claim 12 is characterized in that, the material of described substrate is single crystalline Si, metal or pottery.
14. semiconductor structure as claimed in claim 12 is characterized in that, when substrate was single crystalline Si, the indices of crystallographic plane of described substrate were (100), (110) or (111).
15., it is characterized in that described beryllium oxide insulating barrier is mono-crystalline structures as claim 12 and 13 described semiconductor structures.
16. semiconductor structure as claimed in claim 12 is characterized in that, the thickness of described beryllium oxide insulating barrier is the 0.1-500 micron.
17. semiconductor structure as claimed in claim 12 is characterized in that, described single-crystal semiconductor layer is single crystalline Si, single crystalline Si Ge, monocrystalline Ge or monocrystalline III-V family semi-conducting material.
18., it is characterized in that described single-crystal semiconductor layer is the semi-conducting material with strain as the described semiconductor structure of claim 12 to 17.
19., it is characterized in that described single-crystal semiconductor layer is the strain SiGe thin-film material as claim 11 and 18 described semiconductor structures.
20. semiconductor structure as claimed in claim 12 is characterized in that, the thickness of described single-crystal semiconductor layer is the 0.005-200 micron.
21. semiconductor structure as claimed in claim 15 is characterized in that, forms described beryllium oxide insulating barrier and described single-crystal semiconductor layer by the epitaxy technique growth.
22. semiconductor structure as claimed in claim 12 is characterized in that, described semiconductor active device is power semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102044601A CN103337513A (en) | 2013-05-28 | 2013-05-28 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102044601A CN103337513A (en) | 2013-05-28 | 2013-05-28 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103337513A true CN103337513A (en) | 2013-10-02 |
Family
ID=49245648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102044601A Pending CN103337513A (en) | 2013-05-28 | 2013-05-28 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103337513A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068724A (en) * | 2017-04-24 | 2017-08-18 | 京东方科技集团股份有限公司 | OLED display panel and preparation method thereof, OLED display |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52156581A (en) * | 1976-06-23 | 1977-12-27 | Toshiba Corp | Semiconductor device |
| US4523211A (en) * | 1982-03-16 | 1985-06-11 | Futaba Denshi Kogyo Kabushiki Kaisha | Semiconductor device |
| US20100044696A1 (en) * | 2006-09-04 | 2010-02-25 | Taiwan Tft Lcd Association | Thin film transistor and liquid crystal display |
-
2013
- 2013-05-28 CN CN2013102044601A patent/CN103337513A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52156581A (en) * | 1976-06-23 | 1977-12-27 | Toshiba Corp | Semiconductor device |
| US4523211A (en) * | 1982-03-16 | 1985-06-11 | Futaba Denshi Kogyo Kabushiki Kaisha | Semiconductor device |
| US20100044696A1 (en) * | 2006-09-04 | 2010-02-25 | Taiwan Tft Lcd Association | Thin film transistor and liquid crystal display |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068724A (en) * | 2017-04-24 | 2017-08-18 | 京东方科技集团股份有限公司 | OLED display panel and preparation method thereof, OLED display |
| WO2018196279A1 (en) * | 2017-04-24 | 2018-11-01 | 京东方科技集团股份有限公司 | Oled display panel, manufacturing method thereof, and oled display |
| US10546907B2 (en) | 2017-04-24 | 2020-01-28 | Boe Technology Group Co. Ltd. | OLED display panel, method of manufacturing the same, OLED display |
| CN107068724B (en) * | 2017-04-24 | 2020-06-12 | 京东方科技集团股份有限公司 | OLED display panel, preparation method thereof and OLED display |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Amano et al. | The 2018 GaN power electronics roadmap | |
| TWI732925B (en) | Electronic power devices integrated with an engineered substrate | |
| Iacopi et al. | Power electronics with wide bandgap materials: Toward greener, more efficient technologies | |
| TWI585863B (en) | Buffer layer structures suited for iii-nitride devices with foreign substrates | |
| US9911813B2 (en) | Reducing leakage current in semiconductor devices | |
| US20100085713A1 (en) | Lateral graphene heat spreaders for electronic and optoelectronic devices and circuits | |
| US20160308041A1 (en) | Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof | |
| US10256294B2 (en) | Vertical gallium nitride power field-effect transistor with a field plate structure | |
| US20200294883A1 (en) | Self-healing pdms encapsulation and repair of power modules | |
| US11715791B2 (en) | Group III-Nitride devices on SOI substrates having a compliant layer | |
| JP2015088756A (en) | Substrate structure, cmos device including the same, and method of manufacturing the same | |
| CN103021814A (en) | Method for preparing epitaxial composite substrate of gallium nitride based semiconducting material | |
| CN103400858B (en) | Three-dimensional semiconductor device and forming method thereof on insulator | |
| TW201128787A (en) | Solar module and manufacture method thereof | |
| CN103337513A (en) | Semiconductor structure and forming method thereof | |
| CN210897283U (en) | Semiconductor device with a plurality of transistors | |
| US11373998B2 (en) | Semiconductor device with differences in crystallinity between components | |
| CN103824880A (en) | Dual-axis tensile strain GeSn n channel tunneling field effect transistor | |
| CN114628523B (en) | Gallium nitride-based CMOS field effect transistor and preparation method thereof | |
| US20190181121A1 (en) | Method and system for electronic devices with polycrystalline substrate structure interposer | |
| EP2755236A2 (en) | Semiconductor structure including a spatially confined dielectric region | |
| CN104637813A (en) | IGBT manufacturing method | |
| CN208142186U (en) | A kind of high electronic migration rate transmistor epitaxial structure | |
| US20240047284A1 (en) | Composite substrate and semiconductor structure | |
| CN219246703U (en) | Composite substrate, epitaxial wafer and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131002 |
|
| RJ01 | Rejection of invention patent application after publication |