CN103336706A - System and method for converting pseudocode into programming language - Google Patents
System and method for converting pseudocode into programming language Download PDFInfo
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Abstract
The invention discloses a system and a method for converting a pseudocode into a programming language. The system comprises a data input module, a chip design specification module, a pseudocode conversion module and a data output module, wherein the data output module comprises a programming language output unit and a Bit operation type unit, and after the data input module and the chip design specification module are converted by the pseudocode conversion module, the programming language output unit outputs the generated programming language, and converts the pseudocode into a software language capable of being used directly by matching with the Bit operation type unit complying with the programming language. According to the system and the method, the conversion time from the pseudocode to the software language is shortened greatly, the functionality and the logicality of chip design logic can be verified efficiently, and the efficiency of chip testing is improved.
Description
Technical field
The present invention relates to the chip design development field, especially relate to a kind of system and method that false code is converted to programming language.
Background technology
In chip design, generally all write design specifications in the mode of false code, false code is a kind of algorithm description language between natural language and programming language, compare programming language (Java for example, C++, C, Dephi etc.), its similar natural language is easily understood.
Chip design personnel, checking personnel carry out design verification according to the design specifications of writing with false code, and there is long, problem such as verification efficiency is low of proving time in this verification mode.So, in order to shorten design, exploitation, proving time, consider to use the method for software simulation to come in advance the logic of false code design to be verified usually, so false code at first need be converted to the programming language that can carry out software simulation.The false code of writing is not generally speaking carried out format specification, changes problems such as difficult, that switching time is long so existing false code conversion regime exists, thereby has reduced the efficient of chip design.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, a kind of system and method that false code is converted to directly available programming language is provided, chip list association database and the chip design normative translation that to write with false code are programming language, and the programming language after will changing cooperates the Bit class of operation to generate the programming language that can be used for chip logic checking, shortened the switching time from the false code to the software language greatly.
For achieving the above object, the present invention proposes following technical scheme: a kind of system that false code is converted to programming language, it comprises the input data module, chip design standard module, false code modular converter and output data module, the data of described input data module input are the chip list association database, the chip logic of importing in the described chip design standard module that is to use prescribed form to write, the described chip list association database of writing with false code and chip logic after the conversion of false code modular converter, the programming language that can be used for chip logic checking that is generated by the output of output data module.
Preferably, described chip list association database comprises list item structure and the contents in table of chip at least, and the contents in table of described chip comprises list item size, list item attribute, document location, byte length at least.
Described false code modular converter comprises respectively chip list item converting unit and the chip design normative translation unit that links to each other with chip design standard module with the input data module.
Described chip design normative translation unit comprises that the module that links to each other successively is connected to programming language function converting unit, operational symbol, special character, and data structure is resolved and is replaced unit, chip read-write list item converting unit, the non-read-write list item of chip converting unit.
Described output data module comprises programming language output unit and Bit class of operation unit, and described programming language output unit and Bit class of operation unit match and generate the programming language that can be used for chip logic checking.
Described Bit class of operation unit comprises: the Bit operation accords with heavily loaded unit, Bit operation memory management unit and Bit operation information storage unit.
A kind of method that false code is converted to programming language, comprise: chip list association database and chip design standard are carried out typing, the information of typing is carried out false code to the conversion of programming language, and cooperate the programming language after the Bit class of operation will be changed to be generated as the programming language that can be used for chip logic checking.
Preferably, described chip list association database comprises list item structure and the contents in table of all chips at least, and described contents in table comprises list item size, list item attribute, document location, byte length at least.
The chip logic of described chip design standard for using prescribed form to write.
Described information with typing is carried out false code and is comprised to the conversion method of programming language:
The chip list association database is converted to the programming language data structure;
Module annexation in the chip design standard is converted to the programming language function call;
With the false code operational symbol in the chip design standard, be converted to after special character and data structure are resolved programming language can the heavy duty operational symbol, the character that can set and data structure;
The chip list item that needs in the chip design standard to read and write is converted to global variable;
Local variable is searched and be converted to non-chip read-write list item in the chip design standard automatically.
The method that programming language after described cooperation Bit class of operation will be changed is generated as the programming language that can be used for chip logic checking comprises:
With the operational symbol of operator overloading for calculating by Bit;
The Bit class is carried out the management of Memory Allocation;
Information in the contents in table in the chip list association database is stored.
Beneficial effect of the present invention is: can realize false code is converted to directly available software language, can be used for software simulation chip design logic, thereby carry out the simulation test of chip design, shortened the switching time from the false code to the software language greatly, be conducive to efficiently functional, the logicality of chip design logic be verified, improved the efficient of chip testing greatly.
Description of drawings
Fig. 1 is the general structure block diagram that the embodiment of the invention is converted to false code the system of C Plus Plus;
Fig. 2 is the FB(flow block) that embodiment of the invention chip list association database is converted to the C Plus Plus data structure;
Fig. 3 is that embodiment of the invention chip design normative translation is the FB(flow block) of C++ logical language;
Fig. 4 is embodiment of the invention Bit class of operation unit composition frame chart;
Fig. 5 is the FB(flow block) that the embodiment of the invention is converted to false code the method for C Plus Plus;
Fig. 6 carries out false code to the transformation flow figure of C Plus Plus with the information of typing among Fig. 5;
Fig. 7 cooperates the Bit class of operation to generate the FB(flow block) of the C Plus Plus that can be used for chip logic checking among Fig. 5;
Embodiment
Below in conjunction with accompanying drawing of the present invention, the technical scheme of the embodiment of the invention is carried out clear, complete description.
Be example false code is converted to C Plus Plus in the example of the present invention, disclosed a kind of method that false code is converted to C Plus Plus, this method is stipulated the pseudo-code language form of chip design standard on the one hand, utilize the heavily loaded function of object oriented calculation machine programming languages such as C++ on the other hand, and according to the singularity of chip design, the i.e. characteristic that Bit is operated is set up the heavy duty about the various operational symbols of Bit of C++, thereby is generated the C Plus Plus that can be used for chip logic checking.
Referring to shown in Figure 1, Fig. 1 is the general structure block diagram that the present invention is converted to false code the system of C Plus Plus, this system comprises: input data module, chip design standard module, false code modular converter and output data module, the input data module of writing with false code and chip design standard module after the conversion of false code modular converter, the C Plus Plus that can be used for chip logic checking that is generated by the output of output data module.
The data of importing in the input data module are the chip list association database, i.e. list item structure and the contents in table of all chips of typing.
The chip logic of importing in the chip design standard module that is to use prescribed form to write for the pseudo-code language form of regulation chip design standard, is convenient to carry out false code to the conversion of C Plus Plus, improves conversion efficiency.
The output data module comprises C Plus Plus output unit and Bit class of operation unit, wherein the C++ code of C Plus Plus output unit output matches with Bit class of operation unit, the heavily loaded function of Bit class of operation unit by using C++ object oriented calculation machine programming language, and the singularity according to chip design, the i.e. characteristic that Bit is operated, set up the heavy duty about the various operational symbols of Bit of C++, thereby generate the C Plus Plus that can be used for chip logic checking.
Referring to shown in Figure 2, Fig. 2 is converted to the FB(flow block) of C Plus Plus data structure for chip list association database of the present invention, the data of importing in the input data module are the chip list association database, and the chip list association database converts the C Plus Plus data structure to through chip list item converting unit.
The list item structure and the contents in table that comprise chip in the chip list association database, contents in table comprise list item size, list item attribute, document location, byte length at least,
Referring to shown in Figure 3, Fig. 3 is the FB(flow block) of C++ logical language for the chip design normative translation, and the chip design specification unit is converted to the C Plus Plus function call with the connection of the module in the chip design standard after module is connected to C Plus Plus function converting unit.
Again through operational symbol, special character, data structure is resolved and is replaced the unit with the false code operational symbol in the chip design standard, and special character and data structure are resolved and are changed, and are converted to the operational symbol that C Plus Plus can heavy duty, discernible character and data structure.
Chip read-write list item converting unit is converted to global variable with the chip list item that needs in the chip design standard to read and write, and is beneficial to can directly use at each modularity function.
The local variable of each function is searched and be generated as to the non-read-write list item of chip converting unit with its dependent variable of the non-read-write list item of chip, automatically, is used in the inner use of function.
Referring to shown in Figure 4, Fig. 4 is Bit class of operation of the present invention unit composition frame chart, and Bit class of operation unit comprises: the Bit operation accords with heavily loaded unit, Bit operation memory management unit and Bit operation information storage unit.
The Bit operation accords with heavily loaded unit, is used for operational symbol is carried out heavy duty the operational symbol of heavy duty for calculating by Bit.The operational symbol of heavy duty mainly comprises "+", "-", ", ", " | ", “ ﹠amp; ", " | ", “ ﹠amp; ﹠amp; ", " () ", " [] ", " * ", "/", "＜＜", "＞＞", "＞", symbol such as "＜" common operation, all heavy duty is the operational symbol to newly-built Bit class, and the operational symbol between Bit class and other data types.
Bit operates memory management unit, mainly the Bit class is carried out the management of Memory Allocation, constructed fuction and destructor function etc.
Bit operation information storage unit, the relevant information of file in the C Plus Plus data structure of main storage after conversion, as document location, byte length, file name and other information.
Wherein, the false code modular converter among the present invention comprises that chip list item converting unit, module are connected to C Plus Plus function converting unit, special character, and data structure is resolved and replaced unit, chip read-write list item converting unit, the non-read-write list item of chip converting unit.
Also disclosed in the embodiment of the invention and a kind of false code has been converted to the method for C Plus Plus, FB(flow block) as shown in Figure 5 comprises successively:
The first step is carried out typing with chip list association database and chip design standard;
Wherein, the chip list association database is as the input data, comprise chip list item structure and contents in table, contents in table is information such as list item size, list item attribute, document location, byte length, and the chip list association database is carried out typing according to certain rule, is convenient to generate the C Plus Plus data structure.
The chip design standard is the chip logic that uses prescribed form to write, and has stipulated the pseudo-code language form of chip design standard.
In second step, the information of typing is carried out false code to the conversion of C Plus Plus; FB(flow block) as shown in Figure 6 comprises:
The chip list association database is converted to the C Plus Plus data structure;
Module annexation in the chip design standard is converted to the C Plus Plus function call;
With the false code operational symbol in the chip design standard, be converted to after special character and data structure are resolved C Plus Plus can the heavy duty operational symbol, the character that can set and data structure;
The chip list item that needs in the chip design standard to read and write is converted to global variable, is beneficial to directly to use at each modularity function;
Non-chip in the chip design standard is read and write the local variable that each modularity function was searched and be converted to list item automatically, use in each inside modules.
The 3rd step cooperated the C Plus Plus after the Bit class of operation will be changed to be generated as the C Plus Plus that can be used for chip logic checking, and FB(flow block) as shown in Figure 7 comprises:
With the operational symbol of operator overloading for calculating by Bit, the operational symbol of heavy duty mainly comprises "+", "-", ", ", " | ", “ ﹠amp; ", " || ", “ ﹠amp; ﹠amp; ", " () ", " [] ", " * ", "/", "＜＜", "＞＞", "＞", symbol such as "＜" common operation, all heavy duty is the operational symbol to newly-built Bit class, and the operational symbol between Bit class and other data types;
The Bit class is carried out the management of Memory Allocation, mainly the Bit class is carried out the management of Memory Allocation, constructed fuction and destructor function etc.;
Information in the contents in table in the chip list association database is stored, the relevant information of file in the C Plus Plus data structure of main storage after conversion, as document location, byte length, file name and other information.
Further, what the present invention mainly utilized is the heavily loaded function of C Plus Plus, set up the Bit class of operation of pressing the Bit operation, other object oriented programming languages also have heavily loaded function, therefore on basis of the present invention, the part modular converter revised a little can be converted to other object oriented programming languages, it is a kind of to be not limited to C Plus Plus, can adapt to different programming language platforms.
In sum, the invention provides a kind of system and method that false code is converted to directly available programming language, shortened the switching time from the false code to the software language greatly, be conducive to efficiently functional to the chip design logic, logicality is verified, has improved the efficient of chip testing.
Technology contents of the present invention and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; therefore; protection domain of the present invention should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by the present patent application claim.
Claims (10)
1. false code is converted to the system of programming language, it is characterized in that: it comprises input data module, chip design standard module, false code modular converter and output data module, the data of described input data module input are the chip list association database, the chip logic of importing in the described chip design standard module that is to use prescribed form to write, the described chip list association database of writing with false code and chip logic after the conversion of false code modular converter, the programming language that can be used for chip logic checking that is generated by the output of output data module.
2. the system that false code is converted to programming language according to claim 1, it is characterized in that, described chip list association database comprises list item structure and the contents in table of chip at least, and the contents in table of described chip comprises list item size, list item attribute, document location, byte length at least.
3. the system that false code is converted to programming language according to claim 1, it is characterized in that described false code modular converter comprises respectively chip list item converting unit and the chip design normative translation unit that links to each other with chip design standard module with the input data module.
4. the system that false code is converted to programming language according to claim 3, it is characterized in that, described chip design normative translation unit comprises that the module that links to each other successively is connected to programming language function converting unit, operational symbol, special character, data structure are resolved and are replaced unit, chip read-write list item converting unit, the non-read-write list item of chip converting unit.
5. the system that false code is converted to programming language according to claim 1, it is characterized in that, described output data module comprises programming language output unit and Bit class of operation unit, and described programming language output unit and Bit class of operation unit match and generate the programming language that can be used for chip logic checking.
6. according to claim 5 false code is converted to the system of programming language, it is characterized in that described Bit class of operation unit comprises: the Bit operation accords with heavily loaded unit, Bit operation memory management unit and Bit operation information storage unit.
7. false code is converted to the method for programming language, it is characterized in that: chip list association database and the chip design standard of using prescribed form to write are carried out typing, the information of typing is carried out false code to the conversion of programming language, and cooperate the programming language after the Bit class of operation will be changed to generate the programming language that can be used for chip logic checking.
8. the method that false code is converted to programming language according to claim 7, it is characterized in that, described chip list association database comprises list item structure and the contents in table of all chips at least, and described contents in table comprises list item size, list item attribute, document location, byte length at least.
9. according to claim 7 false code is converted to the method for programming language, it is characterized in that, described information with typing is carried out false code and is comprised to the conversion method of programming language:
The chip list association database is converted to the programming language data structure;
Module annexation in the chip design standard is converted to the programming language function call;
With the false code operational symbol in the chip design standard, be converted to after special character and data structure are resolved programming language can the heavy duty operational symbol, special character and data structure;
The chip list item that needs in the chip design standard to read and write is converted to global variable;
Local variable is searched and be converted to non-chip read-write list item in the chip design standard automatically.
10. according to claim 7 false code is converted to the method for programming language, it is characterized in that the method that the programming language after described cooperation Bit class of operation will be changed is generated as the programming language that can be used for chip logic checking comprises:
With the operational symbol of operator overloading for calculating by Bit;
The Bit class is carried out the management of Memory Allocation;
Information in the contents in table in the chip list association database is stored.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105446268A (en) * | 2015-09-15 | 2016-03-30 | 浙江吉利控股集团有限公司 | Simulation method for movement track of pressing machine |
| CN106293725A (en) * | 2016-08-04 | 2017-01-04 | 深圳市微我科技有限公司 | A kind of natural language hybrid programming method based on rear realization |
| CN107506228A (en) * | 2017-09-11 | 2017-12-22 | 珠海亿智电子科技有限公司 | A kind of method that driving code is automatically generated according to chip handbook |
| CN109960590A (en) * | 2019-03-26 | 2019-07-02 | 北京简约纳电子有限公司 | A method of optimization embedded system diagnostic printing |
| CN110752895A (en) * | 2019-10-22 | 2020-02-04 | 盛科网络（苏州）有限公司 | Programming method and device of Ethernet message |
| CN114386381A (en) * | 2021-11-30 | 2022-04-22 | 航天信息股份有限公司 | Method and system for automatically generating analysis report |
| CN114386381B (en) * | 2021-11-30 | 2024-08-02 | 航天信息股份有限公司 | Method and system for automatically generating analysis report |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446268A (en) * | 2015-09-15 | 2016-03-30 | 浙江吉利控股集团有限公司 | Simulation method for movement track of pressing machine |
| CN106293725A (en) * | 2016-08-04 | 2017-01-04 | 深圳市微我科技有限公司 | A kind of natural language hybrid programming method based on rear realization |
| CN107506228A (en) * | 2017-09-11 | 2017-12-22 | 珠海亿智电子科技有限公司 | A kind of method that driving code is automatically generated according to chip handbook |
| CN109960590A (en) * | 2019-03-26 | 2019-07-02 | 北京简约纳电子有限公司 | A method of optimization embedded system diagnostic printing |
| CN110752895A (en) * | 2019-10-22 | 2020-02-04 | 盛科网络（苏州）有限公司 | Programming method and device of Ethernet message |
| WO2021077879A1 (en) * | 2019-10-22 | 2021-04-29 | 盛科网络（苏州）有限公司 | Ethernet packet programming method and apparatus |
| CN114386381A (en) * | 2021-11-30 | 2022-04-22 | 航天信息股份有限公司 | Method and system for automatically generating analysis report |
| CN114386381B (en) * | 2021-11-30 | 2024-08-02 | 航天信息股份有限公司 | Method and system for automatically generating analysis report |
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Effective date of registration: 20171218 Address after: Xinghan street Suzhou Industrial Park in Jiangsu province 215000 No. 5 Building No. 6 Room 201 Patentee after: Suzhou Sheng Ke science and Technology Co., Ltd. Address before: Xinghan Street Industrial Park of Suzhou city in Jiangsu province 215021 No. 5 (Tengfei Industrial Square) B building 4 floor 13/16 unit Patentee before: Centec Networks (Suzhou) Inc. |