CN103327587A - Method and device for controlling sleep cycle of terminal - Google Patents
Method and device for controlling sleep cycle of terminal Download PDFInfo
- Publication number
- CN103327587A CN103327587A CN2013102068220A CN201310206822A CN103327587A CN 103327587 A CN103327587 A CN 103327587A CN 2013102068220 A CN2013102068220 A CN 2013102068220A CN 201310206822 A CN201310206822 A CN 201310206822A CN 103327587 A CN103327587 A CN 103327587A
- Authority
- CN
- China
- Prior art keywords
- timing
- frequency clock
- low
- timing point
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
The invention provides a method and device for controlling a sleep cycle of a terminal. The method includes the steps that after the instruction of entering a sleep mode is received, a high-frequency clock is used for conducting timing; when the fact that timing of the high-frequency clock reaches a first time point is determined, a low-frequency clock is used for conducting timing and the terminal enters the sleep mode; when the fact that the timing of the low-frequency clock reaches a second timing point is determined, the high-frequency clock is used for conducting timing; when the fact that the timing of the high-frequency clock reaches a third timing point, the terminal is triggered to enter a working mode, and starts to conduct data interaction with a base station. The method and device can prolong the sleep cycle of the terminal and lower power consumption of the terminal.
Description
Technical field
The present invention relates to the mobile communication technology field, particularly relate to a kind of terminal sleep periodic Control method, and a kind of terminal sleep periodic Control device.
Background technology
LTE (Long Term Evolution, the Long Term Evolution project) is widely used as a kind of the 4th generation wireless telecommunications (3G) standard, use the electronic equipment of LTE communication standard that the network service of fast and stable can be provided as the user, has receiving velocity high, the characteristics such as the high and receiver of the availability of frequency spectrum is simple.
In the LTE system, in user terminal UE when work, must to carry out correct time synchronous with base station eNB, namely constantly keeps the state of the subframe alignment of the transmission of data.Under mode of operation, there is independent time block in the UE receiver, produce sequential and the timing of various needs with high frequency clock, high frequency clock provides the precise time reference for the operation of system, can guarantee the normal transceiving data of UE.
UE can close receiver and enter sleep pattern when not needing monitor channel information, and under sleep pattern, UE carries out the sleep awakening process according to DRX (Discontinuous Reception, the discontinuous acceptance) cycle of network side configuration.In order to reduce as far as possible system power dissipation, high frequency clock source that can shutdown system comprises high-frequency oscillating circuits and PLL, uses the low-frequency clock timing.After the DRX sleep cycle finishes, need from sleep, to wake UE up immediately, and the startup receiver is started working.
Adopt low-frequency clock (32.768KHZ) to replace the higher high frequency clock of precision under the sleep pattern, when when UE wakes up, beginning the transmission of data, because the inaccuracy of time, the losing of the synchronous information such as the subframe border that can cause the transmission of data and frame number, thus need re-synchronization.
And the process need high frequency clock of re-synchronization, and require UE to be in mode of operation, therefore, need to finish in advance sleep pattern, thus, the process of re-synchronization is actual to be the length of one's sleep that has shortened terminal, because the time of re-synchronization can reach Millisecond, for shorter DRX sleep cycle, system even can't enter sleep is unfavorable for the low-power consumption of terminal.
Summary of the invention
Technical problem to be solved by this invention provides a kind of terminal sleep periodic Control method, to prolong the sleep cycle of terminal, reduces the power consumption of terminal.
The present invention also provides a kind of terminal sleep periodic Control device, in order to guarantee said method application and realization in practice.
In order to address the above problem, the invention discloses a kind of terminal sleep periodic Control method, comprising:
After receiving the instruction that enters sleep pattern, carry out timing by high frequency clock;
When determining to arrive the first timing point by described high frequency clock timing, carry out timing by low-frequency clock, and triggering terminal enters sleep pattern, wherein, the first side of described the first timing point and described low-frequency clock is along concordant;
When determining to arrive the second timing point by described low-frequency clock timing, carry out timing by described high frequency clock, wherein, the Second Edge of described the second timing point and described low-frequency clock is along concordant, the difference T1 of the duration of the duration of described the second timing point and described the first timing point is according to the sleep cycle T0 configuration of described terminal, and the difference of T0 and T1 is less than the first pre-set threshold value;
When determining to arrive the 3rd timing point by described high frequency clock timing, triggering terminal enters mode of operation, and beginning is carried out data interaction with the base station, and wherein, the duration of described the 3rd timing point is described sleep cycle T0.
Preferably,, comprising according to the difference T1 that the sleep cycle T0 of described terminal configures the duration of the first timing point and the second timing point by following steps:
With the time-count cycle of sleep cycle T0 divided by low-frequency clock, obtain low-frequency clock the first number of time-count cycle;
Determine the second number of the time-count cycle of low-frequency clock according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value, with the product of described the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
Preferably, described first side is along being after the time zero, first edge of described low-frequency clock.
Preferably, described first side is along being after the time zero, N edge of described low-frequency clock, and N is positive integer;
Described method also comprises, determines the first side edge of described low-frequency clock by following steps:
Calculate the difference of difference T1 that described sleep cycle T0 deducts the duration of the duration of the second timing point and described the first timing point;
The described time zero of selected distance is no more than the edge of T0 and T1 difference as the first side edge of described low-frequency clock.
Preferably, the first side of described low-frequency clock edge or Second Edge are along sampling definite by described high frequency clock to described low-frequency clock.
The present invention also provides a kind of terminal sleep periodic Control device, comprising:
The first high frequency timing module, after being used for receiving the instruction that enters sleep pattern, carry out timing by high frequency clock, when determining by described high frequency clock timing to the first timing point, stop to carry out timing by described high frequency clock, wherein, described the first timing point and the first side of described low-frequency clock are along concordant;
The low frequency timing module, be used for carrying out timing by low-frequency clock, and triggering terminal enters sleep pattern, when determining by described low-frequency clock timing to the second timing point, stop to carry out timing by described low-frequency clock, wherein, the Second Edge of described the second timing point and described low-frequency clock is along concordant, the difference T1 of the duration of the duration of described the second timing point and described the first timing point configures according to described sleep cycle T0, and the difference of T0 and T1 is less than the first pre-set threshold value;
The second high frequency timing module, be used for by using described high frequency clock to carry out timing, when determining to arrive the 3rd timing point by described high frequency clock timing, stop to carry out timing by described high frequency clock, the duration of described the 3rd timing point is the sleep cycle T0 of described terminal;
The work trigger module is used for triggering described terminal and enters mode of operation, and beginning is carried out data interaction with the base station.
Preferably, described device also comprises:
The time distribution module is for the difference T1 that configures the duration of the first timing point and the second timing point according to the sleep cycle T0 of described terminal;
Described time distribution module comprises:
The first number is determined submodule, is used for the time-count cycle divided by low-frequency clock with sleep cycle T0, obtains low-frequency clock the first number of time-count cycle;
The second number is determined submodule, be used for determining according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value the second number of the time-count cycle of low-frequency clock, with the product of described the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
Preferably, described the first high frequency timing module, concrete be used for when timing to time zero after, when first edge of described low-frequency clock is concordant, definite when arriving the first timing point by described high frequency clock timing.
Preferably, described the first high frequency timing module, concrete be used for when timing to time zero after, when N edge of described low-frequency clock was concordant, definite when arriving the first timing point by described high frequency clock timing, wherein, N was positive integer;
Described device also comprises, the edge determination module, the difference T1 that is used for the duration of definite duration according to described sleep cycle T0 and the second timing point and described the first timing point, determine the first side edge of described low-frequency clock, described first side is along being after the time zero, N edge of described low-frequency clock;
Described edge determination module comprises:
The difference calculating sub module is used for calculating the difference of difference T1 that described sleep cycle T0 deducts the duration of the duration of the second timing point and described the first timing point;
Submodule is chosen at the edge, is used for the described time zero of selected distance and is no more than the edge of T0 and T1 difference as the first side edge of described low-frequency clock.
Preferably, described the first high frequency timing module by described high frequency clock to described low-frequency clock sample determine timing to the first side of described low-frequency clock along the first mutually concordant timing point, described low frequency timing module by described high frequency clock to described low-frequency clock sample determine timing to the Second Edge of described low-frequency clock along the second mutually concordant timing point.
Compared with prior art, the present invention has the following advantages:
According to the embodiment of the invention, after receiving the instruction that enters sleep pattern, by the high frequency clock timing to the first timing point, then begin to carry out timing by low-frequency clock, go forward side by side into sleep pattern, when the low-frequency clock timing arrives the second timing point, carry out timing by high frequency clock, until arrive the 3rd timing point, triggering terminal enters sleep pattern, begins to recover the data interaction with the base station.Because the second timing point that the first timing point that the timing of low-frequency clock begins and timing finish is the edge of low-frequency clock, therefore, low-frequency clock timing in sleep pattern is accurately, in the part that does not arrive the low-frequency clock edge and the time after reaching T1 by the high frequency clock timing, thereby can guarantee timing accuracy under the whole sleep pattern; In the situation that accurate timing, enter sleep pattern from certain subframe border of receive data, and sleep cycle is the integral multiple of subframe, after then can guaranteeing to finish sleep cycle, receive data still is the subframe border.
In sum, adopt the method for the embodiment of the invention to need not finishing to carry out re-synchronization between the sleep pattern, and the difference of the timing duration T1 of sleep cycle T0 and low-frequency clock is less than the first pre-set threshold value, than the time of the re-synchronization of Millisecond, the embodiment of the invention can prolong the sleep cycle of terminal, reduces the power consumption of terminal.
And, adopting the method for the embodiment of the invention, self-defined DRX sleep cycle length as required can arrange the actual length of one's sleep according to time of sleep cycle, for practical application provides larger flexibility in register.
Description of drawings
Fig. 1 is the flow chart of a kind of terminal sleep periodic Control of the present invention embodiment of the method 1;
Fig. 2 is the flow chart of a kind of terminal sleep periodic Control of the present invention embodiment of the method 2;
Fig. 3 is the structured flowchart of a kind of terminal sleep periodic Control of the present invention device embodiment 1;
Fig. 4 is the structured flowchart of a kind of terminal sleep periodic Control of the present invention device embodiment 2;
Fig. 5 is the timing schematic diagram of terminal sleep pattern in the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
With reference to figure 1, show the flow chart of a kind of terminal sleep periodic Control embodiment of the method 1 of the present invention, specifically can may further comprise the steps:
Terminal can enter sleep pattern when not needing monitor channel information, and generates the instruction that enters sleep pattern, also can submit the instruction that enters sleep pattern to by the interface that terminal presets by the user.Comprise two elapsed time clocks in the terminal, one is the low frequency elapsed time clock, and one is the high frequency elapsed time clock, in the embodiment of the invention, after receiving the instruction that enters sleep pattern, carries out timing by high frequency clock.Because terminal is carried out timing not entering sleep pattern when in running order by high frequency clock, therefore, after receiving the instruction that enters sleep pattern, continue to carry out timing by high frequency clock.
The timing time of high frequency clock is as the criterion with the first timing point, arrive can use low-frequency clock instead behind the first timing point and begin timing, and triggering terminal enters sleep pattern.Wherein, the first timing point is the first side edge of low-frequency clock, the first side edge can be rising edge or the trailing edge of low-frequency clock, because when receiving the instruction that enters sleep pattern, mostly can't be in the edge of low-frequency clock in the situation, in the situation that non-edge enters sleep pattern, adopting the low-frequency clock timing, can cause the timing uncertainty under the sleep pattern true, the embodiment of the invention enters sleep pattern from the edge of low-frequency clock, thereby can guarantee that the timing of low-frequency clock is accurately when entering sleep pattern.
In embodiments of the present invention, the first timing point is that the edge of low-frequency clock can be sampled definite by high frequency clock to low-frequency clock.
Under sleep pattern, terminal is carried out timing by low-frequency clock, and the timing end point of low-frequency clock is as the criterion with the second timing point, and wherein, the second timing point is the Second Edge edge of low-frequency clock, and the Second Edge edge can be rising edge or the trailing edge of low-frequency clock.In embodiments of the present invention, the second timing point is that the edge of low-frequency clock can be sampled definite by high frequency clock to low-frequency clock.
Wherein, the timing duration of the first timing point refers to, from receiving the instruction that enters sleep pattern and bringing into use the time zero of high frequency clock timing, to the time between the first timing point; Equally, the timing duration of the second timing point refers to, from receiving the instruction that enters sleep pattern and bringing into use the time zero of high frequency clock timing, to the time between the second timing point.
In the embodiment of the invention, first side edge and Second Edge are along being rising edge, or be trailing edge, in this case, the difference of the duration of the duration of the first timing point and the second timing point is the low-frequency clock integral multiple of time-count cycle, first side edge and Second Edge along also can one be that one of rising edge is trailing edge, in this case, the difference of the duration of the duration of the first timing point and the second timing point is that the integral multiple of low-frequency clock time-count cycle is added half period.Adopt another edge of low-frequency clock timing tremendously low frequency clock, can guarantee that the low-frequency clock timing in sleep pattern is accurately.
As shown in Figure 5, provided the timing schematic diagram of terminal sleep pattern in the embodiment of the invention.Upwards arrow logo among the SUBFRAME_BOUNDARY of Fig. 5 top is the subframe border of data, mid portion corresponds to high frequency clock (SYS_CLK, system clock) timing schematic diagram, below low-frequency clock (Real-Time Clock, RTC) timing schematic diagram, for fear of the problem that synchronizing information is lost, sleep cycle (DRX SLEEP INTERVAL) finishes on the subframe border from the subframe border.
The sleep cycle T0 of B for arranging, that the starting point of sleep cycle is corresponding is certain subframe a of receive data, corresponding the time point b of low-frequency clock, point b is not the edge of low-frequency clock, if adopt the mode of background technology, the problem that low-frequency clock timing uncertainty needing really to cause the re-synchronization data can occur.If begin to adopt the low-frequency clock timing from certain edge c, and stop the low-frequency clock timing at another edge d, thereby can guarantee the accuracy of the timing duration (being time B shown in Figure 5) of low-frequency clock.
In the embodiment of the invention, can be according to concrete business or environmental demand, preset sleep cycle T0 for terminal, because sleep cycle T0 all can be set to the integral multiple of subframe, if enter sleep pattern from certain subframe border of current receive data, in the situation that accurate timing, after just can guaranteeing to finish sleep cycle, receive data is the subframe border still, need not to finish in advance sleep pattern and carries out re-synchronization, can guarantee the accuracy of data receiver.
Wherein, time zero first timing point of low-frequency clock and the difference T1 of timing end point the second timing point are the timing time of low-frequency clock, be terminal actual length of one's sleep, T1 is according to the sleep cycle T0 configuration of terminal, and when distributing the timing time of low-frequency clock, need satisfy the difference of timing time T1 of sleep cycle T0 and low-frequency clock less than the first pre-set threshold value, carry out in the background technology the remaining length of one's sleep behind the re-synchronization thereby be longer than the actual length of one's sleep that can guarantee terminal, thereby can reduce power consumption of terminal, prolong the stand-by time of terminal.
In the embodiment of the invention, the difference T1 of the duration of the first timing point and the second timing point can be the low-frequency clock integral multiple of time-count cycle, can distribute by following steps the difference T1 of the duration of the first timing point and the second timing point:
Substep S11, with the time-count cycle of sleep cycle T0 divided by low-frequency clock, obtain low-frequency clock the first number of time-count cycle;
Substep S12, determine the second number of the time-count cycle of low-frequency clock according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value, with the product of the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
At first, can be with the time-count cycle of sleep cycle T0 divided by low-frequency clock, the merchant that obtains of being divided by is the periodicity that low-frequency clock at most can timing, i.e. the first number of low-frequency clock time-count cycle.For example, sleep cycle T0 is 10ms, and can obtain the result divided by cycle of low-frequency clock is 327.68, namely the merchant is 327, explanation in sleep cycle low-frequency clock at most can timing 327 complete cycles, remainder be 0.68 explanation except complete cycle, low-frequency clock can also 0.68 cycle of timing.
Because certain edge from low-frequency clock in the embodiment of the invention begins timing, edge herein can be rising edge or trailing edge, and when entering sleep pattern, certain edge apart from low-frequency clock may also have a segment distance, if the length of this segment distance is greater than remainder, then low-frequency clock can't carry out timing according to maximum periodicities, need to distribute to the periodicity of low-frequency clock timing.
For example, the rising edge of current distance low-frequency clock also has 0.1 cycle, in 0.1 cycle that adopt first the complete low-frequency clock of high frequency clock timing this moment, can also continue to adopt 327 cycles of low-frequency clock timing; If but the rising edge of current distance low-frequency clock also has 0.8 cycle, then adopt 0.8 cycle of the complete low-frequency clock of high frequency clock timing, low-frequency clock can't timing 327 complete cycles.
Therefore, in embodiments of the present invention, can determine according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value the second number of the time-count cycle of low-frequency clock, namely, maximum periodicities are deducted a preset value, thereby the timing time that guarantees low-frequency clock is complete cycle.In concrete realization, the second pre-set threshold value can be set to 2, can guarantee that the timing time of low-frequency clock is complete cycle on the one hand, and the opposing party can make the timing time of low-frequency clock long, and the actual length of one's sleep of terminal also can be long.
After having determined the number of time-count cycle of low-frequency clock, with the second number and low-frequency clock multiply each other the difference T1 of the duration that can obtain the first timing point and the second timing point, i.e. the timing time T1 of low-frequency clock.
In the embodiment of the invention, timing operation can be finished by the timer of terminal, after distributing T1, can deposit the difference T1 of the duration of the first timing point and the second timing point in the register of timer in, also can further deposit the difference of T0 and T1 in, i.e. the total timing time of high frequency clock.
In concrete realization, when the difference of the timing time T1 of sleep cycle T0 and low-frequency clock is no less than one-period, high frequency clock can corresponding timing can have multiple choices to the edge of low-frequency clock, namely, first side be along can being after the time zero, first edge of low-frequency clock, and first side is along also can being after the time zero, N edge of low-frequency clock, N is positive integer.
As shown in Figure 5, after foundation the second pre-set threshold value draws the interior number of cycles of time B, take rising edge as example, the first side edge that can select first rising edge behind the b point to begin timing as low-frequency clock also can select the c point to begin the first side edge of timing as low-frequency clock.
In order to prolong as far as possible the actual length of one's sleep of terminal, namely prolong the timing time of low-frequency clock, can use first edge of high frequency clock timing tremendously low frequency clock, be that the first side edge is for after the time zero, first edge of low-frequency clock, thereby so that reach the longest the actual length of one's sleep of terminal, the energy consumption of terminal is minimum.In concrete realization, it is unfixing from the time at first edge of low-frequency clock that terminal enters the start point distance of sleep pattern at every turn, and namely the size of the A1 among Fig. 5 is unfixed.
After the low-frequency clock timing finishes, can continue to carry out timing by high frequency clock, although this moment, terminal was not in sleep, but still be in the sleep cycle, therefore, after step 103 medium-high frequency clock begins timing, can't triggering terminal enter mode of operation, but when high frequency clock arrived the 3rd timing point, triggering terminal entered mode of operation.
Wherein, the timing duration of the 3rd timing point refers to, from receiving the instruction that enters sleep pattern and bringing into use the time zero of high frequency clock timing, to the time between the 3rd timing point.The duration of the 3rd timing point is sleep cycle T0, and namely total timing time of high frequency clock and low-frequency clock is sleep cycle T0.
As shown in Figure 5, sleep cycle is divided into three phases, and A1 and A2 are the timing time of high frequency clock, and A1 is high frequency clock phase I timing time, and A2 is high frequency clock second stage timing time, and B is the timing time of low-frequency clock.When arriving the 3rd timing point, the high frequency clock timing that is to say in sleep cycle, total timing time of high frequency clock reaches A, or the timing time of high frequency clock second stage reaches A2, this moment, triggering terminal was waken up from sleep pattern, enter mode of operation, and can begin monitor channel information, recover reception or transmission to base station data.
In concrete realization, a kind of preferred mode can for, when step 101 medium-high frequency clock timing tremendously low frequency clock edge, record the timing time A1 of high frequency clock in this stage, then according to the difference A of sleep cycle T0 and low-frequency clock timing time T1, subtract each other with the time A1 of high frequency clock phase I, obtain high frequency clock second stage timing time A2, the time point that A2 finishes is the 3rd timing point, and it is the wake-up terminal that high frequency clock arrives A2 in the second stage timing.
Another kind of preferred mode can for, when step 101 medium-high frequency clock timing tremendously low frequency clock edge, record the timing time A1 of high frequency clock in this stage, when the low-frequency clock timing, record the timing time B of low-frequency clock in this stage, then according to the difference of the length of one's sleep and A1 and B, obtain high frequency clock second stage timing time A2, it is the wake-up terminal that high frequency clock arrives A2 in the second stage timing.
Terminal is by the receiver system receive data, therefore as long as A2 finishes before receiver ready, and that the high frequency clock source need to guarantee before the A2 stage begins timing is ready, as shown in Figure 5, high frequency clock finishes the previous cycle in the B stage, and namely to begin the previous cycle ready the A2 stage.
According to the embodiment of the invention, in the part that does not arrive the low-frequency clock edge and the time after reaching low frequency another edge in being by the high frequency clock timing, thereby can guarantee timing accuracy under the whole sleep pattern; In the situation that accurate timing, enter sleep pattern from certain subframe border of receive data, and sleep cycle is the integral multiple of subframe, after then can guaranteeing to finish sleep cycle, receive data still is the subframe border, avoid the re-synchronization after UE wakes up, prolonged system's sleep cycle, be conducive to system power dissipation optimization.
And, adopting the method for the embodiment of the invention, self-defined DRX sleep cycle length as required can arrange the actual length of one's sleep according to time of sleep cycle, for practical application provides larger flexibility in register.
With reference to figure 2, show the flow chart of a kind of terminal sleep periodic Control embodiment of the method 2 of the present invention, specifically can may further comprise the steps:
Among the embodiment 1 preferably, the first timing point is that first side with low-frequency clock is along concordant, first side is along being after the time zero, first edge of low-frequency clock, first edge of high frequency clock timing tremendously low frequency clock, then begin to carry out timing by low-frequency clock, because when the difference of the timing time T1 of sleep cycle T0 and low-frequency clock is no less than one-period, high frequency clock can corresponding timing can have multiple choices to the edge of low-frequency clock, therefore, provided definite method of the first timing point in the present embodiment, it is definite method at the low-frequency clock edge that begins timing, the edge of N edge low-frequency clock can be rising edge or the trailing edge of low-frequency clock, and step 202 can comprise:
Substep S21, calculate the difference of difference T1 that sleep cycle T0 deducts the duration of the duration of the second timing point and the first timing point;
Substep S22, selected distance time zero are no more than the edge of T0 and T1 difference as the first side edge of low-frequency clock.
The difference of the duration of the duration of the second timing point and the first timing point is the timing time T1 of low-frequency clock, the difference of the timing time T1 of sleep cycle T0 and low-frequency clock is the timing time summation of high frequency clock in sleep cycle, when the timing time of high frequency clock surpasses one-period, selection that can the edge can have various ways, only needs to satisfy the edge that choose and is no more than above-mentioned difference apart from the current time and gets final product.
As shown in Figure 5, the difference of the timing time T1 of sleep cycle T0 and low-frequency clock is the length of A1 and A2 time, be about 2.8 cycles, A2 is 1.3 cycles, A2 is 1.5 cycles, take rising edge as example, first rising edge is 0.3 cycle apart from the current time, second rising edge that is to say that the c point is 1.3 cycles apart from the current time, the 3rd rising edge that is to say that the c point is 2.3 cycles apart from the current time, the 4th rising edge that is to say that the c point is 3.3 cycles apart from the current time, therefore, can select to be no more than first of 2.8 cycles of difference, second or the 3rd rising edge be as the time that begins by the low-frequency clock timing, selected second rising edge c point conduct to begin time by the low-frequency clock timing among Fig. 5.
In the embodiment of the invention, the edge of low-frequency clock can be sampled definite by high frequency clock to low-frequency clock.
According to the embodiment of the invention, after receiving the instruction that enters sleep pattern, by the high frequency clock timing to the first timing point, then begin to carry out timing by low-frequency clock, go forward side by side into sleep pattern, when the low-frequency clock timing arrives the second timing point, carry out timing by high frequency clock, until arrive the 3rd timing point, triggering terminal enters sleep pattern, begins to recover the data interaction with the base station.Because the timing of low-frequency clock begins to be with the timing end edge of low-frequency clock, therefore, low-frequency clock timing in sleep pattern is accurately, in the part that does not arrive the low-frequency clock edge and the time after reaching T1 by the high frequency clock timing, thereby can guarantee timing accuracy under the whole sleep pattern; In the situation that accurate timing, enter sleep pattern from certain subframe border of receive data, and sleep cycle is the integral multiple of subframe, after then can guaranteeing to finish sleep cycle, receive data still is the subframe border.
In sum, adopt the method for the embodiment of the invention to need not finishing to carry out re-synchronization between the sleep pattern, and the difference of the timing duration T1 of sleep cycle T0 and low-frequency clock is less than the first pre-set threshold value, than the time of the re-synchronization of Millisecond, the embodiment of the invention can prolong the sleep cycle of terminal, reduces the power consumption of terminal.
And, adopting the method for the embodiment of the invention, self-defined DRX sleep cycle length as required can arrange the actual length of one's sleep according to time of sleep cycle, for practical application provides larger flexibility in register.
For embodiment of the method, for simple description, therefore it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the specification all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
With reference to figure 3, show the structured flowchart of a kind of terminal sleep periodic Control device embodiment 1 of the present invention, specifically can comprise with lower module:
The first high frequency timing module 301 after being used for receiving the instruction that enters sleep pattern, carries out timing by high frequency clock, when determining by high frequency clock timing to the first timing point, stop to carry out timing by high frequency clock, wherein, the first side of the first timing point and low-frequency clock is along concordant;
Low frequency timing module 302 links to each other with the first high frequency timing module 301, when low frequency timing module 302 arrives the first timing point for 301 timing of the first high frequency timing module, carry out timing by low-frequency clock, and triggering terminal enters sleep pattern, when determining by low-frequency clock timing to the second timing point, stop to carry out timing by low-frequency clock, wherein, the first side of the first timing point and low-frequency clock is along concordant, the difference T1 of the duration of the duration of the second timing point and the first timing point is according to sleep cycle T0 configuration, and the difference of T0 and T1 is less than the first pre-set threshold value;
The second high frequency timing module 303 links to each other with low frequency timing module 302, the second high frequency timing module 303 is used for when 302 timing of low frequency timing module arrive the second timing point, by the high frequency clock timing, when determining to arrive the 3rd timing point by the high frequency clock timing, stop to carry out timing by high frequency clock, the duration of the 3rd timing point is the sleep cycle T0 of terminal;
Work trigger module 304 links to each other with the second high frequency timing module 303, and work trigger module 304 is used for triggering terminal and enters mode of operation, and beginning is carried out data interaction with the base station.
In the embodiment of the invention, the first high frequency timing module, concrete be used for when timing to time zero after, when first edge of low-frequency clock is concordant, definite when arriving the first timing point by the high frequency clock timing.
In the embodiment of the invention, the first high frequency timing module can timing to first timing point concordant with low-frequency clock rising edge or trailing edge, the low frequency timing module can timing to second timing point concordant with low-frequency clock rising edge or trailing edge.
In the embodiment of the invention, the first high frequency timing module can by high frequency clock to low-frequency clock sample determine timing to the first side of low-frequency clock along the first mutually concordant timing point, the low frequency timing module can by high frequency clock to low-frequency clock sample determine timing to the Second Edge of low-frequency clock along the second mutually concordant timing point.
With reference to figure 4, show the structured flowchart of a kind of terminal sleep periodic Control device embodiment 2 of the present invention, specifically can comprise with lower module:
Time distribution module 401, for the difference T1 that configures the duration of the first timing point and the second timing point according to the sleep cycle T0 of terminal, wherein, the difference of T0 and T1 is less than the first pre-set threshold value;
Edge determination module 402 links to each other with time distribution module 401, edge determination module 402 is used for the difference T1 according to the duration of the duration of the sleep cycle T0 of time distribution module 401 distribution and the second timing point and the first timing point, determine the first side edge of low-frequency clock, first side is along being after the time zero, N edge of low-frequency clock, N is positive integer;
The first high frequency timing module 403 links to each other with edge determination module 402, after the first high frequency timing module 403 is used for receiving the instruction that enters sleep pattern, carry out timing by high frequency clock, when determining by high frequency clock timing to the first timing point, stop to carry out timing by high frequency clock, wherein, the first side of the low-frequency clock determined of the first timing point and edge determination module 402 is along concordant;
Low frequency timing module 404 links to each other with the first high frequency timing module 403 with time distribution module 401, when low frequency timing module 404 arrives the first timing point for 403 timing of the first high frequency timing module, carry out timing by low-frequency clock, and triggering terminal enters sleep pattern, when determining by low-frequency clock timing to the second timing point, stop to carry out timing by low-frequency clock, wherein, the Second Edge of the second timing point and low-frequency clock is along concordant, and the difference T1 of the duration of the duration of the second timing point and the first timing point is determined by time distribution module 401;
The second high frequency timing module 405 links to each other with low frequency timing module 404, high frequency timing module 405 is used for when 404 timing of low frequency timing module arrive the second timing point, carry out timing by high frequency clock, when determining to arrive the 3rd timing point by the high frequency clock timing, stop to carry out timing by high frequency clock, the duration of the 3rd timing point is the sleep cycle T0 of terminal;
Work trigger module 406 links to each other with the second high frequency timing module 405, and when work trigger module 406 arrived the 3rd timing point for 405 timing of the second high frequency timing module, triggering terminal entered mode of operation, and beginning is carried out data interaction with the base station.
In the embodiment of the invention, the first high frequency timing module, concrete be used for when timing to time zero after, when N edge of low-frequency clock was concordant, definite when arriving the first timing point by the high frequency clock timing, wherein, N was positive integer.
In the embodiment of the invention, time distribution module 401 can comprise:
The first number is determined submodule, is used for the time-count cycle divided by low-frequency clock with sleep cycle T0, obtains low-frequency clock the first number of time-count cycle;
The second number determines that submodule and the first number determine that submodule links to each other, the first number of the low-frequency clock time-count cycle that the second number determines that submodule is used for determining according to the first number that submodule determines and the difference of the second pre-set threshold value are determined the second number of the time-count cycle of low-frequency clock, with the product of the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
In the embodiment of the invention, the edge determination module can comprise:
The difference calculating sub module determines that with the second number submodule links to each other, and the difference calculating sub module be used for to be calculated the difference of difference T1 that sleep cycle T0 deducts the duration of the duration of the second timing point and the first timing point;
The edge is chosen submodule and is linked to each other with the difference calculating sub module, and the edge is chosen submodule and is no more than the edge of the definite T0 of difference calculating sub module and T1 difference as the first side edge of low-frequency clock for the selected distance time zero.
In the embodiment of the invention, the first high frequency timing module timing is to first timing point concordant with low-frequency clock rising edge or trailing edge, and the timing of low frequency timing module is to second timing point concordant with low-frequency clock rising edge or trailing edge.
In the embodiment of the invention, the first high frequency timing module by high frequency clock to low-frequency clock sample determine timing to the first side of low-frequency clock along the first mutually concordant timing point, the low frequency timing module by high frequency clock to low-frequency clock sample determine timing to the Second Edge of low-frequency clock along the second mutually concordant timing point.
Because described device embodiment is substantially corresponding to aforementioned embodiment of the method illustrated in figures 1 and 2, therefore not detailed part in the description of the present embodiment can referring to the related description in the previous embodiment, just not given unnecessary details at this.
The present invention can be used in numerous general or special purpose computingasystem environment or the configuration.For example: personal computer, server computer, handheld device or portable set, plate equipment, multicomputer system, the system based on microprocessor, set top box, programmable consumer-elcetronics devices, network PC, minicom, mainframe computer, comprise distributed computing environment (DCE) of above any system or equipment etc.
The present invention can describe in the general context of the computer executable instructions of being carried out by computer, for example program module.Usually, program module comprises the routine carrying out particular task or realize particular abstract data type, program, object, assembly, data structure etc.Also can in distributed computing environment (DCE), put into practice the present invention, in these distributed computing environment (DCE), be executed the task by the teleprocessing equipment that is connected by communication network.In distributed computing environment (DCE), program module can be arranged in the local and remote computer-readable storage medium that comprises memory device.
In this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Above to a kind of terminal sleep periodic Control method provided by the present invention, and, a kind of terminal sleep periodic Control device is described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a terminal sleep periodic Control method is characterized in that, comprising:
After receiving the instruction that enters sleep pattern, carry out timing by high frequency clock;
When determining to arrive the first timing point by described high frequency clock timing, carry out timing by low-frequency clock, and triggering terminal enters sleep pattern, wherein, the first side of described the first timing point and described low-frequency clock is along concordant;
When determining to arrive the second timing point by described low-frequency clock timing, carry out timing by described high frequency clock, wherein, the Second Edge of described the second timing point and described low-frequency clock is along concordant, the difference T1 of the duration of the duration of described the second timing point and described the first timing point is according to the sleep cycle T0 configuration of described terminal, and the difference of T0 and T1 is less than the first pre-set threshold value;
When determining to arrive the 3rd timing point by described high frequency clock timing, triggering terminal enters mode of operation, and beginning is carried out data interaction with the base station, and wherein, the duration of described the 3rd timing point is described sleep cycle T0.
2. method according to claim 1 is characterized in that,, comprising according to the difference T1 that the sleep cycle T0 of described terminal configures the duration of the first timing point and the second timing point by following steps:
With the time-count cycle of sleep cycle T0 divided by low-frequency clock, obtain low-frequency clock the first number of time-count cycle;
Determine the second number of the time-count cycle of low-frequency clock according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value, with the product of described the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
3. method according to claim 1 is characterized in that, described first side is along being after the time zero, first edge of described low-frequency clock.
4. method according to claim 2 is characterized in that, described first side is along being after the time zero, N edge of described low-frequency clock, and N is positive integer;
Described method also comprises, determines the first side edge of described low-frequency clock by following steps:
Calculate the difference of difference T1 that described sleep cycle T0 deducts the duration of the duration of the second timing point and described the first timing point;
The described time zero of selected distance is no more than the edge of T0 and T1 difference as the first side edge of described low-frequency clock.
5. method according to claim 1 is characterized in that, the first side edge of described low-frequency clock or Second Edge are along sampling definite by described high frequency clock to described low-frequency clock.
6. a terminal sleep periodic Control device is characterized in that, comprising:
The first high frequency timing module, after being used for receiving the instruction that enters sleep pattern, carry out timing by high frequency clock, when determining by described high frequency clock timing to the first timing point, stop to carry out timing by described high frequency clock, wherein, described the first timing point and the first side of described low-frequency clock are along concordant;
The low frequency timing module, be used for carrying out timing by low-frequency clock, and triggering terminal enters sleep pattern, when determining by described low-frequency clock timing to the second timing point, stop to carry out timing by described low-frequency clock, wherein, the Second Edge of described the second timing point and described low-frequency clock is along concordant, the difference T1 of the duration of the duration of described the second timing point and described the first timing point configures according to described sleep cycle T0, and the difference of T0 and T1 is less than the first pre-set threshold value;
The second high frequency timing module, be used for by using described high frequency clock to carry out timing, when determining to arrive the 3rd timing point by described high frequency clock timing, stop to carry out timing by described high frequency clock, the duration of described the 3rd timing point is the sleep cycle T0 of described terminal;
The work trigger module is used for triggering described terminal and enters mode of operation, and beginning is carried out data interaction with the base station.
7. device according to claim 6 is characterized in that, also comprises:
The time distribution module is for the difference T1 that configures the duration of the first timing point and the second timing point according to the sleep cycle T0 of described terminal;
Described time distribution module comprises:
The first number is determined submodule, is used for the time-count cycle divided by low-frequency clock with sleep cycle T0, obtains low-frequency clock the first number of time-count cycle;
The second number is determined submodule, be used for determining according to the difference of the first number of low-frequency clock time-count cycle and the second pre-set threshold value the second number of the time-count cycle of low-frequency clock, with the product of described the second number and the low-frequency clock difference T1 as the duration of the first timing point and the second timing point.
8. device according to claim 6, it is characterized in that, described the first high frequency timing module, concrete be used for when timing extremely with time zero after, when first edge of described low-frequency clock is concordant, when determining to arrive the first timing point by described high frequency clock timing.
9. device according to claim 7 is characterized in that, described the first high frequency timing module, concrete be used for when timing to time zero after, when N edge of described low-frequency clock is concordant, definite when arriving the first timing point by described high frequency clock timing, wherein, N is positive integer;
Described device also comprises, the edge determination module, the difference T1 that is used for the duration of definite duration according to described sleep cycle T0 and the second timing point and described the first timing point, determine the first side edge of described low-frequency clock, described first side is along being after the time zero, N edge of described low-frequency clock;
Described edge determination module comprises:
The difference calculating sub module is used for calculating the difference of difference T1 that described sleep cycle T0 deducts the duration of the duration of the second timing point and described the first timing point;
Submodule is chosen at the edge, is used for the described time zero of selected distance and is no more than the edge of T0 and T1 difference as the first side edge of described low-frequency clock.
10. device according to claim 6, it is characterized in that, described the first high frequency timing module by described high frequency clock to described low-frequency clock sample determine timing to the first side of described low-frequency clock along the first mutually concordant timing point, described low frequency timing module by described high frequency clock to described low-frequency clock sample determine timing to the Second Edge of described low-frequency clock along the second mutually concordant timing point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310206822.0A CN103327587B (en) | 2013-05-29 | 2013-05-29 | A kind of terminal sleep cycle control methods and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310206822.0A CN103327587B (en) | 2013-05-29 | 2013-05-29 | A kind of terminal sleep cycle control methods and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103327587A true CN103327587A (en) | 2013-09-25 |
| CN103327587B CN103327587B (en) | 2016-12-07 |
Family
ID=49196047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310206822.0A Expired - Fee Related CN103327587B (en) | 2013-05-29 | 2013-05-29 | A kind of terminal sleep cycle control methods and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103327587B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105703749A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Low-power consumption and accurate sleep timer circuit and method |
| CN106376065A (en) * | 2016-08-30 | 2017-02-01 | 重庆邮电大学 | Mechanism for dynamically adjusting turn-off window length of base station based on POMDP (Partially Observable Markov Decision Process) |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| CN107562172A (en) * | 2016-07-01 | 2018-01-09 | 三星电子株式会社 | IC apparatus and electronic system |
| CN111448829A (en) * | 2017-12-19 | 2020-07-24 | 华为技术有限公司 | User node, network node, and method for wireless communication |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2340446A1 (en) * | 1998-08-14 | 2000-02-24 | Qualcomm Incorporated | Synchronisation of a low power clock in a wireless communication device |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| US20060205382A1 (en) * | 2005-03-10 | 2006-09-14 | Wang Michael M | Apparatus and method for determining sleep clock timing |
| CN102821446A (en) * | 2012-06-04 | 2012-12-12 | 江苏大学 | Synchronous awaking mechanism of long-term and deep dormant wireless sensor network |
-
2013
- 2013-05-29 CN CN201310206822.0A patent/CN103327587B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2340446A1 (en) * | 1998-08-14 | 2000-02-24 | Qualcomm Incorporated | Synchronisation of a low power clock in a wireless communication device |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| US20060205382A1 (en) * | 2005-03-10 | 2006-09-14 | Wang Michael M | Apparatus and method for determining sleep clock timing |
| CN102821446A (en) * | 2012-06-04 | 2012-12-12 | 江苏大学 | Synchronous awaking mechanism of long-term and deep dormant wireless sensor network |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105703749A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Low-power consumption and accurate sleep timer circuit and method |
| CN105703749B (en) * | 2014-11-24 | 2018-07-20 | 中国科学院沈阳自动化研究所 | A kind of accurate doze output circuit of low-power consumption and method |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| CN107562172A (en) * | 2016-07-01 | 2018-01-09 | 三星电子株式会社 | IC apparatus and electronic system |
| CN107562172B (en) * | 2016-07-01 | 2021-08-13 | 三星电子株式会社 | Integrated circuit device and electronic system |
| CN106376065A (en) * | 2016-08-30 | 2017-02-01 | 重庆邮电大学 | Mechanism for dynamically adjusting turn-off window length of base station based on POMDP (Partially Observable Markov Decision Process) |
| CN106376065B (en) * | 2016-08-30 | 2019-08-20 | 重庆邮电大学 | A kind of mechanism based on POMDP dynamic adjustment base station shutdown length of window |
| CN111448829A (en) * | 2017-12-19 | 2020-07-24 | 华为技术有限公司 | User node, network node, and method for wireless communication |
| CN111448829B (en) * | 2017-12-19 | 2021-06-29 | 华为技术有限公司 | User node, network node, and method for wireless communication |
| US11115926B2 (en) | 2017-12-19 | 2021-09-07 | Huawei Technologies Co., Ltd. | User node, a network node and methods for wireless communication |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103327587B (en) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103327587A (en) | Method and device for controlling sleep cycle of terminal | |
| CN100517215C (en) | Method and apparatus for timing and event processing in wireless systems | |
| CN101507125B (en) | System frame number (SFN) evaluator | |
| EP3340693B1 (en) | Method and apparatus to controlling sleep time for bluetooth device and bluetooth enabled device | |
| CN109067394B (en) | On-chip clock calibration device and calibration method | |
| CN102412957B (en) | High-precision synchronous clock adjusting method | |
| CN103118188A (en) | Application heartbeat cycle adjusting method and device, and terminal | |
| JP2009515494A (en) | Apparatus and method for estimating sleep clock frequency | |
| CN106304317B (en) | The compensation method of sleep awakening timing offset and electronic equipment | |
| US9974014B2 (en) | System and method for maintaining synchronization with low power endpoints in a time synchronized channel hopping network | |
| US9477293B2 (en) | Embedded controller for power-saving and method thereof | |
| WO2014051788A1 (en) | Systems and methods for time synchronization | |
| RU2579716C2 (en) | Correction of low-accuracy clock generator | |
| CN106255184A (en) | A kind of data transmission method and terminal unit | |
| CN102957403A (en) | Integrated circuit device, synchronisation module, electronic device and method therefor | |
| CN103389644A (en) | Timing system and timing method | |
| Hauweele et al. | Toward accurate clock drift modeling in wireless sensor networks simulation | |
| JP6394452B2 (en) | Wireless communication apparatus, wireless communication method, and program | |
| US20220046538A1 (en) | Timing precision maintenance with reduced power during system sleep | |
| CN102368825A (en) | Energy-saving control method of 3D glasses | |
| EP2730133B1 (en) | Technique for maintaining a radio time base | |
| Terraneo et al. | Jitter-compensated VHT and its application to WSN clock synchronization | |
| CN104597964A (en) | Time server | |
| CN100358383C (en) | Method of improving preciseness of mobile communication terminal low frequency crystal oscillator | |
| CN104735772B (en) | A kind of device and method of Timing Synchronization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161207 Termination date: 20200529 |