CN103326722B - A kind of adaptive sample value estimating circuit and method - Google Patents
A kind of adaptive sample value estimating circuit and method Download PDFInfo
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- CN103326722B CN103326722B CN201210072207.0A CN201210072207A CN103326722B CN 103326722 B CN103326722 B CN 103326722B CN 201210072207 A CN201210072207 A CN 201210072207A CN 103326722 B CN103326722 B CN 103326722B
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Abstract
The invention provides a kind of adaptive sample value estimating circuit and method, wherein, the circuit includes phase error detection module, de-noise module, digital control oscillation module and sample value estimation module；Phase error detection module, for calculating phase error U (k) according to the estimation sample value y (k) of adc circuit output signal, and it is integer that U (k), which is sent to de-noise module, k >=0, k,；De-noise module, for filtering out U (k) high frequency noise components, stable phase error W (k) is obtained, and W (k) is sent to digital control oscillation module；Digital control oscillation module, for calculating integer estimation pointer m according to W (k)kWith decimal estimation pointer μk, and by mkAnd μkSend to sample value estimation module；Sample value estimation module, for according to mkPositioning participates in the output signal of the adc circuit of sample value estimation, according to μkThe coefficient of the output signal is determined, obtains estimating sample value y (k) using the output signal, and y (k) is sent to phase error detection module.The present invention reduces the frequency error of the signal exported through ADC sample circuits and phase error.
Description
Technical field
The present invention relates to the error concealment field of analog to digital conversion circuit sampled signal, more particularly to a kind of adaptive sample value to estimate
Count circuit and method.
Background technology
In (DWDM) transmission system of the intensive multiplexed optical wave based on palarization multiplexing difference quadrature phase shift keying (PM-DQPSK)
In system, transmission of the signal through long-distance and by dispersion (CD), the influence of polarization mode dispersion (PMD) produces change, so as to make
The optical signal gross distortion received into receiving terminal.Therefore, receiving terminal is changed to electricity to optical signal progress photoelectric conversion module
After signal, it is also necessary to the processing such as be filtered to electric signal and could realize information is properly received.
In Electric signal processing, Digital Signal Processing is one of conventional processing means, is needed before Digital Signal Processing
Analog-to-digital conversion ADC sample circuits are utilized, but during ADC is sampled, because ADC sampling clocks are local oscillations, with
Be present certain frequency error and phase error in the signal that ADC is received, adjusted if not realized to these errors, continuous in error
In the case of accumulation, information reception error below will result directly in.
In the prior art, it is adjustment ADC sampled clock signals and the frequency error and phase error of ADC reception signals, leads to
Frequently with method be that directly ADC sampled clock signals are adjusted, it is synchronous with reception signal to reach sampled clock signal
Effect, it realizes block diagram as shown in figure 1, ADC sample circuit output signals are passed sequentially through into phase error detection circuit, denoising
Acoustic-electric road and Voltage-Controlled oscillation circuit VCO, ADC sampling clocks are generated, wherein, Voltage-Controlled oscillation circuit VCO is analog circuit.
The implementation method of above-mentioned sampling clock adjustment circuit typically has two kinds：
One kind is to be integrated in and use chip piece phase error detection circuit, denoising circuit and Voltage-Controlled oscillation circuit VCO
Upper realization.Because phase error detection circuit, denoising circuit are digital circuits, and Voltage-Controlled oscillation circuit VCO is analog circuit.
In the design of this digital analog mixed, analog circuit is big by the noise jamming chance of digital circuit, so as to whole chip
Stability impact.
Another kind is that Voltage-Controlled oscillation circuit VCO individually is made into application specific integrated circuit (Application Specified
Integrated Circuit, ASIC), i.e., it is implemented separately with other digital circuits.The program although reduce VCO by
Digital circuit interference, but adds additional the design cost of whole sampling clock adjustment circuit and answering for circuit design
Polygamy.
The content of the invention
In order to solve the above technical problems, the invention provides a kind of adaptive sample value estimating circuit and method, to solve to subtract
The few frequency error of signal and the technical problem of phase error through the output of ADC sample circuits.
In order to solve the above technical problems, the invention provides a kind of adaptive sample value estimating circuit, the circuit includes phase
Position error sensing module, de-noise module, digital control oscillation module and sample value estimation module, wherein,
The phase error detection module, for the estimation sample value y (k) according to analog-to-digital conversion (ADC) circuit output signal
Phase error U (k) is calculated, and the phase error U (k) is sent to the de-noise module, k is whole more than or equal to 0
Number；
The de-noise module, for filtering out the high frequency noise components of the phase error U (k), obtain stable phase
Error W (k), and the stable phase error W (k) is sent to the digital control oscillation module；
The digital control oscillation module, for calculating integer estimation pointer m according to the smoothly phase error W (k)k
With decimal estimation pointer μk, and the integer is estimated into pointer mkWith decimal estimation pointer μkSend to the sample value estimation module；
The sample value estimation module, for estimating pointer m according to the integerkPositioning participates in the ADC of sample value estimation
The output signal of circuit, pointer μ is estimated according to decimalkThe coefficient of the output signal is determined, is obtained using the output signal
Estimate sample value y (k), and the estimation sample value y (k) is sent to the phase error detection module.
Further, the y (k) is the DQPSK signals of two-dimensional modulation
Further,
The mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1；
NCOout(0)=0.
Further,
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
Wherein, x (mk+2)、x(mk+1)、x(mk)、x(mk- 1) m of adc circuit is represented successivelyk+2、mk+1、mkAnd mk-1
Individual output signal.
In order to solve the above technical problems, present invention also offers a kind of adaptive sample value method of estimation, methods described includes：
Phase error U (k) is calculated according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal；
The high frequency noise components of the phase error U (k) are filtered out, obtain stable phase error W (k)；
Integer estimation pointer m is calculated according to the smoothly phase error W (k)kWith decimal estimation pointer μk；
Pointer m is estimated according to the integerkPositioning participates in the output signal of the adc circuit of sample value estimation, according to small
Number estimation pointer μkThe coefficient of the output signal is determined, obtains estimating sample value y (k) using the output signal.
Further, when the DQPSK signals that y (k) is two-dimensional modulation；
Further,
The mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1。
Further,
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
Wherein, x (mk+2)、x(mk+1)、x(mk)、x(mk- 1) m of adc circuit is represented successivelyk+2、mk+1、mkAnd mk-1
Individual output signal.
Above-mentioned technical proposal no longer reduces the frequency of the signal exported through ADC sample circuits by adjusting ADC sampling clocks
Error and phase error, but the signal to being exported through ADC sample circuits carries out adaptive sample value estimation and sampled to reduce through ADC
The frequency error and phase error of the signal of circuit output, whole adaptive sample value estimating circuit is digital circuit, that is, is ensured
The stability of adaptive sample value estimating circuit, also will not be that circuit design bring extra complexity.
Brief description of the drawings
Fig. 1 is the composition figure of prior art sampling clock adjustment circuit；
Fig. 2 is the adaptive sample value estimating circuit composition figure of the present embodiment；
Fig. 3 is the electrical block diagram of the phase error detection module of the present embodiment；
Fig. 4 is the electrical block diagram of the de-noise module of the present embodiment；
Fig. 5 is the electrical block diagram of the digital control oscillation module of the present embodiment；
Fig. 6 is the electrical block diagram of the sample value estimation module of the present embodiment；
Fig. 7 is the adaptive sample value method of estimation flow chart of the present embodiment.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case where not conflicting, in the embodiment and embodiment in the application
Feature can mutually be combined.
Fig. 2 is the adaptive sample value estimating circuit composition figure of the present embodiment.
The adaptive sample value estimating circuit includes phase error detection module, de-noise module, digital control oscillation module
And sample value estimation module, wherein,
Phase error detection module, for being calculated according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal
Phase error U (k), and the phase error U (k) is sent to the de-noise module, k is the integer more than or equal to 0；
Such as, input estimation sample value y (k) is the DQPSK signals of two-dimensional modulation,
Then
Wherein, I, Q are respectively y (k) real and imaginary parts；k、K-1 is 3 continuous sampled point sequence numbers, the phase
The electrical block diagram of error sensing module is as shown in Figure 3.
In the signal Complete Synchronization of no phase error, i.e. ADC sampling clocks and input ADC, if input ADC letter
Number the polarity of sample value change, then intermediate samples pointWithIt should be zero；If input ADC signal
The polarity of sample value does not change, then [I (k)-I (k-1)] and [Q (k)-Q (k-1)] should be zero.Therefore, regardless of sample value
Change, when not having phase error, the output U (k) of phase error detection circuit is zero.Conversely, when sampling clock and input
When the sample value of ADC signal has phase difference, then the output U (k) of phase error detection circuit is not zero.U (k) absolute values it is big
The small size for representing phase error, its symbol represent the direction of phase error.
De-noise module, for filtering out the high frequency noise components of the phase error U (k), obtain stable phase error W
(k), and by the stable phase error W (k) send to the digital control oscillation module；
Stable phase error W (k) acquisition can be realized by following formula：
Xp(k)=w1·U(k)；
Xi(k)=w2·U(k)+Xi(k-1)；
W (k)=Xp(k)+Xi(k)；
w1For proportional gain, w2For storage gain w2；
Xp(k) proportional path is represented, it is by phase error U (k) and proportional gain w1Multiplication obtains, adaptive for controlling
The phase error amplitude of accommodation of sample value estimating circuit each time.Such as：In the ideal case, if without phase error, i.e. U
(k)=0, then proportional path Xp(k)=0, the phase error amplitude of accommodation of adaptive sample value estimating circuit is zero.With ratio road
Footpath Xp(k) increase, the phase error amplitude of accommodation also increases.
Xi(k) path of integration is represented, it is cumulative errors.Due to currently available cumulative errors be prime cumulative errors with
The sum of error current, even if so error current and prime error have larger difference, react the ripple in current cumulative errors value
It is also relatively small on dynamic, that is, obtain a stable phase error.
The electrical block diagram of de-noise module is as shown in Figure 4.
Digital control oscillation module, for calculating integer estimation pointer m according to the smoothly phase error W (k)kWith it is small
Number estimation pointer μk, and the integer is estimated into pointer mkWith decimal estimation pointer μkSend to the sample value estimation module；
When y (k) is the DQPSK signals of two-dimensional modulation,
Integer estimation pointer mkWith decimal estimation pointer μkIt can be obtained according to following formula：
mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1。
NCOout(0)=0.
From NCOout(k) seen in calculation formula, NCOout(k) equivalent to one phase register, the wherein value of register
Constantly adjusted according to W (k-1).Work as NCOout(k) be 0 when, when the sampling of phase error, now ADC is not present in corresponding sampled point
The signal Complete Synchronization of clock and input ADC.
The electrical block diagram of digital control oscillation module is as shown in Figure 5.
Sample value estimation module, for estimating pointer m according to the integerkPositioning participates in the defeated of the adc circuit of sample value estimation
Go out signal, pointer μ is estimated according to decimalkThe coefficient of the output signal is determined, sample value estimation is carried out using the output signal,
Obtain estimating sample value y (k), and the sample value y (k) estimated is sent to the phase error detection module.
When y (k) is the DQPSK signals of two-dimensional modulation,
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
Wherein, x (mk+2)、x(mk+1)、x(mk)、x(mk- 1) m of adc circuit is represented successivelyk+2、mk+1、mkAnd mk-1
Individual output signal.
The electrical block diagram of sample value estimation module is as shown in Figure 6.
The output y (k) of sample value estimation module eliminates the sampled signal relative to the sampled signal exported through adc circuit
Frequency and phase error, y (k) be subsequent digital signal processing need sampled value.
Fig. 7 is the adaptive sample value method of estimation flow chart of the present embodiment.
S701 calculates phase error U (k) according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal；
When y (k) is the DQPSK signals of two-dimensional modulation,
Wherein, I, Q are respectively y (k) real and imaginary parts；k、K-1 is 3 continuous sampled point sequence numbers；
S702 filters out the high frequency noise components of the phase error U (k), obtains stable phase error W (k)；
S703 calculates integer estimation pointer m according to the smoothly phase error W (k)kWith decimal estimation pointer μk；
When y (k) is the DQPSK signals of two-dimensional modulation,
The mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1。
S704 estimates pointer m according to the integerkPositioning participates in the output signal of the adc circuit of sample value estimation, root
According to decimal estimation pointer μkThe coefficient of the output signal is determined, obtains estimating sample value y (k) using the output signal；
When y (k) is the DQPSK signals of two-dimensional modulation,
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
Wherein, x (mk+2)、x(mk+1)、x(mk)、x(mk- 1) m of adc circuit is represented successivelyk+2、mk+1、mkAnd mk-1
Individual output signal.
One of ordinary skill in the art will appreciate that all or part of step in the above method can be instructed by program
Related hardware is completed, and described program can be stored in computer-readable recording medium, such as read-only storage, disk or CD
Deng.Alternatively, all or part of step of above-described embodiment can also be realized using one or more integrated circuits, accordingly
Ground, each module/unit in above-described embodiment can be realized in the form of hardware, can also use the shape of software function module
Formula is realized.The present invention is not restricted to the combination of the hardware and software of any particular form.
It should be noted that the present invention can also have other various embodiments, without departing substantially from of the invention spiritual and its essence
In the case of, those skilled in the art can make various corresponding changes and deformation according to the present invention, but these are corresponding
Change and deform the protection domain that should all belong to appended claims of the invention.
Claims (8)
1. a kind of adaptive sample value estimating circuit, it is characterised in that the circuit includes phase error detection module, denoising acoustic mode
Block, digital control oscillation module and sample value estimation module, wherein,
The phase error detection module, for calculating phase according to the estimation sample value y (k) of analog-to-digital conversion adc circuit output signal
Position error U (k), and the phase error U (k) is sent to the de-noise module, k is the integer more than or equal to 0；
The de-noise module, for filtering out the high frequency noise components of the phase error U (k), obtain stable phase error W
(k), and by the stable phase error W (k) send to the digital control oscillation module；
The digital control oscillation module, for calculating integer estimation pointer m according to the smoothly phase error W (k)kWith it is small
Number estimation pointer μk, and the integer is estimated into pointer mkWith decimal estimation pointer μkSend to the sample value estimation module；
The sample value estimation module, for estimating pointer m according to the integerkPositioning participates in the adc circuit of sample value estimation
Output signal, pointer μ is estimated according to decimalkThe coefficient of the output signal is determined, obtains estimating sample using the output signal
Value y (k), and the estimation sample value y (k) is sent to the phase error detection module.
2. adaptive sample value estimating circuit as claimed in claim 1, it is characterised in that
The y (k) is the DQPSK signals of two-dimensional modulation.
3. adaptive sample value estimating circuit as claimed in claim 2, it is characterised in that：
The mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1；
NCOout(0)=0；
NCOoutIt is to be used to the decimal estimation pointer μ be calculatedkA median.
4. adaptive sample value estimating circuit as claimed in claim 2 or claim 3, it is characterised in that：
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
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Go out signal；C2、C1、C0、C-1The proportionality coefficient of the original sample value of the estimated value for calculating optimum sampling point is represented successively.
5. a kind of adaptive sample value method of estimation, it is characterised in that methods described includes：
Phase error U (k) is calculated according to the estimation sample value y (k) of analog-to-digital conversion adc circuit output signal；
The high frequency noise components of the phase error U (k) are filtered out, obtain stable phase error W (k)；
Integer estimation pointer m is calculated according to the smoothly phase error W (k)kWith decimal estimation pointer μk；
Pointer m is estimated according to the integerkPositioning participates in the output signal of the adc circuit of sample value estimation, is estimated according to decimal
Pointer μkThe coefficient of the output signal is determined, obtains estimating sample value y (k) using the output signal；
K is the integer more than or equal to 0.
6. method as claimed in claim 5, it is characterised in that
The y (k) is the DQPSK signals of two-dimensional modulation.
7. method as claimed in claim 6, it is characterised in that
The mk=floor (W (k) × k), floor () represent to round；
μk=NCOout(k)/W(k)；
NCOout(k)=[NCOout(k-1)-W(k-1)]mod1；
NCOoutIt is to be used to the decimal estimation pointer μ be calculatedkA median.
8. method as claimed in claims 6 or 7, it is characterised in that
Y (k)=x (mk+2)×C2(μk)+x(mk+1)×C1(μk)+x(mk)×C0(μk)+x(mk-1)×C-1(μk)；
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Wherein, x (mk+2)、x(mk+1)、x(mk)、x(mk- 1) m of adc circuit is represented successivelyk+2、mk+1、mkAnd mk- 1 defeated
Go out signal；C2、C1、C0、C-1The proportionality coefficient of the original sample value of the estimated value for calculating optimum sampling point is represented successively.
Priority Applications (1)
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