CN103325346A - Driving control method and correlative source electrode driver - Google Patents
Driving control method and correlative source electrode driver Download PDFInfo
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- CN103325346A CN103325346A CN2012100793610A CN201210079361A CN103325346A CN 103325346 A CN103325346 A CN 103325346A CN 2012100793610 A CN2012100793610 A CN 2012100793610A CN 201210079361 A CN201210079361 A CN 201210079361A CN 103325346 A CN103325346 A CN 103325346A
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Abstract
The invention discloses a driving control method for a source electrode driver. The driving control method includes the steps of outputting a positive display voltage signal to a first output buffer of the source electrode driver according to a first control signal, and outputting a negative display voltage signal to a second output buffer of the source electrode driver, and outputting black frame insertion voltage signals to the first output buffer and the second output buffer respectively according to a second control signal.
Description
Technical field
The present invention relates to a kind of driving control method and source electrode driver thereof, relate in particular to a kind of charge share device that can need not use and to reduce driving control method and the source electrode driver thereof of associated component cross-pressure.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) have low radiation, volume is little and the advantage such as low power consuming, replace gradually traditional cathode-ray tube (CRT) (Cathode ray Tube, CRT) display, and then be widely used on the information products such as notebook, digital palmtop computer (personal digital assistant, PDA), flat panel TV or mobile phone.The principle of work of liquid crystal display is to utilize liquid crystal cells (Liquid Crystal Cell) under different ordered states, light had different polarizations or refraction effect, therefore can change via different polar voltages the ordered state of liquid crystal cells, control the amount of penetrating of light, thereby produce the output light of varying strength and the red, green, blue of different gray shade scales.
Because the long-time same polar voltages (such as positive voltage or negative voltage) of using drives liquid crystal cells, will cause liquid crystal material to produce polarization and cause nonvolatil destruction, and then reduce liquid crystal cells to the polarization of light or refraction effect and so that the deterioration of picture disply.Therefore, when the source electrode driver of liquid crystal display carries out the pixel display driver, usually the polarity of voltage that is applied to the liquid crystal material layer two ends must carry out reversal of poles (Polarity Inversion) at set intervals, that is to say, alternately the mode with generating positive and negative voltage drives liquid crystal cells.
For instance, please refer to Fig. 1, Fig. 1 is the schematic diagram that is applied to the source electrode driver 10 of source electrode driver in the known technology.For convenience of description, Fig. 1 only shows digital analog converter PDAC, NDAC, switch 100～110, output buffer OP1, OP2 and a charge share switch S CS of source electrode driver 10, and all the other then slightly do not show such as time schedule controller, code translator (decoder) etc.Digital analog converter PDAC is used for receiving a positive pixel data-signal SD1, and output one is just showing that voltage signal VDP is to the input end IN1 of output buffer OP1.Digital analog converter NDAC is used for receiving a negative pixel data-signal SD2, to export a negative demonstration voltage signal VDN to the input end IN2 of output buffer OP2.Switch 100 is used for according to a control signal BFIB, the link between control input end IN1 and a node N1.Switch 102 is used for according to control signal BFIB, the link between control input end IN2 and a node N2.In addition, because digital analog converter PDAC and digital analog converter NDAC are with middle pressure assembly realization, so switch 100 is to realize with middle pressure assembly with switch 102.Switch 104, switch 106 are controlled the link of node N1 and input end IN1 respectively according to control signal CTL1, control signal CTL2.Switch 108, switch 110 are controlled respectively the link of node N2 and input end IN2 according to control signal CTL1, control signal CTL2.Because output buffer OP1 and output buffer OP2 realize with high potential assembly, so switch 104～110th, realize with high potential assembly (High-voltage device).Output buffer OP1 is used for receiving the node voltage VIN1 of input end IN1, to export output voltage signal VOUT1 to a pixel P1.Output buffer OP2 is used for receiving the node voltage VIN2 of input end IN2, and to export output voltage signal VOUT2 to a pixel P2, wherein pixel P2 is the neighbor of pixel P1.Charge share switch S CS is used for according to a control signal CTL3, the link between control input end IN1 and the input end IN2.
Specifically, when a display cycle begins, switch 100,102,104,108 meeting conductings, and switch 106,110 can disconnect, just showing that voltage signal VDP can export output buffer OP1 to, and the negative voltage signal VDN that shows can export output buffer OP2 to.Subsequently, if drive unit 10 carries out reversal of poles immediately, to just show immediately namely that voltage signal VDP switches to export output buffer OP2 to and will bear shows that voltage signal VDN switches and exports output buffer OP1 to, and switch 104,108 needs to disconnect, and switch 106,110 needs conducting.Thus, in the moment of switch 106, switch 110 conductings, the node voltage VN1 of node N1 negative shows voltage signal VDN, and a cross-pressure Vswitch1 of switch 100 becomes and just shows that voltage signal VDP deducts the negative value that shows voltage signal VDN.Under this situation, cross-pressure Vswitch1 may be excessive and cause the switch 100 of realizing with middle pressure assembly to damage.In like manner, cross-pressure Vswitch2 also may cause switch 102 to damage.Therefore, before carrying out reversal of poles, drive unit 10 needs first electric conduction lotus to share switch S CS, makes input end IN1 and input end IN2 carry out charge share.Thus, in the time of can avoiding control signal CTL2 to indicate this conducting state, switch 100 and switch 102 cause respectively damage because cross-pressure Vswitch1, cross-pressure Vswitch2 are excessive.
Further, please refer to Fig. 2, the sequential chart of coherent signal when Fig. 2 is source electrode driver 10 running of Fig. 1.As shown in Figure 2, a display cycle indicator signal LD indicates this display cycle to begin at a time point T1, finishes at a time point T5.Between time point T1 to time point T2, control signal CTL1, BFIB are designated as conducting state, and control signal CTL2, CTL3 are designated as off-state.At this moment, output buffer OP1 receives and is just showing voltage signal VDP, and output buffer OP2 receives the negative voltage signal VDN that shows.Subsequently, if when time point T2, immediately control signal CTL2 switching is designated as conducting state, may causes switch 100, switch 102 damages.Therefore, at time point T2, control signal CTL1 switching is designated as off-state, and control signal CTL3 switching is designated as conducting state, with 102 conductings of charge share switch, makes input end IN1 and input end IN2 carry out charge share.Then, again in time point T3, control signal CTL3 switching is designated as off-state, control signal CTL2 switching is designated as conducting state, makes output buffer OP1 receive the negative voltage signal VDN that shows, output buffer OP2 reception is just showing voltage signal VDP.Thus, 10 beginnings of source electrode driver are finished reversal of poles.
Yet, cause respectively damage because cross-pressure Vswitch1, cross-pressure Vswitch2 are excessive for fear of switch 100, switch 102, source electrode driver 10 needs the extra charge share switch S CS that increases, thus, not only can increase the complexity of circuit design, and can significantly promote the manufacturing cost of integrated circuit.In view of this, known technology has improved necessity in fact.
Summary of the invention
Therefore, the present invention mainly provides the cross-pressure that can reduce source electrode driver relevant internal components when carrying out reversal of poles, with the driving control method of avoiding relevant internal components to damage.
The present invention discloses a kind of driving control method for the one source pole driver, comprise: according to one first control signal, output one is just showing voltage signal to one first output buffer of this source electrode driver, and exports a negative demonstration voltage signal to one second output buffer of this source electrode driver; And according to one second control signal, export respectively a black plug voltage signal to this first output buffer and this second output buffer.
The present invention also discloses a kind of source electrode driver, be used for a display device, this source electrode driver comprises one first output buffer, receives one at a first input end and is just showing voltage signal or a negative demonstration voltage signal, and export according to this one first source drive voltage signal to the first pixel; One second output buffer receives this at one second input end and is just showing that voltage signal maybe should negatively show voltage signal, to export one second source drive voltage signal to the second pixel; One positive digital analog converter is used for according to a positive pixel data-signal, is just showing voltage signal in positive output end output one; One negative digital analog converter is used for according to a negative pixel data-signal, exports a negative demonstration voltage signal at a negative output terminal; One correction data switch is coupled to this positive output end and a first node; One negative data switch is coupled to this negative output terminal and a Section Point; One positive black plug switch is coupled to this first node and a black plug power supply, and the magnitude of voltage of this black plug power supply is a black plug voltage; One negative black plug switch is coupled to this Section Point and this black plug power supply; One first tumbler switch is coupled to this first node and this first output buffer; One second tumbler switch is coupled to this first node and this second output buffer; One the 3rd tumbler switch is coupled to this Section Point and this first output buffer; And one the 4th tumbler switch, be coupled to this Section Point and this second output buffer; Wherein, according to one first control signal this correction data switch, this first tumbler switch, this negative data switch and this second tumbler switch are switched on, this positive digital analog converter is exported this and is just being shown voltage signal to this first output buffer and should negative digital analog converter output should negatively show that voltage signal was to this second output buffer, and make this positive black plug switch and should be switched on by negative black plug switch according to one second control signal, to export respectively a black plug voltage signal to this first output buffer and this second output buffer.
Cooperate detailed description and claims of following diagram, embodiment at this, with on address other purpose of the present invention and advantage and be described in detail in after.
Description of drawings
Fig. 1 is the schematic diagram of known one source pole driver.
Fig. 2 is the sequential chart of source electrode driver when running coherent signal of Fig. 1.
Fig. 3 is the schematic diagram of embodiment of the invention one source pole driver.
The sequential chart of coherent signal when Fig. 4 is source electrode driver shown in Figure 3 running.
Fig. 5 is the schematic diagram of another implementation of source electrode driver shown in Figure 3.
The sequential chart of coherent signal when Fig. 6 is source electrode driver shown in Figure 5 running.
Another sequential chart of coherent signal when Fig. 7 is source electrode driver shown in Figure 3 running.
An again sequential chart of coherent signal when Fig. 8 is source electrode driver shown in Figure 3 running.
Fig. 9 is the process flow diagram that the embodiment of the invention one drives control method.
Wherein, description of reference numerals is as follows:
10,30,50 source electrode drivers
100～110,300～310,500～510 switches
312,314,512,514 black plug switches
90 drive control method
900～910 steps
BFI, CTL1, CTL2, CTL3 control signal
BFIB、CTL1B、CTL2B
The INP positive input terminal
The INN negative input end
IN1, IN2 input end
N1, N2 node
NDAC bears digital analog converter
OP1, OP2 output buffer
PDAC positive digital analog converter
SCS charge share switch
T1, T2, T3, T4, T5, T6 time point
VB black plug voltage signal
The negative voltage signal that shows of VDN
VDP is just showing voltage signal
VIN1, VIN2, VN1, VN2 node voltage
VOUT1, VOUT2 output voltage signal
Vswitch1, Vswitch2 cross-pressure
Embodiment
Please refer to Fig. 3, Fig. 3 is the schematic diagram of embodiment of the invention one source pole driver 30.Source electrode driver 30 is applied to a display device, for example is used for a liquid crystal indicator.Source electrode driver 30 is used for receiving the pixel data signal that is transmitted by time schedule controller, and produce according to this source drive voltage signal VOUT1, VOUT2 to export pixel P1, P2 (not being illustrated in Fig. 3) to, preferably, pixel P2 is the neighbor of pixel P1.As shown in Figure 3, source electrode driver 30 comprises digital analog converter PDAC, NDAC, switch 300～310, black plug switch 312,314, output buffer OP1, OP2.Digital analog converter PDAC is used for a positive pixel data-signal SD1 is converted to the just demonstration voltage signal VDP of positive polarity.Digital analog converter NDAC is used for a negative pixel data-signal SD2 is converted to the negative demonstration voltage signal VDN of negative polarity.In source electrode driver 30, after receiving the pixel data signal that is transmitted by time schedule controller, source electrode driver 30 can be divided into positive pixel data-signal SD1 and negative pixel data-signal SD2 with pixel data signal according to a polarity control signal, and provide respectively to digital analog converter PDAC, NDAC, required signal polarity requirement when realizing the reversal of poles program, as for, pixel data signal is divided into the operation of positive pixel data-signal and negative pixel data-signal, knowing this skill personage should understand, and does not repeat them here.
Usually source electrode driver 30 is when carrying out reversal of poles, when switch 300,304 conducting, digital analog converter PDAC can export the just demonstration voltage signal VDP of positive polarity to output buffer OP1, and when switch 302,308 conducting, digital analog converter NDAC can export the negative demonstration voltage signal VDN of negative polarity to output buffer OP2.When switch 300,306 conducting, digital analog converter PDAC can export the just demonstration voltage signal VDP of positive polarity to output buffer OP2, and when switch 302,310 conducting, digital analog converter NDAC can export the negative demonstration voltage signal VDN of negative polarity to output buffer OP1.Black plug switch 312,314 is used for respectively according to control signal BFI, export a black plug voltage signal VB to output buffer OP1 and output buffer OP2, in the present invention, black plug switch 312,314 is except showing black data in two picture frame display cycle chien shih pixel P1, P2, thereby reach outside the purpose of black plug, more can be before carrying out reversal of poles, make magnitude of voltage on node N1, N2, input end IN1, the IN2 be adjusted into the magnitude of voltage size of black plug voltage signal VB.Wherein, the large I of magnitude of voltage of black plug voltage signal VB is between the minimum voltage value of the maximum voltage value that just shows voltage signal VDP and negative demonstration voltage signal VDN, for instance, the magnitude of voltage of black plug voltage signal VB size is a ceiling voltage of source electrode driver 30 and the mean value of a minimum voltage.
In brief, source electrode driver 30 is by adjusting the sequential of control signal BFI, BFIB, CTL1, CTL2, can be before source electrode driver 30 carries out reversal of poles, make black plug switch 312,314 conductings, and allow magnitude of voltage on node N1, N2, input end IN1, the IN2 be adjusted into the magnitude of voltage of black plug voltage signal VB.Because black plug voltage signal VB and the voltage difference that is just showing voltage signal VDP and black plug voltage signal VB and the negative voltage difference of voltage signal VDN that shows are all less than just showing voltage signal VDP and the negative voltage difference that shows voltage signal VDN, therefore when source electrode driver 30 carries out reversal of poles, voltage swing on the above-mentioned node will reduce effectively, and switch 300 and switch 302 are will be not can cross-pressure not excessive and cause damaging.
Specifically, when a picture frame display cycle begins, according to control signal BFI, BFIB, CTL1, CTL2, switch 300,302,304,308 meeting conductings, switch 306,310 and black plug switch 312,314 can disconnect, so that the node voltage VIN1 of the node voltage VN1 on the node N1 and input end IN1 equals just to show the magnitude of voltage size of voltage signal VDP, and the node voltage VIN2 of the node voltage VN2 of node N2 and input end IN2 equals the negative magnitude of voltage size that shows voltage signal VDN.That is to say, because switch 300,302,308,312 is in conducting state, therefore, output buffer OP1 can receive the just demonstration voltage signal VDP that digital analog converter PDAC transmits, and output buffer OP2 can receive the negative demonstration voltage signal VDN that digital analog converter NDAC transmits.Subsequently, switch 300～310 can disconnect, and black plug switch 312,314 meeting conductings are so that the magnitude of voltage of node voltage VN1 and node voltage VN2 can convert the magnitude of voltage size of black plug voltage signal VB to.Then, with switch 306,310 conductings.At this moment, switch 300～304,308 continues to be in off-state, and switch 306,310, black plug switch 312,314 are in conducting state, thus, with so that node voltage VIN1, voltage VIN2 also can convert the magnitude of voltage size of black plug voltage signal VB to, that is to say, output buffer OP1, OP2 receive respectively black plug voltage signal VB.All equal the magnitude of voltage of black plug voltage signal VB in node voltage VN1, VN2, VIN1, VIN2 after, source electrode driver 30 can carry out reversal of poles.That is to say, switch 304,308, black plug switch 312,314 are understood disconnection, and switch 300,302,306,310 is understood conductings, so that node voltage VN1, VIN2 equal just to show voltage signal VDP, voltage VN2, VIN2 equal the negative voltage signal VDN that shows, to realize reversal of poles.That is to say, output buffer OP1 can receive the negative demonstration voltage signal VDN that digital analog converter NDAC transmits, and output buffer OP1 can receive the negative demonstration voltage signal VDP that digital analog converter PDAC transmits.At last, before this display cycle finishes, switch 300～304,308 can disconnect, switch 306,310 and black plug switch 312,314 can conductings, make the magnitude of voltage of node voltage VN1, VN2, VIN1, VIN2 can again move the magnitude of voltage size of black plug voltage signal VB to, so that output buffer OP1 and output buffer OP2 output black plug voltage signal VB, thereby pixel P1 and pixel P2 show black data, to carry out routine black plug program.
Further, please refer to Fig. 4, the sequential chart of coherent signal when Fig. 4 is source electrode driver 30 running of Fig. 3.As shown in Figure 4, suppose that display cycle indicator signal LD is used to refer to the cycle that picture frame shows, for example, the display cycle, indicator signal LD was noble potential in time point T1～T6, was expressed as a picture frame display cycle.In time point T1 between the time point T2, control signal BFIB, CTL1 are designated as conducting state, and control signal BFI, CTL2 are designated as off-state.At this moment, the magnitude of voltage size of node voltage VN1, VIN1 equals just to show the magnitude of voltage of voltage signal VDP, and voltage VN2 and voltage VIN2 equal the negative magnitude of voltage that shows voltage signal VDN.Subsequently, when time point T2, control signal CTL1, BFIB switching is designated as off-state, and the magnitude of voltage size of node voltage VN1, VN2 all becomes the magnitude of voltage of black plug voltage signal VB.In time point T3, control signal CTL2 switching is designated as conducting state, and at this moment, the magnitude of voltage of node voltage VIN1, VIN2 will become the magnitude of voltage size of black plug voltage signal VB.Then, at time point T4, control signal BFI switches and to be designated as off-state, and control signal BFIB then switches and is designated as conducting state, the large young pathbreaker of the magnitude of voltage of node voltage VIN1 becomes and negative shows voltage signal VDN, and the magnitude of voltage size of node voltage VIN2 becomes and just shows voltage signal VDP.At last, at time point T5, control signal BFIB switching is designated as off-state, and control signal BFI then is designated as conducting state, and the magnitude of voltage of node voltage VN1, VN2, VIN1 and VIN2 all becomes the magnitude of voltage size of black plug voltage signal VB.
Should be noted, for the magnitude of voltage size with the magnitude of voltage of node voltage VIN1, VIN2 electricity elementary errors black voltage signal VB, can first control signal CTL1, BFIB be switched the indication off-state as shown in Figure 4, again control signal CTL2 is switched to conducting state.In addition, also can simultaneously CTL1, CFIB switching be designated as off-state and control signal CTL2 is switched to conducting state, also the magnitude of voltage of node VIN1, VIN2 can be become the magnitude of voltage size that signal VB is pressed in the black plug shop.
In general, when each conversion, just can carry out the black plug program picture frame display cycle, that is to say, entering next picture frame display cycle before (for example in the time point T5 of Fig. 4 time), can carry out black plug one time, so that the fluency of increase dynamic image.Source electrode driver 30 of the present invention has utilized the framework of black insertion technology, and by control signal BFI, BFIB, CTL1, the sequential adjustment of CTL2, and can be in picture frame carries out the reversal of poles program in the display cycle before, export black plug voltage signal VB to node N1, node N2, input end IN1, input end IN2, so that its corresponding node voltage is pulled to the magnitude of voltage size of black plug voltage signal VB, thus, when source electrode driver 30 carries out reversal of poles, voltage swing on the above-mentioned node will reduce effectively, and then lower the magnitude of voltage size of cross-pressure Vswitch1 and cross-pressure Vswitch2 when carrying out reversal of poles, thereby avoid switch 300 and switch 302 damages.
Please refer to Fig. 5, Fig. 5 is the schematic diagram of embodiment of the invention one source pole driver 50.Source electrode driver 50 is an implementation of the source electrode driver 30 of Fig. 3.Source electrode driver 30 compared to Fig. 3, in Fig. 5, switch 300～310, black plug switch 312 and black plug switch 314 are to realize with transistor 500～514, as shown in Figure 5, transistor 500,504,506, the 512nd, P type metal-oxide half field effect transistor, transistor 502,508,510, the 514th, N-type metal-oxide half field effect transistor.In addition, in order to reach the conducting order identical with switch 300～314 tools of Fig. 3, source electrode driver 50 is adjusted the configuration of part control signal, wherein, utilize control signal BFI whether to control transistor 500,514 conducting, utilize control signal BFIB whether to control transistor 502,512 conducting.Utilize respectively in addition conducting that control signal CTL1B, CTL2B, CTL1, CTL2 control transistor 504～510 whether.Thus, the operation of source electrode driver 50 can with reference to above-mentioned source electrode driver 30, be not repeated herein.
The detailed time sequential routine as for source electrode driver 50 please refer to Fig. 6, the sequential chart of coherent signal when Fig. 6 is source electrode driver 50 running of Fig. 5.As shown in Figure 6, display cycle indicator signal LD is high logic current potential in time point T1 to time point T6, to indicate this picture frame display cycle.In time point T1 between the time point T2, control signal BFIB, CTL1, CTL2B are high logic current potentials, and control signal BFI, CTL1B, CTL2 are low logic current potentials.At this moment, transistor 500,502,504,508 conductings, the voltage of node voltage VN1, VIN1 equals just to show the magnitude of voltage of voltage signal VDP, and the voltage of node voltage VN2, VIN2 is the negative magnitude of voltage that shows voltage signal VDN.Subsequently, at time point T2, control signal BFIB, control signal CTL1 are pulled down to low logic current potential, and control signal BFI, the control signal CTL1B paramount logic current potential that rises disconnects transistor 512,514 conductings, transistor 500,502,504,508.Node voltage VN1, VN2 can equal the magnitude of voltage of black plug voltage signal VB at this moment.Then, at time point T3, the control signal CTL2 paramount logic current potential that rises, and control signal CTL2B drops to low logic current potential.Under this situation, transistor 506,510 meeting conductings, the magnitude of voltage of node voltage VIN1 and voltage VIN2 becomes black plug voltage signal VB.Next, at time point T4, control signal BFI is pulled down to low logic current potential, the control signal BFIB paramount logic current potential that rises, so that transistor 500,502 conductings, transistor 512,514 disconnect, node voltage VIN1 becomes the negative voltage signal VDN of demonstration and node voltage VIN2 and becomes and just show voltage signal VDP.At last, at time point T5, the control signal BFI paramount logic current potential that rises, control signal BFI is pulled down to low logic current potential, so that transistor 500,502 disconnections, transistor 512,514 conductings, node voltage VIN1, VIN2 get back to black plug voltage signal VB once again, the black plug purpose when changing with the realization picture frame display cycle.
Should be noted, main spirits of the present invention is to adjust the sequential of the control signal of source electrode driver, the cross-pressure of source electrode driver internal switch assembly when carrying out reversal of poles to utilize the circuit unit that is used for realizing black insertion technology, to be reduced to source electrode driver, thus avoid switch module to damage.According to different application, those skilled in the art can make suitable variation or adjustment according to this.For example, please refer to Fig. 7, another sequential chart of coherent signal when Fig. 7 is source electrode driver 50 running of Fig. 5.As shown in Figure 7, control signal BFI and CTL1 and control signal BFIB and CTL1B are non-overlapping frequency signal (Non overlapping clock), to avoid that non-essential charge share occurs in the source electrode driver 50, cause source electrode driver 50 to work.
In addition, please refer to Fig. 8, an again sequential chart of coherent signal when Fig. 8 is source electrode driver 50 running of Fig. 5.As shown in Figure 8, after time point T2, control signal BFI continues to keep high logic current potential, and control signal BFIB then continues to keep low logic current potential.Under this situation, node voltage VN1, VN2 will continue to equal the size of black plug voltage signal VB, until time point T6.Therefore, after time point T3, node voltage VIN1, VIN2 also continue to equal black plug voltage signal VB.In other words, as long as source electrode driver 50 is before cycle indicator signal LD is pulled down to low logic current potential, before namely this finishes picture frame display cycle, have node voltage VIN1, VIN2 are switched to black plug voltage signal VB can to make output buffer OP1, OP2 export respectively black plug voltage signal VB to pixel P1 and pixel P2.Certainly, in the case, source electrode driver 50 also can not carry out reversal of poles.
About the running of the source electrode driver 30 of Fig. 3, can further be summarized as one and drive control method 90.Please refer to Fig. 9, Fig. 9 is the schematic diagram that one of the embodiment of the invention drives control method 90.As shown in Figure 9, the step of driving control method 90 comprises:
Step 900: beginning.
Step 902: output is just showing voltage signal VDP to output buffer OP1, and the negative voltage VDN that shows of output is to output buffer OP2.
Step 904: output black plug voltage signal VB is to output buffer OP1 and output buffer OP2.
Step 906: output is just showing voltage signal VDP to output buffer OP2, and the negative voltage signal VDN that shows of output is to output buffer OP1.
Step 908: output black plug voltage signal VB is to output buffer OP1 and output buffer OP2.
Step 910: finish.
The detailed operation that drives control method 90 can with reference to above-mentioned, not repeat them here.
In sum, the present invention realizes being similar to the function of charge share switch, thereby avoids switch module to damage by sequential and original circuit unit that is used for realizing black insertion technology of control source electrode driver associated control signal.Therefore, compared to known technology, the present invention is except needing additionally to arrange the charge share switch, more can use original circuit unit that namely is used for realizing black insertion technology, and effectively reduces the complexity of circuit design and significantly reduce the manufacturing cost of integrated circuit.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. driving control method that is used for the one source pole driver comprises:
According to one first control signal, output one is just showing voltage signal to one first output buffer of this source electrode driver, and exports a negative demonstration voltage signal to one second output buffer of this source electrode driver; And
According to one second control signal, export respectively a black plug voltage signal to this first output buffer and this second output buffer.
2. driving control method as claimed in claim 1 is characterized in that, in exporting respectively this black plug voltage signal to this first output buffer and this second output buffer, this driving control method also comprises:
According to one the 3rd control signal, export this and just showing voltage signal to this second output buffer, and output should negatively show that voltage signal was to this first output buffer; And
According to one the 4th control signal, export respectively this black plug voltage signal to this first output buffer and this second output buffer.
3. driving control method as claimed in claim 1, it is characterized in that, this first output buffer is exported one first source drive voltage signal to the first pixel, this second output buffer is exported one second source drive voltage signal to the second pixel, and this first pixel and this second pixel are adjacent pixels.
4. driving control method as claimed in claim 1 is characterized in that, the magnitude of voltage size of this black plug voltage signal is just showing between the maximum voltage value and the negative minimum voltage value that shows voltage signal of voltage signal between this.
5. driving control method as claimed in claim 1 is characterized in that, the magnitude of voltage size of this black plug voltage signal is a ceiling voltage of this source electrode driver and the mean value of a minimum voltage.
6. a source electrode driver is used for a display device, and this source electrode driver comprises
One first output buffer receives one at a first input end and is just showing voltage signal or a negative demonstration voltage signal, and exports according to this one first source drive voltage signal to the first pixel;
One second output buffer receives this at one second input end and is just showing that voltage signal maybe should negatively show voltage signal, to export one second source drive voltage signal to the second pixel;
One positive digital analog converter is used for according to a positive pixel data-signal, is just showing voltage signal in positive output end output one;
One negative digital analog converter is used for according to a negative pixel data-signal, exports a negative demonstration voltage signal at a negative output terminal;
One correction data switch is coupled to this positive output end and a first node;
One negative data switch is coupled to this negative output terminal and a Section Point;
One positive black plug switch is coupled to this first node and a black plug power supply, and the magnitude of voltage of this black plug power supply is a black plug voltage;
One negative black plug switch is coupled to this Section Point and this black plug power supply;
One first tumbler switch is coupled to this first node and this first output buffer;
One second tumbler switch is coupled to this first node and this second output buffer;
One the 3rd tumbler switch is coupled to this Section Point and this first output buffer; And
One the 4th tumbler switch is coupled to this Section Point and this second output buffer;
Wherein, according to one first control signal this correction data switch, this first tumbler switch, this negative data switch and this second tumbler switch are switched on, this positive digital analog converter is exported this and is just being shown voltage signal to this first output buffer and should negative digital analog converter output should negatively show that voltage signal was to this second output buffer, and make this positive black plug switch and should be switched on by negative black plug switch according to one second control signal, to export respectively a black plug voltage signal to this first output buffer and this second output buffer.
7. source electrode driver as claimed in claim 6, it is characterized in that, in exporting respectively this black plug voltage signal to this first output buffer and this second output buffer, make this correction data switch according to one the 3rd control signal, the 3rd tumbler switch, this negative data switch and the 4th tumbler switch are switched on, this positive digital analog converter is exported this and is just being shown that voltage signal is to this second output buffer, and should negative digital analog converter output should negatively show that voltage signal was to this second output buffer, and make this positive black plug switch and should be switched on by negative black plug switch according to one the 4th control signal, to export respectively this black plug voltage signal to this first output buffer and this second output buffer.
8. source electrode driver as claimed in claim 6 is characterized in that, the magnitude of voltage size of this black plug voltage signal is just showing between the maximum voltage value and the negative minimum voltage value that shows voltage signal of voltage signal between this.
9. source electrode driver as claimed in claim 6 is characterized in that, the magnitude of voltage size of this black plug voltage signal is a ceiling voltage of this source electrode driver and the mean value of a minimum voltage.
10. source electrode driver as claimed in claim 6, it is characterized in that, this correction data switch, this negative data switch, this positive black plug switch, this negative black plug switch, this first tumbler switch, this second tumbler switch, the 3rd tumbler switch, the 4th tumbler switch are to realize with transistor.
11. source electrode driver as claimed in claim 6, it is characterized in that, this correction data switch, this positive black plug switch, this first tumbler switch, this second tumbler switch are P type metal-oxide half field effect transistors, and this negative data switch, this negative black plug switch, the 3rd tumbler switch, the 4th tumbler switch are the N-type metal-oxide half field effect transistors.
12. source electrode driver as claimed in claim 6 is characterized in that, this first pixel and this second pixel are adjacent pixels.
13. source electrode driver as claimed in claim 6 is characterized in that, this display device is a liquid crystal display.
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| CN105677276A (en) * | 2016-01-04 | 2016-06-15 | 京东方科技集团股份有限公司 | Black frame insertion processing method and device and display device |
| CN110034678A (en) * | 2018-01-12 | 2019-07-19 | 博发电子股份有限公司 | Single inductance double-polarity control type of voltage step-up/down converter and its control method |
| CN113903316A (en) * | 2021-10-19 | 2022-01-07 | 上海新相微电子股份有限公司 | TFT LCD driver chip is to display screen source electrode parasitic capacitance charge recovery circuit |
| CN114187869A (en) * | 2021-12-03 | 2022-03-15 | 北京奕斯伟计算技术有限公司 | Display panel, control method, control device, and storage medium |
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| CN113903316A (en) * | 2021-10-19 | 2022-01-07 | 上海新相微电子股份有限公司 | TFT LCD driver chip is to display screen source electrode parasitic capacitance charge recovery circuit |
| CN114187869A (en) * | 2021-12-03 | 2022-03-15 | 北京奕斯伟计算技术有限公司 | Display panel, control method, control device, and storage medium |
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Application publication date: 20130925 |