CN103324229A - Constant current source - Google Patents
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- CN103324229A CN103324229A CN2012100765131A CN201210076513A CN103324229A CN 103324229 A CN103324229 A CN 103324229A CN 2012100765131 A CN2012100765131 A CN 2012100765131A CN 201210076513 A CN201210076513 A CN 201210076513A CN 103324229 A CN103324229 A CN 103324229A
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Abstract
The invention discloses a constant current source which comprises a first current mirror, wherein the first current mirror comprises a current input end, a first current output end and a second current output end; the constant current source further comprises a current maintaining unit; in the current maintaining unit, conductive paths of a first transistor and a third transistor are sequentially connected between the first current output end and a first reference potential terminal in series; conductive paths of a second transistor and a fourth transistor are sequentially connected between the second current output end and the first reference potential terminal in series; grid electrodes of the first transistor and the second transistor are electrically connected with the first current output end; grid electrodes of the third transistor and the fourth transistor are electrically connected with the second current output end; and a drain electrode of the second transistor is further electrically connected with an external load. By means of the constant current source, current output by the constant current source is not influenced by the resistance value of the load.
Description
Technical field
The present invention relates to a kind of constant current source, particularly relate to a kind of constant current source with current mirror.
Background technology
Constant-current source circuit is exactly to want to provide a stable electric current to guarantee the basis of other circuit steady operation.Namely require constant-current source circuit output steady current, therefore the device as output stage should be the volt-ampere characteristic with saturated output current.This can adopt the BJT (bipolar junction transistor) or the MOSFET (mos field effect transistor) that work in the output current state of saturation to realize.
Figure 1 shows that a kind of basic constant-current source circuit, comprising a current mirror, wherein said current mirror comprises NMOS pipe M1 (N-type mos field effect transistor) and NMOS pipe M2, also comprises PMOS pipe P1 (P-type mos field effect transistor) and PMOS pipe P2 in the described constant-current source circuit.The drain electrode of described NMOS pipe M1 receives reference current Ir, described NMOS pipe M2 output current Ib, because described NMOS pipe M1 and NMOS pipe M2 consist of current mirror, so and the identical output current Ib of length breadth ratio of described NMOS pipe M1 and NMOS pipe M2 and reference current Ir big or small identical.
And described PMOS pipe P1 receives described output current Ib, described PMOS pipe P2 output current Io is to load, and the ratio of the length breadth ratio of the length breadth ratio of described PMOS pipe P2 and PMOS pipe P1 is n, described n is more than or equal to 1, so same mirror principle according to current mirror, described Io is identical with described ratio n with the ratio of Ib, i.e. the value of the most n of Io Ib doubly is so export the value that the value of the electric current I o of load should be n Ib doubly to.
But the I-V formula according to the transistor state of saturation: I=K (Vgs-Vt)
2(1+ λ Vds), can find that this structure has following two point defects:
1, cause the variation of the Vout voltage of described basic constant-current source circuit output owing to the variation of load, so that the difference of the Vout voltage of the VCC voltage of the source of PMOS pipe P2 and drain terminal, namely Vds has produced larger variation.For example, when VCC=2.7V and Ir=1mA, and n=8, this moment, the ideal value of Io should be 8mA according to the mirror principle.
But when the resistance R=100 of load ohm, Vout=Io * R=8 * 100=0.8V, thereby Vds=VCC-Vout=2.7V-0.8V=1.9V, and when the resistance R=200 of load ohm, so Vout=8 * 200=1.6V is Vds=VCC-Vout=2.7V-1.6V=1.1V.So visible in the situation that these two kinds of unequally loaded resistances, the value of Vds is different, and according to the I-V formula of transistor state of saturation, can find under the both of these case, the actual electric current I o that inputs to described load departs from ideal value fully, so the electric current I o that exports load to changes with the change in resistance of load.
2, another situation is that the constant and VCC of the resistance of load is when changing, as mentioned above, for example work as VCC=2.7V, when Ir=1mA and n=8, the ideal value of Io is 8mA, when the resistance R=100 of load ohm, Vout=Io * R=8 * 100=0.8V, so Vds=VCC-Vout=2.7V-0.8V=1.9V, and when VCC changed into 4V, so Vds=VCC-Vout=4V-0.8V=3.2V was in the situation that two kinds of different VCC, because the Vds of PMOS pipe P2 is different so that the actual electric current I o that injects load departs from ideal value, so output current Io changes with the variation of VCC.
The electric current controllability that makes constant-current source circuit output of above two shortcomings is relatively poor, and particularly in the time of low voltage difference, the value difference of the value of output current and the output current of design object is different larger.
Summary of the invention
The technical problem to be solved in the present invention is the relatively poor defective of electric current controllability in order to export in the constant-current source circuit that overcomes prior art, a kind of constant current source is provided, the voltage of the output terminal by keeping described constant current source, thus so that output current keeps being stable at a fixed value.
The present invention solves above-mentioned technical matters by following technical proposals:
The invention provides a kind of constant current source, comprise one first current mirror, wherein said the first current mirror comprises a current input terminal, one first current output terminal and one second current output terminal;
Be characterized in that described constant current source comprises that also an electric current keeps the unit, wherein said electric current is kept the unit and is comprised a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor;
Wherein said the first transistor and the 3rd transistorized conductive path are serially connected with between described the first current output terminal and the one first reference potential terminal successively, and described transistor seconds and the 4th transistorized conductive path are serially connected with between described the second current output terminal and described the first reference potential terminal successively;
The grid of described the first transistor and the grid of transistor seconds are electrically connected with described the first current output terminal, and the described the 3rd transistorized grid and the 4th transistorized grid are electrically connected with described the second current output terminal; The drain electrode of described transistor seconds also is electrically connected with an external loading.
Preferably, described the first current mirror comprises one the 5th transistor, one the 6th transistor and one the 7th transistor, the wherein said the 5th transistorized conductive path is serially connected with between described current input terminal and the one second reference potential terminal, the described the 5th transistorized grid and drain electrode are electrically connected, the described the 6th transistorized conductive path is serially connected with between described the first current output terminal and described the second reference potential terminal, the described the 7th transistorized conductive path is serially connected with between described the second current output terminal and described the second reference potential terminal, and the described the 6th transistorized grid and the 7th transistorized grid are electrically connected with the described the 5th transistorized grid.
Preferably, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor are the MOSFET pipe.
Preferably, described the first transistor, transistor seconds, the 3rd transistor and the 4th transistor are the PMOS pipe, and described the 5th transistor, the 6th transistor and the 7th transistor are the NMOS pipe.
Preferably, described the first reference potential terminal has a constant voltage.
Preferably, described the second reference potential terminal ground connection.
Preferably, described the 5th transistor, the 6th transistor are all identical with the 7th transistorized length breadth ratio.
Preferably, the 3rd transistor is identical with the 4th transistorized length breadth ratio.
Preferably, the ratio of the length breadth ratio of the length breadth ratio of described the first transistor and transistor seconds is more than or equal to 1.
The present invention also provides a kind of constant current source, comprises one first current mirror, and wherein said the first current mirror comprises a current input terminal and a current output terminal;
Be characterized in that described constant current source comprises that also an electric current keeps the unit, wherein said electric current is kept the unit and is comprised a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor;
Wherein said the first transistor and the 3rd transistorized conductive path are serially connected with between described current output terminal and the one first reference potential terminal successively, and described transistor seconds and the 4th transistorized conductive path are serially connected with between an external loading and described the first reference potential terminal successively;
The grid of described the first transistor and the grid of transistor seconds are electrically connected with one second reference potential terminal, and the described the 3rd transistorized grid and the 4th transistorized grid are electrically connected with one the 3rd reference potential terminal.
Preferably, described the first current mirror comprises one the 5th transistor and one the 6th transistor, the wherein said the 5th transistorized conductive path is serially connected with between described current input terminal and one the 4th reference potential terminal, the described the 5th transistorized grid and drain electrode are electrically connected, the described the 6th transistorized conductive path is serially connected with between described current output terminal and described the 4th reference potential terminal, and the described the 6th transistorized grid is electrically connected with the described the 5th transistorized grid.
Preferably, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are the MOSFET pipe.
Preferably, described the first transistor, transistor seconds, the 3rd transistor and the 4th transistor are the PMOS pipe, and described the 5th transistor and the 6th transistor are the NMOS pipe.
Preferably, described the first reference potential terminal, the second reference potential terminal and the 3rd reference potential terminal have respectively a constant voltage.
Preferably, described the 4th reference potential terminal ground connection.
Preferably, described the 5th transistor is identical with the 6th transistorized length breadth ratio.
Preferably, the ratio of the length breadth ratio of the length breadth ratio of the ratio of the 3rd transistor length breadth ratio and the 4th transistorized length breadth ratio and described the first transistor and transistor seconds is identical.
Preferably, the ratio of the length breadth ratio of the length breadth ratio of described the first transistor and transistor seconds is more than or equal to 1.
Positive progressive effect of the present invention is:
Constant current source of the present invention is kept the unit by electric current, keeps the voltage of current source output current end, thereby so that the electric current of constant current source output not in the impact of the resistance that is subject to load, thereby stablized the size of the electric current of constant current source output.
Description of drawings
Fig. 1 is the structural representation of the basic constant-current source circuit of prior art.
Fig. 2 is the structural representation of the first embodiment of constant current source of the present invention.
Fig. 3 is the structural representation of the second embodiment of constant current source of the present invention.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.
The first embodiment:
As shown in Figure 2, the constant current source of the present embodiment comprises that one first current mirror 1 and an electric current keep unit 2, and described the first current mirror 1 is used for output one fixed current.Comprise one the 5th transistor MN1, one the 6th transistor MN2 and one the 7th transistor MN3 described in the present embodiment in the first current mirror 1.Described the 5th transistor MN1, the 6th transistor MN2 and the 7th transistor MN3 are the NMOS pipe.
The source electrode of wherein said the 5th transistor MN1 with is connected the second reference potential terminal V2 and connects, in the present embodiment because described the second reference potential terminal ground connection, so the electromotive force on the second reference potential terminal V2 is zero.The drain electrode of the 5th transistor MN1 described in the present embodiment is electrically connected with a current input terminal IN, and wherein said the 5th transistor MN1 grid and drain electrode are electrically connected.
The source electrode of described the 6th transistor MN2 is connected in one first current output terminal A of the first current mirror 1, and the drain electrode of described the 6th transistor MN2 is connected with described the second reference potential terminal V2.The source electrode of described the 7th transistor MN3 is connected in one second current output terminal B of the first current mirror 1, and the drain electrode of described the 7th transistor MN3 is connected with described the second reference potential terminal V2.The grid of the grid of described the 6th transistor MN2 and the 7th transistor MN3 all is electrically connected with the grid of described the 5th transistor MN1.
The length breadth ratio of the 5th transistor MN1 described in the present embodiment, the 6th transistor MN2 and the 7th transistor MN3 is all identical, and since the 5th transistor MN1, the 6th transistor MN2 and the 7th transistor MN3 all work and the saturation region, so according to saturation region current formula and current mirror principle, the electric current of described the first current output terminal A and the second current output terminal B output is big or small identical with the reference current of current input terminal IN reception.
Can be by the ratio between the length breadth ratio of regulating described the 5th transistor MN1, the 6th transistor MN2 and the 7th transistor MN3 in the present embodiment, thus the proportionate relationship between the reference current of the electric current of regulating described the first current output terminal A and the second current output terminal B output and current input terminal reception.The first current mirror 1 can also adopt the current-mirror structure of other kinds to realize described in the present embodiment in addition.
Electric current described in the present embodiment is kept unit 2 and is comprised a first transistor MP1, a transistor seconds MP2, one the 3rd transistor MP3 and one the 4th transistor MP4.Described the first transistor MP1, transistor seconds MP2, the 3rd transistor MP3 and the 4th transistor MP4 are the PMOS pipe.
The first reference potential terminal V1 described in the present embodiment is connected source electrode and is connected with the first transistor MP1, the first reference potential terminal V1 is connected with the power supply with forward constant voltage described in the present embodiment, so have a constant positive voltage on described the first reference potential terminal V1.The drain electrode of described the first transistor MP1 be connected the source electrode of the 3rd transistor MP3 and connect, the first current output terminal A of the drain electrode of described the 3rd transistor MP3 and described the first current mirror 1 is electrically connected; Namely when described the first transistor MP1 and described the 3rd transistor MP3 conducting, consist of the conductive path of a conducting at described the first reference potential terminal V1 and described the first current output terminal A.
Described the first reference potential terminal V1 also is connected with the source electrode of transistor seconds MP2, the drain electrode of described transistor seconds MP2 be connected the source electrode of the 4th transistor MP4 and connect, the second current output terminal B of the drain electrode of described the 4th transistor MP4 and described the first current mirror 1 is electrically connected; Namely when described transistor seconds MP2 and described the 4th transistor MP4 conducting, consist of the conductive path of a conducting at described the first reference potential terminal V1 and described the second current output terminal B.
The grid of the grid of described the first transistor MP1 and transistor seconds MP2 is electrically connected with described the first current output terminal A, and the grid of the grid of described the 3rd transistor MP3 and the 4th transistor MP4 is electrically connected with described the second current output terminal B; The drain electrode of described transistor seconds MP2 also is electrically connected with an external loading, thereby provides a fixing electric current for external loading.
Wherein the 3rd transistor MP3 is identical with the length breadth ratio of the 4th transistor MP4 described in the present embodiment, and the ratio of the length breadth ratio of the length breadth ratio of same described the first transistor MP1 and transistor seconds MP2 is N, wherein N 〉=1.Wherein said the 3rd transistor MP3 and the 4th transistor MP4, and the current mirroring circuit that consists of respectively of described the first transistor MP1 and transistor seconds MP2.
The principle of work of the constant current source of the present embodiment is as follows:
Described the first current mirror 1 receives reference current Iref by current input terminal IN, described the first current mirror 1 is according to saturation region current formula and current mirror principle, respectively at the first current output terminal A of described the first current mirror 1 current Ib 1 and the Ib2 identical with described reference current Iref with the second current output terminal B output current value.
Because the 3rd transistor MP3 is identical with the length breadth ratio of the 4th transistor MP4 described in the present embodiment, and flow through respectively described the 3rd transistor MP3 and the current Ib 1 of the 4th transistor MP4 and the equal and opposite in direction of Ib2, so according to the saturation region current formula, this moment the 3rd transistor MP3 grid and the grid of voltage difference Vgs3 and the 4th transistor MP4 between the drain electrode and drain between the equal and opposite in direction of voltage difference Vgs4.And described the 3rd transistor MP3 is identical with the grid voltage of the 4th transistor MP4, thus this moment described the 3rd transistor MP3 and the 4th transistor MP4 source electrode on voltage must equate.
Voltage in the drain electrode of described the first transistor MP1 and transistor seconds MP2 is identical at this moment, so this moment, described the first transistor MP1 and transistor seconds MP2 consisted of a simple current mirror, and the ratio of the length breadth ratio of the length breadth ratio of described the first transistor MP1 and transistor seconds MP2 is N, so according to the current mirror principle, the current value of transistor seconds MP2 of flowing through this moment be flow through the first transistor MP1 current value N doubly.
The electric current of described the first transistor MP1 is Ib1 because flow through this moment, the value of the electric current I o of transistor seconds MP2 is N * Ib1 so flow through, again because the electric current of the 4th transistor MP4 that flows through is Ib2, and described the 4th transistor MP4 and transistor seconds MP2 serial connection, described current Ib 2 is big or small identical with current Ib 1 volume, the drain electrode of described transistor seconds MP2 also is connected with an external loading in addition, is (N-1) Ib1 so flow to the electric current I L of external loading this moment.
Again because the equal and opposite in direction of current Ib 1 and reference current Iref described in the present embodiment, so described electric current I L is (N-1) Iref.
So the voltage of the drain electrode by keeping described transistor seconds MP2 among the embodiment is a fixing electric current thereby keep output current, thereby overcome the impact that conventional current mirror output current easily is subject to the impedance of load.
The second embodiment:
As shown in Figure 3, the constant current source of the present embodiment comprises that one first current mirror 1 and an electric current keep unit 2, and described the first current mirror 1 is used for output one fixed current.The first current mirror 1 described in the present embodiment comprises one the 5th transistor MN1 and one the 6th transistor MN2.Described the 5th transistor MN1 and the 6th transistor MN2 are the NMOS pipe.
The source electrode of wherein said the 5th transistor MN1 with is connected the 4th reference potential terminal V4 and connects, in the present embodiment because described the 4th reference potential terminal ground connection, so the electromotive force on the 4th reference potential terminal V4 is zero.The drain electrode of the 5th transistor MN1 described in the present embodiment is electrically connected with a current input terminal IN, and wherein said the 5th transistor MN1 grid and drain electrode are electrically connected.
The source electrode of described the 6th transistor MN2 is connected in a current output terminal OUT of the first current mirror 1, and the drain electrode of described the 6th transistor MN2 is connected with described the 4th reference potential terminal V4.And the grid of described the 6th transistor MN2 is electrically connected with the grid of described the 5th transistor MN1.
The length breadth ratio of the 5th transistor MN1 described in the present embodiment and the 6th transistor MN2 is all identical, and since the 5th transistor MN1 and the 6th transistor MN2 all work and the saturation region, so according to saturation region current formula and current mirror principle, the reference current of the electric current of described current output terminal OUT output and current input terminal IN reception big or small identical.
Proportionate relationship between the electric current that can also regulate the output of described current output terminal by the ratio between the length breadth ratio of regulating described the 5th transistor MN1 and the 6th transistor MN2 in the present embodiment and the reference current of current input terminal IN reception.The first current mirror 1 can also adopt the current-mirror structure of other kinds to realize described in the present embodiment in addition.
Electric current described in the present embodiment is kept unit 2 and is comprised a first transistor MP1, a transistor seconds MP2, one the 3rd transistor MP3 and one the 4th transistor MP4.Described the first transistor MP1, transistor seconds MP2, the 3rd transistor MP3 and the 4th transistor MP4 are the PMOS pipe.
The first reference potential terminal V1 described in the present embodiment is connected source electrode and is connected with the first transistor MP1, the first reference potential terminal V1 is connected with the power supply with forward constant voltage described in the present embodiment, so have a constant positive voltage on described the first reference potential terminal V1.The drain electrode of described the first transistor MP1 be connected the source electrode of the 3rd transistor MP3 and connect, the current output terminal OUT of the drain electrode of described the 3rd transistor MP3 and described the first current mirror 1 is electrically connected; Namely when described the first transistor MP1 and described the 3rd transistor MP3 conducting, consist of the conductive path of a conducting at described the first reference potential terminal V1 and described current output terminal OUT.
Described the first reference potential terminal V1 also is connected with the source electrode of transistor seconds MP2, the drain electrode of described transistor seconds MP2 be connected the source electrode of the 4th transistor MP4 and connect, the drain electrode of described the 4th transistor MP4 and an external loading are electrically connected; Namely when described transistor seconds MP2 and described the 4th transistor MP4 conducting, between described the first reference potential terminal V1 and described external loading, consist of the conductive path of a conducting.
The grid of the grid of described the first transistor MP1 and transistor seconds MP2 is electrically connected with one second reference potential terminal V2, and the grid of the grid of described the 3rd transistor MP3 and the 4th transistor MP4 is electrically connected with one the 3rd reference potential terminal V3.The second reference potential terminal V2 described in the present embodiment and described the 3rd reference potential terminal V3 are electrically connected with power supply with forward constant voltage etc. respectively, so described the second reference potential terminal V2 and described the 3rd reference potential terminal V3 have respectively a constant positive voltage.Wherein the first reference potential terminal V1 described in the present embodiment, described the second reference potential terminal V2 are not identical with constant positive voltage on described the 3rd reference potential terminal V3.
And the first reference potential terminal V1 described in the present embodiment, described the second reference potential terminal V2 and described the 3rd reference potential terminal V3 common so that described the first transistor MP1, transistor seconds MP2, the 3rd transistor MP3 and the 4th transistor MP4 all work and the saturation region.
Wherein the ratio of the length breadth ratio of the length breadth ratio of the ratio of the length breadth ratio of the 3rd transistor MP3 described in the present embodiment and the length breadth ratio of the 4th transistor MP4 and described the first transistor MP1 and transistor seconds MP2 is identical, and described ratio is N, wherein N 〉=1.Wherein said the 3rd transistor MP3 and the 4th transistor MP4, and the current mirroring circuit that consists of respectively of described the first transistor MP1 and transistor seconds MP2.
The principle of work of the constant current source of the present embodiment is as follows:
Described the first current mirror 1 receives reference current Iref by current input terminal IN, described the first current mirror 1 is according to saturation region current formula and current mirror principle, in the current output terminal OUT of described the first current mirror 1 output current value current Ib identical with described reference current Iref.
The first reference potential terminal V1 described in the present embodiment, described the second reference potential terminal V2 and described the 3rd reference potential terminal V3 are so that described the first transistor MP1, transistor seconds MP2, the 3rd transistor MP3 and the 4th transistor MP4 all work in the saturation region, because the first transistor MP1 and transistor seconds MP2 consist of current-mirror structure, described the 3rd transistor MP3 and the 4th transistor MP4 also consist of current-mirror structure, and the electric current on described the first transistor MP1 and the 3rd transistor MP3 is Ib, so the drain voltage of the drain voltage of described the first transistor MP1 and transistor seconds MP2 can only be identical, because based on the current mirror principle, in the described the first transistor MP1 situation identical with electric current on the 3rd transistor MP3, the drain voltage of and if only if described the first transistor MP1 is identical with the drain voltage of transistor seconds MP2, and the electric current of the transistor seconds MP2 that flows through this moment just equates with the electric current of the 4th transistor MP4.
And the ratio of the length breadth ratio of the length breadth ratio of the ratio of the length breadth ratio of the length breadth ratio of described the 3rd transistor MP3 and the 4th transistor MP4 and described the first transistor MP1 and transistor seconds MP2 is N, so flow through this moment the current value of transistor seconds MP2 be flow through the first transistor MP1 current value N doubly.The electric current I L of described transistor seconds MP2 and the 4th transistor MP4 of namely flowing through this moment is N * Ib.
Again because described current Ib is identical with the current value of reference current kef, so described IL is N * Iref.So flowing into the electric current I L of external loading from the drain electrode of described the 4th transistor MP4 is N * Iref.
So in the constant voltage source of the present embodiment when keeping output and not being subjected to a fixed current of external loading impedance influences, so that the ratio between the ratio of described output current and reference current and the transistorized length breadth ratio is consistent, thereby improved the currents match degree.
Although more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, protection scope of the present invention is limited by appended claims.Those skilled in the art can make various changes or modifications to these embodiments under the prerequisite that does not deviate from principle of the present invention and essence, but these changes and modification all fall into protection scope of the present invention.
Claims (18)
1. a constant current source comprises one first current mirror, and wherein said the first current mirror comprises a current input terminal, one first current output terminal and one second current output terminal;
It is characterized in that, described constant current source comprises that also an electric current keeps the unit, and wherein said electric current is kept the unit and comprised a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor;
Wherein said the first transistor and the 3rd transistorized conductive path are serially connected with between described the first current output terminal and the one first reference potential terminal successively, and described transistor seconds and the 4th transistorized conductive path are serially connected with between described the second current output terminal and described the first reference potential terminal successively;
The grid of described the first transistor and the grid of transistor seconds are electrically connected with described the first current output terminal, and the described the 3rd transistorized grid and the 4th transistorized grid are electrically connected with described the second current output terminal; The drain electrode of described transistor seconds also is electrically connected with an external loading.
2. constant current source as claimed in claim 1, it is characterized in that, described the first current mirror comprises one the 5th transistor, one the 6th transistor and one the 7th transistor, the wherein said the 5th transistorized conductive path is serially connected with between described current input terminal and the one second reference potential terminal, the described the 5th transistorized grid and drain electrode are electrically connected, the described the 6th transistorized conductive path is serially connected with between described the first current output terminal and described the second reference potential terminal, the described the 7th transistorized conductive path is serially connected with between described the second current output terminal and described the second reference potential terminal, and the described the 6th transistorized grid and the 7th transistorized grid are electrically connected with the described the 5th transistorized grid.
3. constant current source as claimed in claim 2 is characterized in that, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor are the MOSFET pipe.
4. constant current source as claimed in claim 3 is characterized in that, described the first transistor, transistor seconds, the 3rd transistor and the 4th transistor are the PMOS pipe, and described the 5th transistor, the 6th transistor and the 7th transistor are the NMOS pipe.
5. such as each described constant current source among the claim 1-4, it is characterized in that, described the first reference potential terminal has a constant voltage.
6. such as each described constant current source among the claim 2-4, it is characterized in that described the second reference potential terminal ground connection.
7. such as each described constant current source among the claim 2-4, it is characterized in that, described the 5th transistor, the 6th transistor are all identical with the 7th transistorized length breadth ratio.
8. such as each described constant current source among the claim 1-4, it is characterized in that, the 3rd transistor is identical with the 4th transistorized length breadth ratio.
9. such as each described constant current source among the claim 1-4, it is characterized in that, the ratio of the length breadth ratio of described the first transistor and the length breadth ratio of transistor seconds is more than or equal to 1.
10. a constant current source comprises one first current mirror, and wherein said the first current mirror comprises a current input terminal and a current output terminal;
It is characterized in that, described constant current source comprises that also an electric current keeps the unit, and wherein said electric current is kept the unit and comprised a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor;
Wherein said the first transistor and the 3rd transistorized conductive path are serially connected with between described current output terminal and the one first reference potential terminal successively, and described transistor seconds and the 4th transistorized conductive path are serially connected with between an external loading and described the first reference potential terminal successively;
The grid of described the first transistor and the grid of transistor seconds are electrically connected with one second reference potential terminal, and the described the 3rd transistorized grid and the 4th transistorized grid are electrically connected with one the 3rd reference potential terminal.
11. constant current source as claimed in claim 10, it is characterized in that, described the first current mirror comprises one the 5th transistor and one the 6th transistor, the wherein said the 5th transistorized conductive path is serially connected with between described current input terminal and one the 4th reference potential terminal, the described the 5th transistorized grid and drain electrode are electrically connected, the described the 6th transistorized conductive path is serially connected with between described current output terminal and described the 4th reference potential terminal, and the described the 6th transistorized grid is electrically connected with the described the 5th transistorized grid.
12. constant current source as claimed in claim 11 is characterized in that, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are the MOSFET pipe.
13. constant current source as claimed in claim 12 is characterized in that, described the first transistor, transistor seconds, the 3rd transistor and the 4th transistor are the PMOS pipe, and described the 5th transistor and the 6th transistor are the NMOS pipe.
14. such as each described constant current source among the claim 10-13, it is characterized in that, described the first reference potential terminal, the second reference potential terminal and the 3rd reference potential terminal have respectively a constant voltage.
15., it is characterized in that described the 4th reference potential terminal ground connection such as each described constant current source among the claim 11-13.
16. such as each described constant current source among the claim 11-13, it is characterized in that, described the 5th transistor is identical with the 6th transistorized length breadth ratio.
17. such as each described constant current source among the claim 11-13, it is characterized in that, the ratio of the 3rd transistor length breadth ratio and the 4th transistorized length breadth ratio is identical with the ratio of the length breadth ratio of the length breadth ratio of described the first transistor and transistor seconds.
18. constant current source as claimed in claim 17 is characterized in that, the ratio of the length breadth ratio of described the first transistor and the length breadth ratio of transistor seconds is more than or equal to 1.
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| CN2012100765131A CN103324229A (en) | 2012-03-21 | 2012-03-21 | Constant current source |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105022441A (en) * | 2014-04-30 | 2015-11-04 | 中国科学院声学研究所 | Temperature-independent current reference |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105022441A (en) * | 2014-04-30 | 2015-11-04 | 中国科学院声学研究所 | Temperature-independent current reference |
| CN105022441B (en) * | 2014-04-30 | 2016-09-14 | 中国科学院声学研究所 | A kind of temperature independent integrated circuit current reference source |
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Application publication date: 20130925 |