CN103311214A - 一种用于叠层封装的基板 - Google Patents
一种用于叠层封装的基板 Download PDFInfo
- Publication number
- CN103311214A CN103311214A CN2013101763689A CN201310176368A CN103311214A CN 103311214 A CN103311214 A CN 103311214A CN 2013101763689 A CN2013101763689 A CN 2013101763689A CN 201310176368 A CN201310176368 A CN 201310176368A CN 103311214 A CN103311214 A CN 103311214A
- Authority
- CN
- China
- Prior art keywords
- substrate
- cavity
- stacked package
- dam
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 238000004806 packaging method and process Methods 0.000 title abstract description 17
- 238000005538 encapsulation Methods 0.000 claims description 29
- 238000007789 sealing Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013101763689A CN103311214A (zh) | 2013-05-14 | 2013-05-14 | 一种用于叠层封装的基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013101763689A CN103311214A (zh) | 2013-05-14 | 2013-05-14 | 一种用于叠层封装的基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103311214A true CN103311214A (zh) | 2013-09-18 |
Family
ID=49136267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2013101763689A Pending CN103311214A (zh) | 2013-05-14 | 2013-05-14 | 一种用于叠层封装的基板 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103311214A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017024854A1 (zh) * | 2015-08-13 | 2017-02-16 | 上海航天电子通讯设备研究所 | 一种基于铝基板的三维封装用垂直互连结构及其制备方法 |
CN108428672A (zh) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | 超宽带射频微***的陶瓷双面三维集成架构及封装方法 |
WO2019024813A1 (zh) * | 2017-07-31 | 2019-02-07 | 华为技术有限公司 | 一种嵌入式基板 |
CN111816577A (zh) * | 2020-05-15 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | 基板双面封装芯片的方法和基板双面封装芯片的结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5043794A (en) * | 1990-09-24 | 1991-08-27 | At&T Bell Laboratories | Integrated circuit package and compact assemblies thereof |
US5838060A (en) * | 1995-12-12 | 1998-11-17 | Comer; Alan E. | Stacked assemblies of semiconductor packages containing programmable interconnect |
US6172423B1 (en) * | 1997-11-15 | 2001-01-09 | Hyundai Electronics Industries Co., Ltd. | Layer-type ball grid array semiconductor package and fabrication method thereof |
US20020047214A1 (en) * | 2000-10-16 | 2002-04-25 | Yuichi Morinaga | Multi-chip package-type semiconductor device |
CN101159259A (zh) * | 2007-11-09 | 2008-04-09 | 中国科学院上海微***与信息技术研究所 | 三维多芯片封装模块和制作方法 |
CN101436571A (zh) * | 2007-11-16 | 2009-05-20 | 英飞凌科技股份有限公司 | 电器件和方法 |
-
2013
- 2013-05-14 CN CN2013101763689A patent/CN103311214A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5043794A (en) * | 1990-09-24 | 1991-08-27 | At&T Bell Laboratories | Integrated circuit package and compact assemblies thereof |
US5838060A (en) * | 1995-12-12 | 1998-11-17 | Comer; Alan E. | Stacked assemblies of semiconductor packages containing programmable interconnect |
US6172423B1 (en) * | 1997-11-15 | 2001-01-09 | Hyundai Electronics Industries Co., Ltd. | Layer-type ball grid array semiconductor package and fabrication method thereof |
US20020047214A1 (en) * | 2000-10-16 | 2002-04-25 | Yuichi Morinaga | Multi-chip package-type semiconductor device |
CN101159259A (zh) * | 2007-11-09 | 2008-04-09 | 中国科学院上海微***与信息技术研究所 | 三维多芯片封装模块和制作方法 |
CN101436571A (zh) * | 2007-11-16 | 2009-05-20 | 英飞凌科技股份有限公司 | 电器件和方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017024854A1 (zh) * | 2015-08-13 | 2017-02-16 | 上海航天电子通讯设备研究所 | 一种基于铝基板的三维封装用垂直互连结构及其制备方法 |
WO2019024813A1 (zh) * | 2017-07-31 | 2019-02-07 | 华为技术有限公司 | 一种嵌入式基板 |
CN108428672A (zh) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | 超宽带射频微***的陶瓷双面三维集成架构及封装方法 |
CN111816577A (zh) * | 2020-05-15 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | 基板双面封装芯片的方法和基板双面封装芯片的结构 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NATIONAL CENTER FOR ADVANCED PACKAGING Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150228 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100029 CHAOYANG, BEIJING TO: 214135 WUXI, JIANGSU PROVINCE |
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TA01 | Transfer of patent application right |
Effective date of registration: 20150228 Address after: Taihu international science and Technology Park in Jiangsu province Wuxi City Linghu road 214135 Wuxi national hi tech Industrial Development Zone No. 200 Chinese Sensor Network International Innovation Park building D1 Applicant after: National Center for Advanced Packaging Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Applicant before: Institute of Microelectronics of the Chinese Academy of Sciences |
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RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130918 |
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RJ01 | Rejection of invention patent application after publication |