CN103310850B - The BIST Structure of network-on-chip resource node storer and self-test method - Google Patents
The BIST Structure of network-on-chip resource node storer and self-test method Download PDFInfo
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Abstract
The present invention is BIST Structure and the self-test method of network-on-chip resource node storer, this BIST Structure comprises the BIST controller building on fpga chip, is embedded in resource-network interface and BIST interface, test graph builder and the test response analyzer of corresponding router in addition.BIST controller is connected with external test facility through Peripheral Interface.This method is: external test facility sends instruction to BIST controller and starts test procedure; Is BIST controller according to March? C+ testing algorithm program sends enable signal and state selection signal to each test module, under each test mode, carry out read-write operation to each address of SRAM, finds that fault stops immediately.Test result sends to external test facility.Test duration of the present invention reduces half, and the route network of multiplexing NoC is as test data path, and data transmission is reliable and secure, and chip-area overhead is little; Fault coverage is higher.
Description
Technical field
The present invention relates to network-on-chip (Network-on-chip, NoC) technical field of measurement and test, be specifically related to BIST Structure and the self-test method of network-on-chip resource node storer.
Background technology
Along with the progress of semiconductor technology and the constantly perfect of SoC (System-on-chip, SoC) technology, SoC technology has become the major design technology of integrated circuit in this century.But, it exposes limitation in method for designing, architecture, especially when the IP kernel number comprised in SoC increases to thousands of time, the existing huge challenge taking bus structure as the SoC technology of communication infrastructure and be faced with in performance, power consumption, time delay and reliability etc.Produced problem is embodied in following three aspects:
1. bus-structured address space is limited thus cause the problem of its extendability difference.
2. bus structure adopt time-sharing communication thus cause communication efficiency lower, and multiple user shared bus resource simultaneously in bus, at a time can not more than a pair at the number of users of an enterprising Serial Communication of bus.
3. bus structure are due to the problem of the power consumption that adopts the communication mechanism of global synchronization and cause and area.
In order to solve above problem, the concept of NoC was proposed by Royal Swedish Academy of Sciences in the beginning of the century.Its core concept is the concept and methodology used for reference and transplant in computer network, integrated for multiple subsystem (SoC or IP of existing scale).NoC adopts packet-switch technology to substitute traditional bus communication mode, achieve and calculate and being separated of communicating, each resource node is operated in oneself clock zone, then asynchronous communication is carried out by OCN (OpenComputerNetwork) between different resource nodes, thus solve the bottleneck problem of power consumption, area and the chip-on communication that huge Clock Tree brings, and solve clock synchronization issue.
NoC uses network to substitute bus following features:
1. have good address space extensibility, the number of resource node that in theory can be integrated is unrestricted;
2. good parallel communication ability is provided, thus improves data throughput and overall performance;
3. use globally asynchronous locally synchronous mechanism (GloballyAsynchronousLocallySynchronous, GALS), each resource node is operated in oneself clock zone, then asynchronous communication is carried out by OCN between different resource nodes, well solve the problem that bus structure single clock is synchronous, thus thoroughly solve power consumption and area for cutting that huge Clock Tree brings.
From integrated circuit is born, method for designing, manufacture method and method of testing are indivisible 3 ingredients of integrated circuit development all the time.But early stage in integrated circuit development, the more visual cognitive ability of people is in Design and manufacture field, and early stage integrated circuit logic design is relative with technology simply, and therefore the research of test methodology had once once been in a status got the brush-off.Along with the proposition of NoC architecture and method for designing, research based on the network-on-chip measuring technology of NoC is just being subject to increasing attention, due to a large amount of uses of memory I P core in NoC system, how effective test is at a high speed carried out to storer in NoC system and also become the problem of a focus instantly.
Traditional measuring technology because testing process is complicated, consuming time, costly, fault detect rate is low, can not meet needed for day by day complicated integrated circuit.
Built-in self-test (English is Built-inSelfTest, its BIST that abridges) technology overcomes above-mentioned shortcoming, and it effectively can solve conventional art and the insurmountable problem of boundary scan technique as novel design for Measurability method.Because BIST is not On-board test vector in external test facility, but test and excitation circuit and response analysis circuit are added in circuit-under-test, utilize the test function of a part of completing circuit of circuit-under-test itself.BIST has that Self-adaptive process is short, test process complexity is low and fault detect rate advantages of higher, and can save testing cost, shortens the test duration, improves the reliability that system uses.
The design of the built-in self-test of existing a large amount of bus structure chip SoC storer at present occurs, but there is not yet report storer in NoC system being adopted to build-in self-test method.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of BIST Structure and self-test method of network-on-a-chip storer, and it has, and test structure is simple, fault coverage is high, resource utilization is low, low-power consumption and the strong feature of extendability.
The BIST Structure of the network-on-chip resource node storer of the present invention's design, described network-on-chip is the chip based on FPGA, some routers are interconnected by external channel, the router network formed, its structure is 2 dimension mesh topology of rule, router in NoC adopts the worm hole data exchange mechanism based on Virtual Channel technology, routing algorithm adopts source route algorithm, each router is furnished with resource-network interface, resource-network interface is two-way data flow interface, each resource-network interface is through Bidirectional inner passage connection resource node respectively, resource node is IP kernel, or the general-purpose storage SRAM etc. outside sheet.The outer general-purpose storage SRAM of sheet that one of them router R2 connects through resource-network interface is resource node storer to be tested.
The BIST Structure of resource node storer comprises BIST controller, BIST interface, test graph builder and test response analyzer, and BIST controller builds on fpga chip, test graph builder and test response analyzer.The embedded BIST interface of resource-network interface of router R2, the resource network node build-in-test graphic generator of source router R1 and test response analyzer.
BIST controller is a limited algorithmic state machine, be responsible for the realization of testing algorithm and the control of state flow process, its enable signal output terminal connecting test graphic generator and BIST interface, the signal input part of the output terminal access BIST controller of test response analyzer, BIST controller is furnished with Peripheral Interface, external test facility is connected with BIST controller through this Peripheral Interface, instruction is sent to BIST controller, start this BIST Structure to test, BIST controller through this interface externally testing apparatus export the test result of this BIST Structure.
Test graph builder is a simple state machine, and be responsible for the sequence of test data generating resource node storer, sequence of test data is made up of corresponding test data background, and the data background state current according to BIST controller is determined.
Test response analysis module is an exclusive-OR network, be made up of data background device and XOR comparer, be responsible for the analysis of corresponding test data, the desirable data that the test response data of resource node storer and data background device provide are carried out xor operation, judges that whether test response data is correct accordingly.
BIST interface comprises SRAM address generator and SRAM controller, and SRAM address generator produces the read/write address of Current resource node memory, and realizes address ascending order or descending according to the flow process of testing algorithm.SRAM controller possesses the interface be connected with resource node storer, realizes the Read-write Catrol to resource node storer.The storer of certain resource node in NoC system can be operated in normal mode of operation or test pattern, after starting test, BIST controller sends to the switching signal of the storer of certain resource node to BIST interface, and the SRAM controller of BIST interface arranges this resource node and switches to normal mode of operation or test pattern.
According to the build-in self-test method of the network-on-chip resource node storer of the BIST Structure of the network-on-chip resource node storer of the invention described above design, key step is as follows:
I, the BIST Structure of network-on-chip resource node storer is built at on-chip network chip, BIST controller is set up at fpga chip, and the resource-network interface build-in-test module of corresponding router, namely the resource-network interface of object router R2 is connected to resource node storer to be measured, the embedded BIST interface of resource-network interface of R2, at resource network node build-in-test graphic generator and the test response analyzer of source router R1;
II, external test facility is connected with the Peripheral Interface of BIST controller, and external test facility sends instruction to BIST controller and starts test procedure;
III, BIST controller sends enable signal and state selection signal according to testing algorithm program to each test module, the embedded test graph builder of the resource-network interface of source router R1 is according to the state selection instructions of BIST controller and send instruction, generates current test data and sends test data to router network;
The switching working mode enable signal that BIST controller sends to the SRAM controller of the BIST interface of object router R2, this resource node storer switches to test pattern, receives the test data that test graph builder produces; The SRAM address generator of this BIST interface produces the read/write address of Current resource node memory, and realizes storer SRAM address ascending order to be measured or descending according to the flow process of testing algorithm;
IV, each test mode of this testing algorithm all has data writing operation and read data operation,
When performing data writing operation, the test graph builder transmission instruction that the resource-network interface of BIST controller to source router R1 is embedded, by the test data of the corresponding test mode of testing algorithm Program Generating;
Test data is packed according to routing packets form by the test graph builder that the resource-network interface of R1 is embedded, send into R1, through router Internet Transmission, arrive the object router R2 at resource node storer place, resource-network interface through R2 sends into its embedded BIST interface, deliver to resource node thus to carry out unpacking process, then test data is write resource node storer.This resource node memory operation, in test pattern, provides test response signal to test data, has pointed out a data writing operation.
When performing read data operation, the test response signal of above-mentioned resource node storer, pack at the routing packets form of BIST interface according to return path, resource-network interface residing for it sends into R2, transmit at router network, arrive router R1, enter the test response analyzer that the resource-network interface of R1 is embedded, carry out unpacking process, the XOR comparer of test response analyzer carries out xor operation to the desirable data that the test response data of resource node storer and data background device provide, judge that whether test response data is correct accordingly, and give BIST controller by result,
If V this test response data is correct, test response analyzer determines whether last test mode, if NO, then step IV is returned, the test graph builder transmission instruction that the resource-network interface of BIST controller to source router R1 is embedded, carries out data writing operation and the read data operation of next test mode by testing algorithm program;
If this test response data is correct, test response analyzer judges that this is last test mode, judge that whether this test is last SRAM address of storer to be measured again, if not last SRAM address, then return step IV, by the address ascending order of SRAM address generator or descending, the test of each test mode of testing algorithm requirement is carried out to next SRAM address; When judging this test last SRAM address as storer to be measured, terminating this test, the test result of this resource node storer fed back to BIST controller and sends to chip exterior testing apparatus to analyze; The switching working mode enable signal that simultaneously BIST controller sends to the SRAM controller of the BIST interface of router R2 is set to disarmed state, this resource node storer recovery normal mode of operation.
If this test response data mistake, be fault, test response analyzer stops the test to this resource node storer immediately, and test response analyzer sends test result to BIST controller, and test result is sent to external test facility by BIST controller.The follow-up works such as fault diagnosis and location are carried out by external test facility.
Described test result comprises the information such as theoretical test data, test response data, address information, test duration.
Testing algorithm described in step III is the MarchC+ algorithm improved, and its read-write operation is test cell with word, and the multiple data bit in word are collectively referred to as data background.The resource node storer bit wide of described network-on-a-chip is N position, and sequence of test data has log
2n+1.
Coupling fault between the word that so not only can check resource node storer, can also coupling fault in check word.In addition on the basis of MarchC+ algorithm, add the testing procedure detecting data retention fault, improve the coverage rate of fault test to a certain extent.
Test mode number n in BIST controller algorithm state machine is consistent with the number of March element in algorithm is M0 to Mn, algorithm original state in BIST controller is idle (idle), after starting test, algorithm state first gets test mode M0, if the response data of resource node storer does not find fault under this test mode, i.e. Sram_Error=0, transfers to next state M1 and tests.By that analogy, when not finding fault Sram_Error=0 in test process, M1, M2 is performed successively ... to the test mode of Mn, return original state afterwards and leave unused.When breaking down in test process, i.e. Sram_Error=1, stops test immediately.
Compared with prior art, the BIST Structure of network-on-chip resource node storer of the present invention and the advantage of self-test method as follows:
(1) BIST Structure on chip, directly produces test vector in fpga chip inside, and the test deadline carries out test required time than external testing apparatus and greatly reduces, and is only the half or less of the latter;
(2) router network of multiplexing network-on-chip is as test data access path, and data are transmitted according to the form of routing packets, and data transmission is reliable and secure, and do not need the expense of extra increase area, chip-area overhead is little;
(3) adopt the MarchC+ algorithm of Optimal improvements, fault coverage is higher, can detect persistent fault, state transfer fault, coupling fault, addressing fault, open fault, data retention fault etc.;
(4) effectively save testing cost, shorten the test duration, improve the reliability of test, be conducive to the Application and Development of network-on-chip.
Accompanying drawing explanation
Fig. 1 is the network-on-chip router schematic network structure based on FPGA of the BIST Structure embodiment of network-on-chip resource node storer; In figure: R represents router, S represents resource node, and ■ represents resource-network interface, and IC represents inner passage, and EC represents external channel, and SRAM represents resource node storer;
Fig. 2 is the BIST Structure schematic diagram of the BIST Structure embodiment of network-on-chip resource node storer;
Fig. 3 is the build-in self-test method embodiment test flow chart of network-on-chip resource node storer;
Fig. 4 is build-in self-test method embodiment data packet format and the microplate bit message structure schematic diagram of network-on-chip resource node storer;
Fig. 5 is the build-in self-test method Embodiment B IST controller algorithm state machine state transfer schematic diagram of network-on-chip resource node storer;
Fig. 6 is the build-in self-test method embodiment data writing operation block diagram of network-on-chip resource node storer;
Fig. 7 is the build-in self-test method embodiment data writing operation block diagram of network-on-chip resource node storer.
Embodiment
The BIST Structure embodiment of network-on-chip resource node storer
The network-on-chip that the BIST Structure embodiment of this network-on-chip resource node storer adopts is based on the chip of FPGA, as shown in Figure 1, 3 × 3 router R are interconnected by external channel EC, the router network of 2 dimension grid (2D-Mesh) topological structures of composition rule, router in NoC adopts the worm hole data exchange mechanism based on Virtual Channel technology, routing algorithm adopts source route algorithm, each router is by resource-network interface connection resource node, the outer general-purpose storage SRAM of sheet that one of them router R2 connects through resource-network interface is resource node storer to be tested, resource node storer to be tested below represents with SRAM.Resource-network interface is wherein two-way data flow interface.
The BIST Structure of this routine resource node storer as shown in Figure 2, according to function sub-module, design with Verilog hardware description language, comprise BIST controller, BIST interface, test graph builder and test response analyzer, BIST controller builds on fpga chip, the embedded BIST interface of resource-network interface of router R2, the resource network node build-in-test graphic generator of source router R1 and test response analyzer.
BIST controller is a limited algorithmic state machine, be responsible for the realization of testing algorithm and the control of state flow process, its enable signal output terminal connecting test graphic generator and BIST interface, the signal input part of the output terminal access BIST controller of test response analyzer, BIST controller is furnished with Peripheral Interface, external test facility is connected with BIST controller through this Peripheral Interface, as shown in Figure 2, the Peripheral Interface of the BIST controller of this example has three ports, a port in is used for external test facility and sends instruction to BIST controller, start this BIST Structure to test, another port re be used for BIST controller externally testing apparatus export the test result of this BIST Structure, 3rd port fi is used for BIST controller externally testing apparatus transmission test settling signal.
Test graph builder is a simple state machine, and be responsible for the sequence of test data generating SRAM, sequence of test data is made up of corresponding test data background, and the data background state current according to BIST controller is determined.
Test response analysis module is an exclusive-OR network, be made up of data background device and XOR comparer, be responsible for the analysis of corresponding test data, the desirable data that the test response data of SRAM and data background device provide carried out xor operation, judges that whether test response data is correct accordingly.
BIST interface comprises SRAM address generator and SRAM controller, and SRAM address generator produces the read/write address of current SRAM, and realizes address ascending order or descending according to the flow process of testing algorithm.SRAM controller possesses the interface be connected with SRAM, realizes the Read-write Catrol to SRAM.The storer of certain resource node in NoC system can be operated in normal mode of operation or test pattern, after starting test, BIST controller sends to the switching signal of the storer of certain resource node to BIST interface, and the SRAM controller of BIST interface arranges this resource node and switches to normal mode of operation or test pattern
According to the build-in self-test method of the network-on-chip resource node storer that the BIST Structure of the network-on-chip resource node storer of the invention described above design is set up, as shown in Figure 3, key step is as follows for its flow process:
I, the BIST Structure of network-on-chip resource node storer is built at on-chip network chip, as shown in Figure 2, BIST controller is set up at fpga chip, the resource-network interface build-in-test module of corresponding router, namely the resource-network interface of object router R2 is connected to resource node storer to be measured, the embedded BIST interface of resource-network interface of R2, at resource network node build-in-test graphic generator and the test response analyzer of source router R1;
II, external test facility is connected with the Peripheral Interface of BIST controller, and external test facility sends instruction to BIST controller and starts test procedure;
III, BIST controller sends enable signal and state selection signal according to testing algorithm program to each test module, the initialization of this BIST Structure.
The test graph builder that the resource-network interface of source router R1 is embedded, generate the sequence of test data of SRAM by testing algorithm, sequence of test data is made up of corresponding test data background.
After system electrification, test graph builder is by test data background write internal register, this routine test data background totally 5 groups, after the transmission data enable signal receiving BIST controller, determine the test data of current transmission according to the current data background state signal of BIST controller selection, current test data is sent to router network by the form forwarded according to route data.
The testing algorithm of this example is the MarchC+ algorithm improved, and its read-write operation take word as test cell, and the multiple data bit in word are collectively referred to as data background.The SRAM bit wide of this routine network-on-a-chip is N=16 position, and sequence of test data has log
2n+1=5.
When reading and writing data of testing algorithm is " 1 ", corresponding sequence of test data expands to
1：1111111111111111、
2：1010101010101010、
3：1100110011001100、
4：1111000011110000、
5、1111111100000000。
When reading and writing data of testing algorithm is " 0 ", corresponding sequence of test data expands to
1：0000000000000000、
2：0101010101010101、
3：0011001100110011、
4：0000111100001111
5：0000000011111111。
The data that test graph builder sends send into the resource-network interface of source router, to package and unpack test data according to the form that routes packet data exchanges.
The data that in network-on-chip, processing unit produces are called message (message), message are divided into the packet (packet) of regular length in NoC.The size of packet sets as the case may be, can be several byte, also can be all information in a slice memory field.Within a clock period, the message unit exchanged between routing node is called microplate (flit).A packet is made up of multiple microplate, and microplate width determines the channel bandwidth between resource node and between routing node.Generally, a packet is made up of multiple data microplate.As shown in Figure 4, the message transmitted in this routine network-on-chip is divided into multiple packets of regular length, and each data is surrounded by 8 microplates (flit), and each packet has a head microplate, 6 data microplates and a tail microplate.Head microplate comprises microplate type, Information sign, routing information, destination address and source data packet address.Tail microplate represents the termination of packet.Data microplate is the valid data transmitted, and is between a microplate and tail microplate.Each microplate of this example design has 18, and front two is microplate type information, and microplate type information 01 represents head microplate, and 10 represent tail microplate, and 00 represents data microplate.The microplate of resource-network interface to the packet of process adds microplate type information, and packet each microplate when resource node sends is 16.
Routing information identifies the path that data are transmitted at network-on-chip, is represented by 42 system numbers, the transmission path of the corresponding router of the digital corresponding data process of each, when this routing information is 1, represents and transmits in X direction, be 0 and transmit along Y-direction.Routing information in router read data packet head microplate, determines the path that packet forwards.Often automatically 1 is added through a router routing information in data transmission procedure.If the routing information in the data packet head microplate that source router sends is 0000, the 0th of read path information is 0, therefore this packet that source router sends transmits along Y-direction.When data have passed to next router, routing information adds 1 and becomes 0001, and the 1st of read path information is 0, and this packet still transmits along Y-direction by this router.
The transfer process of packet in network-on-chip is as follows: first by resource node, packed data and relevant handshake are sent to local resource-network interface, this resource-network interface adds microplate type information according to data message to the microplate of packet, then application is sent to local router, local routing feeds back to local resource network interface answer signal after receiving request signal, make it by data stored in the data buffer of resource-network interface; Data are taken out according to the destination address information of carrying in head microplate by resource-network interface from data buffer, by the alteration switch of resource-network interface, exported to output port by destination party, enter into next router, the data so just completed from a router to next router are transmitted.
BIST controller sends switching working mode enable signal to the SRAM controller of the BIST interface of R2, and this SRAM switches to test pattern, receives the test data that test graph builder produces; The SRAM address generator of this BIST interface produces the read/write address of current SRAM, and realizes address ascending order or descending according to the flow process of testing algorithm;
State number n in BIST controller algorithm state machine is consistent with the number of March element in algorithm, as shown in Figure 5, algorithm original state in BIST controller is idle (idle), after starting test, algorithm state first gets test mode M0, if the response data of SRAM does not find fault under this test mode, i.e. Sram_Error=0, transfer to next state M1 and test.By that analogy, in test process, work as Sram_Error=0, perform M1, M2 successively ... Mi ... to the test mode of Mn, finally for terminating test STOP, returning original state and leaving unused.When occurring Sram_Error=1 in test process, representing to there is fault, stopping test immediately.State transfer schematic diagram in BIST controller algorithm state machine as shown in Figure 5.
IV, each test mode of this testing algorithm all has data writing operation and read data operation,
When performing data writing operation, the embedded test graph builder of the resource-network interface of BIST controller to source router R1 sends and writes data command, by the test data of the corresponding test mode of testing algorithm Program Generating;
Test data is packed according to routing packets form by the test graph builder that the resource-network interface of R1 is embedded, send into R1, through router Internet Transmission, arrive the object router R2 at SRAM place, resource-network interface through R2 sends into its embedded BIST interface, deliver to resource node thus to carry out unpacking process, then test data is write SRAM.This SRAM works in test pattern, provides test response signal to test data.
SRAM write data structure and handshake block diagram are as shown in Figure 6.Data writing operation detailed process is as follows: when test data reaches object router R2, first signal Req is sent request to resource-network interface RNI, after obtaining answer signal Grant and be effective, the data Data_in [17:0] of 18 bit wides writes in the output buffer of RNI by router.The transponder of RNI finds there are effective data in the output buffer of RNI, just send read data request signal Read_ask to SRAM, after resource node receives this request signal, then effective to RNI feedback signal Read_en, signal, there is provided simultaneously and read clock Read_clk, from the output buffer of RNI, read data, resource node just starts read data data and will unpack before write SRAM when dataout_flag is effective, namely remove header.Now En_wr sets high by BIST controller, writes in SRAM, so just complete the write operation of a SRAM by the test data Data_out [15:0] of reduction 16 bit wide.
When performing read data operation, the test response signal of above-mentioned SRAM, pack at the routing packets form of BIST interface according to return path, resource-network interface residing for it sends into R2, transmit at router network, arrive router R1, enter the embedded test response analyzer of the resource-network interface of R1, carry out unpacking process, the XOR comparer of test response analyzer carries out xor operation to the desirable data that the test response data of SRAM and data background device provide, judge that whether test response data is correct accordingly, and give BIST controller by result;
SRAM read data structure and handshake block diagram are as shown in Figure 7.When performing read operation in testing algorithm, En_rd signal sets high by BIST controller, enters and reads SRAM data process.Read data operation detailed process is as follows: the SRAM data read packed and when route network transmits, first inquire about the value of Port_av, if Port_av=1 is that effectively Wren_in is set to effectively by resource node, to RNI request write data.After obtaining response, data are sent in router through RNI, in the process of RNI, the group bag device in RNI is preced with the microplate type information of 2 in data head microplate, right overhead microplate mark Flit_ahead be high level effective time, group bag device adds top microplate mark 01 to the microplate when advancing into, follow-up what enter is data microplates, adds data microplate mark 00, because 8 microplates are a frame, so after entering the 6th data, tailing mark 10.When each microplate of packet transmits in a network totally 18.The SRAM data read out to router R1, carries out test response analysis through router Internet Transmission, completes a SRAM read operation.
If V this test response data is correct, test response analyzer determines whether last test mode, if NO, then step IV is returned, the test graph builder transmission instruction that the resource-network interface of BIST controller to source router R1 is embedded, carries out data writing operation and the read data operation of next test mode by testing algorithm program;
If this test response data is correct, test response analyzer judges that this is last test mode, after this judge whether this SRAM address tested is last address again, if not last address, return step III, undertaken carrying out test operation to the next address of SRAM by the address ascending order of SRAM address generator or descending; If judge that this resource node address tested is as last address, the test of this SRAM terminates, the test result of this SRAM is fed back to BIST controller and sends to the external test facility of chip to analyze by test response analyzer, the switching working mode enable signal that simultaneously BIST controller sends to the SRAM controller of the BIST interface of R2 is set to disarmed state, this SRAM recovers normal mode of operation, receives and the data that in storage system, other resource node sends over; This test is completed to this.
If this test response data mistake, be fault, stop the test to this SRAM immediately, test response analyzer sends test result to BIST controller, and test result sends to external test facility to carry out the follow-up works such as fault diagnosis and location by BIST controller.
Described test result comprises the information such as theoretical test data, test response data, address information, test duration.
This routine multiplexing network-on-chip is as Test access mechanism, data are transmitted according to the form of routing packets, resource node storer in concurrent testing NoC system, tested SRAM is provided correctly and the guarantee of test data transmission reliably based on packet technology and source route algorithm in conjunction with 2D-Mesh network-on-chip router.Also improve MarchC testing algorithm pointedly.Interpretation shows, this example achieves the whole coverings comprising the most common failure such as persistent fault, state transfer fault, coupling fault, open fault, addressing fault, data retention fault.Compared with general testing scheme, the method for testing test duration of the built-in self-test of this example is shorter, compared with carrying out test, when testing the SRAM of 1KB, can reduce by the test duration of about 55% with external test facility.And due to this example adopt multiplexing NoC method test, so chip-area overhead is little.
Embodiment shows, method of testing of the present invention has certain advantage in fault coverage, test duration, chip-area overhead and extendability.Reliable and secure data transport service is provided and does not need the expense of extra increase area.
Above-described embodiment, be only the specific case further described object of the present invention, technical scheme and beneficial effect, the present invention is not defined in this.All make within scope of disclosure of the present invention any amendment, equivalent replacement, improvement etc., be all included within protection scope of the present invention.
Claims (7)
1. the BIST Structure of network-on-chip resource node storer, described network-on-chip is the chip based on FPGA, some routers are interconnected by external channel, the router network formed, its structure is 2 dimension mesh topology of rule, router in NoC adopts the worm hole data exchange mechanism based on Virtual Channel technology, routing algorithm adopts source route algorithm, each router is furnished with resource-network interface, resource-network interface is two-way data flow interface, each resource-network interface is through Bidirectional inner passage connection resource node respectively, the outer general-purpose storage SRAM of sheet that one of them router R2 connects through resource-network interface is resource node storer to be tested, it is characterized in that:
The BIST Structure of resource node storer comprises BIST controller, BIST interface, test graph builder and test response analyzer, and BIST controller builds on fpga chip; The embedded BIST interface of resource-network interface of router R2, the resource network node build-in-test graphic generator of source router R1 and test response analyzer;
BIST controller is a limited algorithmic state machine, be responsible for the realization of testing algorithm and the control of state flow process, its enable signal output terminal connecting test graphic generator and BIST interface, the signal input part of the output terminal access BIST controller of test response analyzer, BIST controller is furnished with Peripheral Interface, and external test facility is connected with BIST controller through this Peripheral Interface;
Test graph builder is a state machine, is responsible for the sequence of test data generating resource node storer;
Test response analysis module is an exclusive-OR network, is made up of data background device and XOR comparer, is responsible for the analysis of corresponding test data;
BIST interface comprises SRAM address generator and SRAM controller, and SRAM address generator produces the read/write address of Current resource node memory, and realizes address ascending order or descending according to the flow process of testing algorithm; SRAM controller possesses the interface be connected with resource node storer, realizes the Read-write Catrol to resource node storer.
2. the build-in self-test method of the network-on-chip resource node storer of the BIST Structure of network-on-chip resource node storer according to claim 1, is characterized in that key step is as follows:
I, the BIST Structure of network-on-chip resource node storer is built at on-chip network chip, BIST controller is set up at fpga chip, and the resource-network interface build-in-test module of corresponding router, namely the resource-network interface of router R2 is connected to resource node storer to be measured, the embedded BIST interface of resource-network interface of R2, at resource network node build-in-test graphic generator and the test response analyzer of source router R1;
II, external test facility is connected with the Peripheral Interface of BIST controller, and external test facility sends instruction to BIST controller and starts test procedure;
III, BIST controller sends enable signal and state selection signal according to testing algorithm program to each test module,
The embedded test graph builder of the resource-network interface of source router R1 is according to the state selection instructions of BIST controller and send instruction, generates current test data and sends test data to router network;
The switching working mode enable signal that BIST controller sends to the SRAM controller of the BIST interface of object router R2, this resource node storer switches to test pattern, receives the test data that test graph builder produces; The SRAM address generator of this BIST interface produces the read/write address of Current resource node memory, and realizes storer SRAM address ascending order to be measured or descending according to the flow process of testing algorithm;
IV, each test mode of this testing algorithm all has data writing operation and read data operation,
When performing data writing operation, the test graph builder transmission instruction that the resource-network interface of BIST controller to source router R1 is embedded, by the test data of the corresponding test mode of testing algorithm Program Generating;
Test data is packed according to routing packets form by the test graph builder that the resource-network interface of R1 is embedded, send into R1, through router Internet Transmission, arrive the object router R2 at resource node storer place, resource-network interface through R2 sends into its embedded BIST interface, deliver to resource node thus to carry out unpacking process, then test data is write resource node storer; This resource node memory operation, in test pattern, provides test response signal to test data, has pointed out a data writing operation;
When performing read data operation, the test response signal of above-mentioned resource node storer, pack at the routing packets form of BIST interface according to return path, resource-network interface residing for it sends into R2, transmit at router network, arrive router R1, enter the test response analyzer that the resource-network interface of R1 is embedded, carry out unpacking process, the XOR comparer of test response analyzer carries out xor operation to the desirable data that the test response data of resource node storer and data background device provide, judge that whether test response data is correct accordingly, and give BIST controller by result,
If V this test response data is correct, test response analyzer determines whether last test mode, if NO, then step IV is returned, the test graph builder transmission instruction that the resource-network interface of BIST controller to source router R1 is embedded, carries out data writing operation and the read data operation of next test mode by testing algorithm program;
If this test response data is correct, test response analyzer judges that this is last test mode, judge that whether this test is last SRAM address of storer to be measured again, if not last SRAM address, then return step IV, by the address ascending order of SRAM address generator or descending, the test of each test mode of testing algorithm requirement is carried out to next SRAM address; When judging this test last SRAM address as storer to be measured, terminating this test, the test result of this resource node storer fed back to BIST controller and sends to chip exterior testing apparatus to analyze; The switching working mode enable signal that simultaneously BIST controller sends to the SRAM controller of the BIST interface of router R2 is set to disarmed state, this resource node storer recovery normal mode of operation;
If this test response data mistake, be fault, test response analyzer stops the test to this resource node storer immediately, and test response analyzer sends test result to BIST controller, and test result is sent to external test facility by BIST controller.
3. the build-in self-test method of network-on-chip resource node storer according to claim 2, is characterized in that:
The test result that in described step V, test response analyzer sends BIST controller to comprises theoretical test data, test response data, address information, test duration.
4. the build-in self-test method of network-on-chip resource node storer according to claim 2, is characterized in that:
Testing algorithm described in described step III is the MarchC+ algorithm improved, and its read-write operation take word as test cell, and the multiple data bit in word are collectively referred to as data background; The resource node storer bit wide of described network-on-a-chip is N position, and sequence of test data has log
2n+1.
5. the build-in self-test method of network-on-chip resource node storer according to claim 4, is characterized in that:
Test mode number n in described BIST controller algorithm state machine is consistent with the number of March element in algorithm is M0 to Mn, algorithm original state in BIST controller is idle, after starting test, algorithm state first gets test mode M0, if the response data of resource node storer does not find fault under this test mode, transfer to next state M1 and test; By that analogy, when not finding fault in test process, M1, M2 is performed successively ... to the test mode of Mn, return original state afterwards and leave unused; When breaking down in test process, stop test immediately.
6. the build-in self-test method of network-on-chip resource node storer according to claim 2, is characterized in that:
Be divided into multiple packets of regular length in the message of network-on-chip transmission, each complete data is surrounded by 8 microplates, and each packet has a head microplate, 6 data microplates and a tail microplate; Head microplate comprises microplate type, Information sign, routing information, destination address and source data packet address, and tail microplate represents the termination of packet; Data microplate is the valid data transmitted, and is between a microplate and tail microplate; The front two of each microplate is microplate type information; The microplate of resource-network interface to the packet of process adds microplate type information.
7. the build-in self-test method of network-on-chip resource node storer according to claim 6, is characterized in that:
The transfer process of described packet in network-on-chip is as follows: first by resource node, packed data and relevant handshake are sent to local resource-network interface, this resource-network interface adds microplate type information according to data message to the microplate of packet, then application is sent to local router, local routing feeds back to local resource network interface answer signal after receiving request signal, make it by data stored in the data buffer of resource-network interface; Data are taken out according to the destination address information of carrying in head microplate by resource-network interface from data buffer, by the alteration switch of resource-network interface, exported to output port by destination party, enter into next router, the data so just completed from a router to next router are transmitted.
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