CN103295903A - Method for manufacturing fin type semiconductor device with wrap gate structure - Google Patents
Method for manufacturing fin type semiconductor device with wrap gate structure Download PDFInfo
- Publication number
- CN103295903A CN103295903A CN2012100558273A CN201210055827A CN103295903A CN 103295903 A CN103295903 A CN 103295903A CN 2012100558273 A CN2012100558273 A CN 2012100558273A CN 201210055827 A CN201210055827 A CN 201210055827A CN 103295903 A CN103295903 A CN 103295903A
- Authority
- CN
- China
- Prior art keywords
- fin
- mask layer
- perforation
- substrate
- insulating barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 33
- 230000004888 barrier function Effects 0.000 claims description 31
- 239000002070 nanowire Substances 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention discloses a method for manufacturing a fin type semiconductor device with a fence structure, which is characterized in that after a fin is formed on a body substrate (Bulk substrate), only a partial region of the lower part of the fin is exposed through multi-layer masks and etching, a through hole is etched in the lower part of the fin through the exposed region, an insulating layer is formed under the through hole, and the fence structure capable of surrounding the fin is further formed through the through hole, so that the fin type semiconductor device with the fence structure is manufactured on the body substrate, and the cost is reduced.
Description
Technical field
The present invention relates to semiconductor device processing technology, more particularly, relate to a kind of manufacture method of enclosing the fin formula semiconductor device of grid structure.
Background technology
Along with the height of semiconductor device is integrated, the MOSFET channel length constantly shortens, a series of in the long raceway groove model of MOSFET negligible effect become more remarkable, even become the leading factor that influences device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as cause degradation problem under threshold voltage of the grid decline, power consumption increase and the signal to noise ratio.
In order to control short-channel effect, some improvement have been taked in some aspect of conventional crystal tube device, for example, and on the one hand, the impurity elements such as more phosphorus, boron that mix in the raceway groove, carrier mobility descends in the device channel but this measure easily causes; On the other hand, strengthen the stress of raceway groove, but traditional SiGe PMOS strained silicon technology also begins to face bottleneck, being difficult to provides stronger strain for raceway groove again; Again on the one hand, the thickness of attenuate gate oxide medium, but the thickness aspect of gate oxide medium also the development bottleneck problem will occur, and the speed of gate oxide thicknesses attenuate has been difficult to catch up with the paces that grid width dwindles again, and the gate medium electric leakage is increasing.Along with the continuous shortening of channel dimensions, these improve all can not solve more significant short-channel effect.
At present, in order to solve the problem of short-channel effect, the three-dimensional device architecture of fin formula field effect transistor (Fin-FET) has been proposed, Fin-FET is the transistor with fin channel structure, it utilizes several surfaces of thin fin as raceway groove, thereby can prevent the short-channel effect in the conventional transistor, can increase operating current simultaneously.
(its grid structure surrounds the surface of fin for GAA, Fin-FET device Gate-All-Around), has taken full advantage of each surface of fin as channel region, has increased operating current most possibly, improves the performance of device for enclosing the grid structure.
Yet, the present Fin-FET that encloses the grid structure forms at SOI (Silicon On Insulator) substrate, the SOI substrate comprises at the bottom of top layer silicon, the backing and the oxygen buried layer between them, because the existence of oxygen buried layer, the Fin-FET that encloses the grid structure the manufacturing of SOI substrate is comparatively easy, but inevitably introduce big parasitic parameter, and the cost of SOI substrate itself is higher, has increased manufacturing cost.
Summary of the invention
The embodiment of the invention provides a kind of manufacture method of enclosing the fin formula semiconductor device of grid structure, has solved the problem of making this device at the body substrate, has reduced manufacturing cost.
For achieving the above object, the embodiment of the invention provides following technical scheme:
A kind of manufacture method of enclosing the fin formula field semiconductor device of grid structure comprises:
Substrate is provided, and described substrate is the body substrate;
The described substrate of etching forms fin in described substrate;
On the substrate of described fin both sides and the upper surface of fin form first mask layer, form second mask layer at described first mask layer, and form the 3rd mask layer at the sidewall of described fin;
Remove part second mask layer on the both sides substrate of described fin, to expose the partial sidewall of fin bottom;
Partial sidewall bottom the fin that exposes is carried out etching, forms perforation in the bottom of fin, and removes described first mask layer, second mask layer and the 3rd mask layer;
Form insulating barrier at the substrate of described fin both sides and the substrate under the perforation, the thickness of the insulating barrier under the described perforation is less than the height of perforation;
Form the gate dielectric layer that surrounds fin by described perforation, and form gate electrode at gate dielectric layer.
Alternatively, after removing first mask layer, second mask layer and the 3rd mask layer, form before the gate dielectric layer, also comprise step: form nano wire in the fin in described perforation.
Alternatively, the step that forms described nano wire and insulating barrier comprises:
The substrate of filling described perforation and covering described fin both sides is to form insulating barrier;
Insulating barrier in upper surface, sidewall and the both sides of the fin at described perforation two ends forms the 4th mask layer;
Carry out oxidation technology, divide oxidation with the fin on the described perforation, and remove the oxidized part of the fin on the perforation, remaining fin is nano wire on the perforation;
Remove the partial insulative layer in the described perforation, so that the thickness of the insulating barrier under the described perforation is less than the height of perforation;
Remove the 4th mask layer;
The step that forms gate dielectric layer is: form the gate dielectric layer that surrounds nano wire by described perforation.
Alternatively, described insulating barrier is silicon dioxide, and described the 4th mask layer is silicon nitride.
Alternatively, described second mask layer has selective etching with respect to first mask layer and the 3rd mask layer.
Alternatively, described first mask layer and the 3rd mask layer are silicon dioxide, and described second mask layer is silicon nitride.
Alternatively, the step that forms first mask layer and second mask layer comprises:
Silicon oxide deposition, and carry out isotropic etching, with on the substrate of described fin both sides and the upper surface of fin form first mask layer of silica;
Deposit silicon nitride, and carry out isotropic etching, to form second mask layer of silicon nitride at described first mask layer.
Alternatively, after forming gate electrode, also comprise step: in the fin of described gate electrode both sides, form source-drain area.
Compared with prior art, technique scheme has the following advantages:
The manufacture method of the fin formula semiconductor device that encloses the grid structure of the embodiment of the invention, after utilizing body substrate (Bulk substrate) to form fin, only expose the subregion of the bottom of fin by layered mask and etching, by this area exposed the bottom of fin being etched perforation comes, and under perforation, form insulating barrier, by perforation, what thereby further formation can be surrounded fin encloses grid structure (gate dielectric layer and gate electrode), insulating barrier under the perforation has realized enclosing the grid structure with the isolation of substrate, enclose the fin formula semiconductor device of grid structure thereby realized making on the body substrate, reduced manufacturing cost.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the flow chart of the manufacture method of the fin formula semiconductor device that encloses the grid structure of the present invention;
Fig. 2-Figure 14 is the perspective view according to each manufacture process of the fin formula semiconductor device that encloses the grid structure of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Described as background technology, traditional fin formula process for fabrication of semiconductor device that encloses the grid structure utilizes the SOI substrate to carry out, and the cost height of SOI substrate has increased manufacturing cost.
Based on this, the present invention proposes a kind of manufacture method of enclosing the fin formula semiconductor device of grid structure, after utilizing body substrate (Bulk substrate) to form fin, only expose the subregion of the bottom of fin by layered mask and etching, by this area exposed the bottom of fin being etched perforation comes, by perforation, thus further formation can surround fin enclose grid structure (gate dielectric layer and gate electrode).The manufacture method that this encloses the fin formula semiconductor device of grid structure comprises:
Substrate is provided, and described substrate is the body substrate;
The described substrate of etching forms fin in described substrate;
On the substrate of described fin both sides and the upper surface of fin form first mask layer, form second mask layer at described first mask layer, and form the 3rd mask layer at the sidewall of described fin;
Remove part second mask layer on the both sides substrate of described fin, to expose the partial sidewall of fin bottom;
Partial sidewall bottom the fin that exposes is carried out etching, forms perforation in the bottom of fin, and removes described first mask layer, second mask layer and the 3rd mask layer;
Form insulating barrier at the substrate of described fin both sides and the substrate under the perforation, the thickness of the insulating barrier under the described perforation is less than the height of perforation;
Form the gate dielectric layer that surrounds fin by described perforation, and form gate electrode at gate dielectric layer.
Said method can also be for the manufacture of the FINFET that encloses the grid structure of nano wire, can be after forming perforation and removing first, second, and third mask layer, after fin in the perforation got rid of a part, form nano wire, and then form gate dielectric layer and the gate electrode that surrounds this nano wire.
More than be manufacture method of enclosing the fin formula semiconductor device of grid structure of the present invention, the solution of enclosing the fin formula semiconductor device of grid structure the manufacturing of body substrate is provided, reduced manufacturing cost.
For a better understanding of the present invention, the structural representation below with reference to manufacturing process of the present invention and manufacture process is described in detail embodiments of the invention.
As shown in Figure 1, Fig. 1 is the flow chart of the manufacture method of the fin formula semiconductor device that encloses the grid structure of the present invention.
At step S01, substrate 200 is provided, described substrate is the body substrate, as shown in Figure 2.
In the present embodiment, described substrate 200 can comprise the body silicon substrate (for example wafer) that is arranged in crystal structure.In other embodiments, can also comprise other elemental semiconductors or compound semiconductor, for example Ge, GeSi, GaAs, InP, SiC or diamond etc.According to the known designing requirement of prior art (for example p-type substrate or n type substrate), substrate 200 can comprise various doping configurations.In addition, substrate 200 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.
At step S02, the described substrate 200 of etching forms fin 202, with reference to shown in Figure 3 in described substrate 200.
In the present embodiment, can be by the hard mask of deposit (scheming not shown) on substrate 200, for example silicon dioxide and upward silicon nitride, the hard mask of patterning then, then can utilize lithographic technique, for example the method for RIE etches away certain thickness substrate, thereby forms fin 202 in this body substrate 200.
At step S03, forming first mask layer 204 and second mask layer 206 on the substrate 200 of described fin 202 both sides and on the upper surface of fin 202 successively, and forming the 3rd mask layer 208 at the sidewall of described fin 202, as shown in Figure 5.
In the present invention, described second mask layer 206 has selective etching with respect to first mask layer 204 and the 3rd mask layer 208, like this, in subsequent technique, can expose the partial sidewall of the bottom of fin by patterning second mask layer 206, and then form perforation, and be not damaged to other parts of fin.
In the present embodiment, described first mask layer 204 and the 3rd mask layer 208 can be silicon dioxide, and described second mask layer 206 can be silicon nitride, and thickness can be roughly the height of the perforation that will form, and particularly, can realize by following steps:
At first, can adopt for example method silicon oxide deposition of PECVD, LTO etc., thereby, form thicker silica on the surface of Semiconductor substrate and the top of fin, and form thinner silica along the sidewall direction of fin, then carry out isotropic etching, the method of RIE for example, remove the silica on the sidewall of fin, thus on the substrate of described fin both sides and the upper surface of fin form first mask layer 204 of silica, with reference to shown in Figure 4.
Then, method with above-mentioned formation first mask layer, can deposit silicon nitride, the method of PECVD for example, the top that is formed on the surface of Semiconductor substrate and fin forms thicker and forms thinner silicon nitride along the sidewall direction of fin, then carries out isotropic etching, for example the method for RIE, thereby at second mask layer 206 of described first mask layer formation silicon nitride, with reference to shown in Figure 4.
Then, can adopt dry etch process that this silicon dioxide is anti-carved, thereby form the 3rd mask layer at the sidewall of fin 202 by behind deposit silicon dioxide on the above-mentioned device, with the sidewall of protection fin, with reference to shown in Figure 5.
At step S04, remove part second mask layer 206 on the both sides substrate 200 of described fin 202, to expose the partial sidewall 210 of fin bottom, with reference to shown in Figure 6.
Can only expose the partial sidewall of described fin 202 1 side bottoms, also can expose the partial sidewall of 202 liang of side bottoms of described fin, the side walls that exposes can be symmetrically distributed.
In the present embodiment, can pass through described second mask layer 206 of patterning, remove second mask layer 206 of the part of fin both sides symmetrically, like this, the part that the bottom of fin and second mask layer join is exposed, and sidewall 210 parts that exposed at both sides goes out are symmetrically distributed in the fin both sides, like this, in subsequent etching technology, in order to form the perforation of bottom.
At step S05, carry out etching from the sidewall 210 of the fin that exposes, form perforation 212 in the bottom of fin 202, and remove described first mask layer 204, second mask layer 206 and the 3rd mask layer 208, with reference to shown in Figure 7.
In the present embodiment, can adopt wet etching, TMAH solution for example, under the sheltering of described first mask layer 204, second mask layer 206 and the 3rd mask layer 208, carry out etching from the bottom of 210 pairs of fins of sidewall of the fin that exposes, form perforation 212, then further described first mask layer 204, second mask layer 206 and the 3rd mask layer 208 are all removed, thereby formed bridge architecture, as shown in Figure 7, the fin at described perforation two ends can also be further used for forming the source-drain area of device for supporting, and forms by this perforation 212 and encloses the grid structure.
At step S06, form insulating barrier 214 at the substrate of described fin both sides and the substrate under the perforation, the thickness of the insulating barrier 214 under the described perforation 212 is less than the height of perforation 212, with reference to shown in Figure 8.
In the present embodiment, can form this insulating barrier 214, for example SiO less than perforation 212 insulating material highly by deposition thickness
2As shown in Figure 8, described insulating barrier 212 does not all fill up perforation, and subsequent technique can pass perforation formation and enclose the grid structure, and the grid structure of enclosing that described insulating barrier 212 will form is opened with following substrate isolation.
At step S07, form the gate dielectric layer that surrounds fin by described perforation, and form gate electrode 212 at gate dielectric layer, as shown in Figure 9.
Described gate dielectric layer can be silica, silicon oxynitride or high K medium material etc., and the high K medium material is the hafnium base oxide for example, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc.
Described gate electrode 212 can be one or more layers structure, and gate electrode can comprise metal gate electrode or polysilicon etc., for example can comprise: Ti, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
x, Ru, TaN
x, TiAlN, WCN, MoAlN, RuO
x, polysilicon or other suitable materials, or their combination.
In the present embodiment, can be by behind deposit high K medium material successively and the metal gate electrode, carry out patterning form surround described fin enclose the grid structure, thereby make each surface of fin increase the operating current of device as raceway groove.
So far, formed the fin formula semiconductor device that encloses the grid structure of the embodiment of the invention, then, can finish subsequent machining technology as required, for example form source-drain area, in the present invention, can in the fin at perforation two ends, just enclose in the fin of both sides of grid structure, form source-drain area, and can further form isolation structure between device and contact plug etc.
More than embodiments of the invention are described in detail, in preferred embodiment, after above-described embodiment forms bridge architecture, after namely forming perforation and removing first, second, and third mask layer, can form nano wire, then form at nano wire and enclose the grid structure.
In the preferred embodiment, the step that forms perforation and remove first, second, and third mask layer with above-mentioned embodiment in the step of S01-S05 identical, do not repeat them here, step afterwards can comprise following concrete steps:
At step S051, the substrate 200 of filling described perforation 212 and covering described fin 202 both sides is to form insulating barrier 214, as shown in figure 10.
In the present embodiment, can form this insulating barrier 214 by deposit TEOS.
At step S052, the insulating barrier 214 in upper surface, sidewall and the both sides of the fin at described perforation 212 two ends forms the 4th mask layer 216, as shown in figure 11.
In the present embodiment, can pass through deposit silicon nitride, then carry out patterning, form the 4th mask layer 216, described the 4th mask layer is all covered the fin at through hole two ends, only exposes the part of the fin on the through hole.
At step S053, carry out oxidation technology, divide oxidation with the fin on the described perforation, and remove the oxidized part of the fin on the perforation, remaining fin is nano wire on the perforation, with reference to shown in Figure 12.
In the present embodiment, particularly, at first, carry out oxidation technology, owing to the fin on the through hole comes out, and other parts are covered, have only the fin meeting on the through hole oxidized, by the condition of control oxidation technology, the only fin of this part of partial oxidation, then, by etching technics, wet etching for example, the part that this is oxidized is removed, only be left not oxidized fin branch, remaining fin is nano wire on the perforation, and the diameter of remaining fin can be less than 10nm on the described perforation.Then, remove the 4th mask layer.
At step S61, remove the partial insulative layer 214 in the described perforation 212, so that the thickness of the insulating barrier 214 under the described perforation 212 is less than the height of perforation, with reference to shown in Figure 12.
In the present embodiment, can be still with the 4th mask layer for sheltering, further etching is removed perforation certain thickness insulating barrier 214 down, makes the thickness of the insulating barrier 214 under the described perforation 212 less than the height of boring a hole, perforation is used to form when enclosing grid, and the bottom also has insulating barrier.
More preferably, after removing partial insulative layer, can also carry out H
2Thermal annealing under the environment is to repair the surface of nano wire.
Then, remove the 4th mask layer, as shown in figure 12.
So far, the nano wire of present embodiment and the insulating barrier under the nano wire have been formed.
Then, form the gate dielectric layer that surrounds nano wire by the perforation under the nano wire, and the gate electrode on the gate dielectric layer, the grid structure enclosed thereby form.This step is not being given unnecessary details at this with the step S07 of aforementioned embodiment.
Then, can finish subsequent machining technology as required, for example form source-drain area, in the present invention, can be in the fin at perforation two ends, just enclose in the fin of both sides of grid structure, form source-drain area, and can further form isolation structure between device and contact plug etc.
Though the present invention discloses as above with preferred embodiment, yet is not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a manufacture method of enclosing the semiconductor device of grid structure is characterized in that, comprising:
Substrate is provided, and described substrate is the body substrate;
The described substrate of etching forms fin in described substrate;
On the substrate of described fin both sides and the upper surface of fin form first mask layer, form second mask layer at described first mask layer, and form the 3rd mask layer at the sidewall of described fin;
Remove part second mask layer on the both sides substrate of described fin, to expose the partial sidewall of fin bottom;
Partial sidewall bottom the fin that exposes is carried out etching, forms perforation in the bottom of fin, and removes described first mask layer, second mask layer and the 3rd mask layer;
Form insulating barrier at the substrate of described fin both sides and the substrate under the perforation, the thickness of the insulating barrier under the described perforation is less than the height of perforation;
Form the gate dielectric layer that surrounds fin by described perforation, and form gate electrode at gate dielectric layer.
2. manufacture method according to claim 1 is characterized in that, after removing first mask layer, second mask layer and the 3rd mask layer, form before the gate dielectric layer, also comprises step: form nano wire in the fin in described perforation.
3. manufacture method according to claim 2 is characterized in that, the step that forms described nano wire and insulating barrier comprises:
The substrate of filling described perforation and covering described fin both sides is to form insulating barrier;
Insulating barrier in upper surface, sidewall and the both sides of the fin at described perforation two ends forms the 4th mask layer;
Carry out oxidation technology, divide oxidation with the fin on the described perforation, and remove the oxidized part of the fin on the perforation, remaining fin is nano wire on the perforation;
Remove the partial insulative layer in the described perforation, so that the thickness of the insulating barrier under the described perforation is less than the height of perforation;
Remove the 4th mask layer;
The step that forms gate dielectric layer is: form the gate dielectric layer that surrounds nano wire by described perforation.
4. manufacture method according to claim 3 is characterized in that, described insulating barrier is silicon dioxide, and described the 4th mask layer is silicon nitride.
5. according to each described manufacture method among the claim 1-4, it is characterized in that described second mask layer has selective etching with respect to first mask layer and the 3rd mask layer.
6. manufacture method according to claim 5 is characterized in that, described first mask layer and the 3rd mask layer are silicon dioxide, and described second mask layer is silicon nitride.
7. manufacture method according to claim 6 is characterized in that, the step that forms first mask layer and second mask layer comprises:
Silicon oxide deposition, and carry out isotropic etching, with on the substrate of described fin both sides and the upper surface of fin form first mask layer of silica;
Deposit silicon nitride is also carried out isotropic etching, to form second mask layer of silicon nitride at described first mask layer.
8. according to each described manufacture method among the claim 1-4, after forming gate electrode, also comprise step:
In the fin of described gate electrode both sides, form source-drain area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210055827.3A CN103295903B (en) | 2012-03-05 | 2012-03-05 | Method for manufacturing fin type semiconductor device with wrap gate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210055827.3A CN103295903B (en) | 2012-03-05 | 2012-03-05 | Method for manufacturing fin type semiconductor device with wrap gate structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103295903A true CN103295903A (en) | 2013-09-11 |
| CN103295903B CN103295903B (en) | 2016-06-15 |
Family
ID=49096579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210055827.3A Active CN103295903B (en) | 2012-03-05 | 2012-03-05 | Method for manufacturing fin type semiconductor device with wrap gate structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103295903B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795326A (en) * | 2014-01-16 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon nanowire structure |
| CN108470685A (en) * | 2018-03-30 | 2018-08-31 | 中国科学院微电子研究所 | Nanowire structure and manufacturing method thereof |
| CN110838444A (en) * | 2018-08-17 | 2020-02-25 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050176186A1 (en) * | 2004-02-10 | 2005-08-11 | Lee Choong-Ho | Field effect transistor and method for manufacturing the same |
| CN101017820A (en) * | 2006-02-07 | 2007-08-15 | 三星电子株式会社 | Semiconductor device having gate-all-around structure and method of fabricating the same |
| KR20090042590A (en) * | 2007-10-26 | 2009-04-30 | 삼성전자주식회사 | Nanowire transistor and manufacturing method of the same |
| US20110081764A1 (en) * | 2009-10-07 | 2011-04-07 | Globalfoundries Inc. | Methods for forming isolated fin structures on bulk semiconductor material |
| CN102301480A (en) * | 2009-02-17 | 2011-12-28 | 国际商业机器公司 | Nanowire Mesh Device And Method Of Fabricating Same |
-
2012
- 2012-03-05 CN CN201210055827.3A patent/CN103295903B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050176186A1 (en) * | 2004-02-10 | 2005-08-11 | Lee Choong-Ho | Field effect transistor and method for manufacturing the same |
| CN101017820A (en) * | 2006-02-07 | 2007-08-15 | 三星电子株式会社 | Semiconductor device having gate-all-around structure and method of fabricating the same |
| KR20090042590A (en) * | 2007-10-26 | 2009-04-30 | 삼성전자주식회사 | Nanowire transistor and manufacturing method of the same |
| CN102301480A (en) * | 2009-02-17 | 2011-12-28 | 国际商业机器公司 | Nanowire Mesh Device And Method Of Fabricating Same |
| US20110081764A1 (en) * | 2009-10-07 | 2011-04-07 | Globalfoundries Inc. | Methods for forming isolated fin structures on bulk semiconductor material |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795326A (en) * | 2014-01-16 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon nanowire structure |
| CN108470685A (en) * | 2018-03-30 | 2018-08-31 | 中国科学院微电子研究所 | Nanowire structure and manufacturing method thereof |
| CN108470685B (en) * | 2018-03-30 | 2022-02-01 | 中国科学院微电子研究所 | Nanowire structure and manufacturing method thereof |
| CN110838444A (en) * | 2018-08-17 | 2020-02-25 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN110838444B (en) * | 2018-08-17 | 2024-01-30 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| US11894446B2 (en) | 2018-08-17 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103295903B (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10319863B2 (en) | Semiconductor device having a varying thickness nanowire channel and method for fabricating the same | |
| KR101729439B1 (en) | Finfet with buried insulator layer and method for forming | |
| US9257545B2 (en) | Stacked nanowire device with variable number of nanowire channels | |
| US10896956B2 (en) | Field effect transistor with reduced contact resistance | |
| US9153657B2 (en) | Semiconductor devices comprising a fin | |
| US9929270B2 (en) | Gate all-around FinFET device and a method of manufacturing same | |
| KR20180123422A (en) | Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same | |
| US9224849B2 (en) | Transistors with wrapped-around gates and methods for forming the same | |
| CN102810476B (en) | Method for manufacturing fin field effect transistor | |
| CN107527801A (en) | Semiconductor devices and forming method thereof | |
| US10600795B2 (en) | Integration of floating gate memory and logic device in replacement gate flow | |
| US11038039B2 (en) | Method of forming a semiconductor device | |
| CN104282540A (en) | Transistor and method for forming transistor | |
| CN103295903B (en) | Method for manufacturing fin type semiconductor device with wrap gate structure | |
| CN103839819A (en) | Semiconductor device and method for manufacturing the same | |
| CN105633152B (en) | Semiconductor structure and manufacturing method thereof | |
| CN104217948B (en) | Semiconductor manufacturing method | |
| CN102931085A (en) | Semiconductor device and method for manufacturing the same | |
| KR20240038102A (en) | Method of forming bottom dielectric isolation layers | |
| CN106558489B (en) | Nanowire structure, fence nanowire device and manufacturing method thereof | |
| CN103094217B (en) | Transistor Manufacturing Method | |
| CN106558603B (en) | Nanowire structure, fence nanowire device and manufacturing method thereof | |
| CN110875390B (en) | Semiconductor structure and forming method thereof | |
| CN115719706A (en) | Stacked nanosheet GAA-FET device and manufacturing method thereof | |
| CN115995490A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |