CN103281270A - Forecast decision feedback equalizer - Google Patents
Forecast decision feedback equalizer Download PDFInfo
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- CN103281270A CN103281270A CN201310201939XA CN201310201939A CN103281270A CN 103281270 A CN103281270 A CN 103281270A CN 201310201939X A CN201310201939X A CN 201310201939XA CN 201310201939 A CN201310201939 A CN 201310201939A CN 103281270 A CN103281270 A CN 103281270A
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Abstract
The invention discloses a forecast decision feedback equalizer, comprising a decision feedback equalizing system which comprises a selector, a D flip-flop and two adjustable-threshold-value samplers, wherein N decision feedback equalizing systems are arranged; N is an positive integer larger than or equal to 2; in two adjacent decision feedback equalizing systems, the output end of the D flip-flop of the previous decision feedback equalizer is connected with the control end of the selector of the next decision feedback equalizer; the output end of the D flip-flop of the last decision feedback equalizer is connected with the control end of the selector of the most front decision feedback equalizer; the frequency of a control clock of each decision feedback equalizer is an external input analog signal frequency; and difference exists in the phase positions of the control clocks of the decision feedback equalizers. On the basis of not changing the forecast decision feedback equalizer algorithm, the forecast decision feedback equalizer makes the external input analog signal be correctly selected and obtain a correct equilibrium result through controlling the frequencies of the control clocks.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of leading DFF.
Background technology
In mobile communication, the finiteness of multipath effect and channel width and the imperfection of the characteristic of channel inevitably produce intersymbol interference when causing transfer of data, become the principal element that influences communication quality; And the balancing technique of channel can be eliminated intersymbol interference and noise, and reduces the error rate.Wherein DFF (DFE) is a kind of very effective and widely used measure that is used for eliminating or reducing the multipath interference.
Fig. 1 is the structural representation of leading DFF of the prior art.As shown in Figure 1, existing leading DFF comprises selector S, d type flip flop D1 and two adjustable threshold samplers; Two adjustable threshold samplers are respectively positive threshold value sampler D2 and negative threshold value sampler D3; The analog signal ADATA of outside input inputs to positive threshold value sampler D2 and negative threshold value sampler D3 respectively, and positive threshold value sampler D2, the clock control end of negative threshold value sampler D3 and d type flip flop D1 is connected with external clock respectively, clk is to positive threshold value sampler D2 for external clock output clock pulse, the clock control end of negative threshold value sampler D3 and d type flip flop D1, and the frequency of clock pulse clk is identical with the analog signal ADATA of outside input, thereby when the rising edge of clock pulse clk arrives, positive threshold value sampler D2 and the external analog signal ADATA of negative threshold value sampler D3 sample, and signal DATA0 and ADTA1 after output is sampled respectively; Positive threshold value sampler D1 is connected with two inputs of selector S respectively with the output of negative threshold value sampler D2, the output of selector S is connected with the input of d type flip flop D3, thereby selector S selects also output signal DATA to signal DATA0 and the ADTA1 of input, and signal DATA is by the stable analog signal Dout of output behind the d type flip flop D3; In addition, the output of d type flip flop D3 is connected with the control end of selector S, thereby the signal Dout that previous judgement obtains is in order to control selector S to the selection of next signal.
From above-mentioned leading DFF shown in Figure 1, before obtaining previous judgement, with positive threshold value sampler D2 and negative threshold value sampler D3 input analog signal ADATA is sampled, it is 1 that positive threshold value sampler D2 just adjudicates on the occasion of output greater than certain at the input analog signal level of sampler, and it is 0 that negative threshold value sampler D3 just adjudicates less than certain negative value output at the input analog signal level of sampler; And the threshold value of positive threshold value sampler D2 and negative threshold value sampler D3 can be regulated, thereby positive threshold value sampler D2 or negative threshold value sampler D3 can be finished importing the sampling of analog signal ADATA.According to the previous judgement that recovers (being the signal of d type flip flop D3 output), selector S will select correct court verdict in DATA0 and ADTA1, abandon the result of another one mistake, and output signal DATA; And by the stable analog signal Dout of d type flip flop D3 output, and the analog signal Dout of output controls the selection of next analog signal again by selector S.
Fig. 2 is the sequential chart of leading first feedback loop of DFF shown in Figure 1.Owing to precompute by leading DFF at previous analog signal, so selector S only need select correct result with previous analog signal and gets final product.As seen from Figure 2, owing to need to utilize the signal Dout that has recovered to select, adjudicate different analog signal DATA0, the DATA1 of two threshold value sampler outputs; Because the frequency of clock pulse clk is identical with the analog signal ADATA of outside input, therefore, Dout must be stabilized to its end value before next rising edge clock arrives, i.e. the total delay of first feedback path must be satisfied formula (1), correct equilibrium result could be chosen.
T
mux+T
cq＜1UI?（1）
Wherein:
T
Mux---the delay of MUX;
T
Cq---the transmission delay of d type flip flop.
But when carrying out high speed data transfer in communication, (1) formula is difficult to set up; When being 10G such as the frequency of analog signal ADATA of input, UI=100ps postpones about Tmux=75ps, about d type flip flop data setup time Tcq=90ps at selector under the current the fastest main flow technology that can reach.75ps+90ps〉100ps, so said structure will be difficult to select correct equilibrium result.
Therefore, be necessary to provide a kind of improved leading DFF to overcome above-mentioned defective.
Summary of the invention
The purpose of this invention is to provide a kind of leading DFF, leading DFF of the present invention need not change on the basis of leading DFF algorithm, by using frequency reducing multi-phase clock over-sampling to realize the algorithm of leading DFF, make the analog signal of outside input can correctly be selected and obtain correct equilibrium result.
For achieving the above object, the invention provides a kind of leading DFF, described leading DFF, comprise the decision feedback equalization system, described decision feedback equalization system comprises selector, d type flip flop and two adjustable threshold samplers, two adjustable threshold samplers are respectively positive threshold value sampler and negative threshold value sampler, the analog signal of outside input inputs to described positive threshold value sampler and negative threshold value sampler respectively, and described positive threshold value sampler is connected with the control clock respectively with the clock control end of negative threshold value sampler, described positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of described selector is connected with the input of described d type flip flop, the clock control end of described d type flip flop is connected with the control clock, and the output of described d type flip flop is connected with the control end of described selector, wherein, described decision feedback equalization system is the N cover, and N is the positive integer more than or equal to 2, the adjacent described decision feedback equalization of two covers system, the output of the d type flip flop of last cover decision feedback equalization system is connected with the control end of the selector of back one cover decision feedback equalization system, the output of the d type flip flop of last cover decision feedback equalization system is connected with the control end of the selector of the most last cover decision feedback equalization system, and the frequency of the control clock of every cover decision feedback equalization system is that frequency analog signal is imported in the outside
And the phase place of the control clock of every cover decision feedback equalization system is all variant.
Preferably, the phase phasic difference of the control clock of every adjacent two cover decision feedback equalization systems
The phase phasic difference of the phase place of the control clock of last cover decision feedback equalization system and the control clock of the most last cover decision feedback equalization system
T is the cycle of control clock.
Compared with prior art, leading DFF of the present invention is because described decision feedback equalization system is the N cover, and N be the positive integer more than or equal to 2, and the frequency of the control clock of every cover decision feedback equalization system be that frequency analog signal is imported in the outside
Make leading DFF of the present invention in the analog signal sampling processing procedure to input, only need the transmission delay of each selector and d type flip flop to satisfy Tmux+Tcq＜N*UI and can select correct equilibrium result, and the transmission delay that will make each selector and d type flip flop satisfies following formula, and the tricks N of the described decision feedback equalization of relative set system can realize; Therefore leading DFF of the present invention is easy to realize, and can guarantee to select to obtain correct equilibrium result.
By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining the present invention.
Description of drawings
Fig. 1 is the structural representation of leading DFF of the prior art.
Fig. 2 is the sequential chart of leading first feedback loop of DFF shown in Figure 1.
Fig. 3 is the structural representation of an embodiment of the leading DFF of the present invention.
Fig. 4 is the sequential chart of leading first feedback loop of DFF shown in Figure 3.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, the similar elements label represents similar elements in the accompanying drawing.As mentioned above, the invention provides a kind of leading DFF, leading DFF of the present invention need not change on the basis of leading DFF algorithm, by using frequency reducing multi-phase clock over-sampling to realize the algorithm of leading DFF, make the analog signal of outside input can correctly be selected and obtain correct equilibrium result.
Please refer to Fig. 3, Fig. 3 is the structural representation of an embodiment of the leading DFF of the present invention.As shown in the figure, leading DFF of the present invention comprises N cover decision feedback equalization system, and N is the positive integer more than or equal to 2.Wherein, every suit decision feedback equalization system includes selector (being respectively S2, S4, S6, S8), d type flip flop (being respectively D12, D14, D16, D18) and two adjustable threshold samplers, and two adjustable threshold samplers are respectively positive threshold value sampler (being respectively D22, D24, D26, D28) and negative threshold value sampler (being respectively D32, D34, D36, D38); The analog signal ADATA of outside input inputs to each positive threshold value sampler (being respectively D22, D24, D26, D28) and negative threshold value sampler (being respectively D32, D34, D36, D38) respectively, and the clock control end of positive threshold value sampler, negative threshold value sampler and d type flip flop is connected with corresponding control clock respectively, and each control clock output clock pulse (being respectively clk2, clk4, clk6, clk8) is to the clock control end of corresponding positive threshold value sampler, negative threshold value sampler and d type flip flop; And the frequency of each clock pulse clk2, clk4, clk6, clk8 is the outside analog signal ADATA frequency of importing
Thereby when the rising edge of each clock pulse clk2, clk4, clk6, clk8 arrives, corresponding positive threshold value sampler and negative threshold value sampler are sampled to external analog signal ADATA, and signal vthp2, vthn2 after output is sampled respectively, vthp4, vthn4, vthp6, vthn6, vthp8, vthn8; Positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of selector is connected with the input of d type flip flop, thereby selector is to signal vthp2, the vthn2 of input, vthp4, vthn4, vthp6, vthn6, vthp8, vthn8 select also output signal OUT2, OUT4, OUT6, OUT8, and the signal of described selector output is by the stable analog signal (being respectively Dout2, Dout4, Dout6, Dout8) of d type flip flop output.
Particularly, in one embodiment of the present of invention shown in Figure 3, N is 4, that is to say to comprise 4 cover decision feedback equalization systems in the leading DFF of this embodiment, and apparently, in the specific embodiment of the present invention, the N value is not limited to 4.In this embodiment, 4 cover decision feedback equalization systems are respectively the first cover decision feedback equalization D2 of system, the second cover decision feedback equalization D4 of system, the 3rd cover decision feedback equalization D6 of system and the quadruplet decision feedback equalization D8 of system; And the frequency of clock pulse clk2, clk4, clk6, clk8 of respectively overlapping decision feedback equalization system correspondence is for the analog signal ADATA frequency of outside input
Wherein, the positive threshold value sampler D22 of the first cover decision feedback equalization D2 of system is connected with the input of selector S2 respectively with the output of negative threshold value sampler D32, and the output of selector S2 is connected with the input of d type flip flop D12; Annexation between above-mentioned each device, all identical in the D4 of decision feedback equalization system, D6 and D8, no longer be repeated in this description at this.In addition, in DFF of the present invention, the adjacent described decision feedback equalization of two covers system, the output of the d type flip flop of last cover decision feedback equalization system is connected with the control end of the selector of back one cover decision feedback equalization system, and last output that overlaps the d type flip flop of decision feedback equalization system is connected with the control end of the selector of the most last cover decision feedback equalization system; Particularly, the output of the d type flip flop D12 of the first cover decision feedback equalization D2 of system is connected with the control end of the selector S4 of the second cover decision feedback equalization D4 of system, and the output of the d type flip flop D14 of the second cover decision feedback equalization D4 of system is connected with the control end of the selector S6 of the 3rd cover decision feedback equalization D6 of system; Accordingly, the follow-up output that other respectively overlaps the d type flip flop of decision feedback equalization system is connected with the selector of next cover decision feedback equalization system, and to the last the output of the d type flip flop D18 of the quadruplet decision feedback equalization D8 of system is connected with the control end of the selector S2 of the first cover decision feedback equalization D2 of system; Thereby the selection operation of the selector of next cover decision feedback equalization system of the signal controlling of the d type flip flop of last cover decision feedback equalization system output, and the selection operation of the selector of the most last cover decision feedback equalization of the signal controlling system (being D2) of d type flip flop of last cover decision feedback equalization system (being D8) output.
Please again in conjunction with reference to figure 4, describe the course of work of the first cover decision feedback equalization D2 of system, wherein omitted the feedback sequential of the second cover decision feedback equalization D4 of system and the 3rd cover decision feedback equalization D6 of system among Fig. 4; Clk_send is the tranmitting data register of high-speed serial data among the figure, and external analog signal ADATA sends when the rising edge of this clock.When the rising edge of clock pulse clk2 arrives, positive threshold value sampler D22 and negative threshold value sampler D32 are to input analog signal ADATA sampling, it is 1 that positive threshold value sampler D22 just adjudicates on the occasion of output greater than certain at the input analog signal level of sampler, and it is 0 that negative threshold value sampler D32 just adjudicates less than certain negative value output at the input analog signal level of sampler; Selector S2 is according to the court verdict (i.e. the signal of the d type flip flop D8 of quadruplet decision feedback equalization system output) of the previous round that recovers, selector S will select correct court verdict in its input signal vthp2 and vthn2, abandon the result of another one mistake, and by the stable analog signal Dout2 of d type flip flop D2 output, and the analog signal Dout2 of output controls the selection of next analog signal again by selector S4.Correspondingly, because phase phasic difference of respectively overlapping the control clock of decision feedback equalization system of the present invention
The phase phasic difference of the phase place of the control clock of last cover decision feedback equalization system and the control clock of the most last cover decision feedback equalization system
T is the cycle of control clock, and the time that the feasible rising edge of respectively controlling the clock pulse of clock arrives also all differs
Be in the present embodiment
Similarly carry out aforesaid operations when its rising edge of controlling the clock pulse of clock arrives respectively, to the last a cover decision feedback equalization system also executes aforesaid operations, and namely leading DFF of the present invention is finished one and taken turns feedback procedure.
From the above, whole leading DFF will realize selecting correct equilibrium result, only need the transmission delay of each selector and d type flip flop to satisfy Tmux+Tcq＜N*UI, thereby need not change leading DFF algorithm the basis on, the tricks that the N of decision feedback equalization system is set by adjusting can make following formula be easy to realize, thereby make leading DFF of the present invention correctly select correct equilibrium result, and whole leading DFF is easy to realize.
Above invention has been described in conjunction with most preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain various modification, equivalent combinations of carrying out according to essence of the present invention.
Claims (2)
1. leading DFF, comprise the decision feedback equalization system, described decision feedback equalization system comprises selector, d type flip flop and two adjustable threshold samplers, two adjustable threshold samplers are respectively positive threshold value sampler and negative threshold value sampler, the analog signal of outside input inputs to described positive threshold value sampler and negative threshold value sampler respectively, and described positive threshold value sampler is connected with the control clock respectively with the clock control end of negative threshold value sampler, described positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of described selector is connected with the input of described d type flip flop, the clock control end of described d type flip flop is connected with the control clock, and the output of described d type flip flop is connected with the control end of described selector, it is characterized in that, described decision feedback equalization system is the N cover, and N is the positive integer more than or equal to 2, the adjacent described decision feedback equalization of two covers system, the output of the d type flip flop of last cover decision feedback equalization system is connected with the control end of the selector of back one cover decision feedback equalization system, the output of the d type flip flop of last cover decision feedback equalization system is connected with the control end of the selector of the most last cover decision feedback equalization system, and the frequency of the control clock of every cover decision feedback equalization system is that frequency analog signal is imported in the outside
And the phase place of the control clock of every cover decision feedback equalization system is all variant.
2. leading DFF as claimed in claim 1 is characterized in that, the phase phasic difference of the control clock of every adjacent two cover decision feedback equalization systems
The phase phasic difference of the phase place of the control clock of last cover decision feedback equalization system and the control clock of the most last cover decision feedback equalization system
T is the cycle of control clock.
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| CN112422461A (en) * | 2020-11-05 | 2021-02-26 | 硅谷数模(苏州)半导体有限公司 | Decision feedback equalizer and data acquisition and correction method |
| CN113114229A (en) * | 2020-01-13 | 2021-07-13 | 达尔科技股份有限公司 | Combined decision feedback equalizer and phase detector for clock data recovery |
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