CN103281076B - A kind of method of clock source and signal transacting thereof - Google Patents
A kind of method of clock source and signal transacting thereof Download PDFInfo
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- CN103281076B CN103281076B CN201310203139.1A CN201310203139A CN103281076B CN 103281076 B CN103281076 B CN 103281076B CN 201310203139 A CN201310203139 A CN 201310203139A CN 103281076 B CN103281076 B CN 103281076B
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Abstract
The embodiment of the invention discloses a kind of method of clock source and signal transacting thereof, relate to electronic information field, solve the problem that such product design is complicated, the production cycle is long.This clock source comprises at least one satellite navigation receiver, clock generator, processor and high stability crystal oscillator, described clock generator is directly connected with described high stability crystal oscillator, described processor and at least one satellite navigation receiver described, and described processor is directly connected with described clock generator and at least one satellite navigation receiver described.The present invention is used for the process of clock signal.
Description
Technical field
The present invention relates to electronic information field, particularly relate to a kind of method of clock source and signal transacting thereof.
Background technology
Along with the development of science and technology, satellite synchronizing clock source is more and more extensive in the demand of the high-tech sectors such as Aero-Space, weapon test, astronomical observation.Current most satellite synchronizing clock product-derived is all receive navigation satellite (GPS (GlobalPositioningSystem, global positioning system) or Beidou satellite navigation system) 1PPS (1pulsepersecond, pulse per second (PPS)) signal, the 1PPS signal fusing produced with local clock frequency division, by processor, filtering process is carried out to both time difference datas again, then control D/A (DigitaltoAnalogconverter, digital-to-analogue conversion) transducer produces corresponding analog voltage, realizes calibrating with this function that local clock exports.
But current product needed is produced separately special time difference measurement circuit, frequency division frequency multiplier circuit and D/A change-over circuit and processed the navigation satellite 1PPS signal that clock source receives, therefore product design is complicated, and the production cycle is longer.
Summary of the invention
The embodiment provides a kind of method of clock source and signal transacting thereof, the design complexities of product can be reduced, shorten the production cycle of product.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, embodiments of the invention provide a kind of clock source, comprising:
At least one satellite navigation receiver, clock generator, processor and high stability crystal oscillator, described clock generator is directly connected with described high stability crystal oscillator, described processor and at least one satellite navigation receiver described, described processor is directly connected with described clock generator and at least one satellite navigation receiver described, wherein
At least one satellite navigation receiver described is for receiving at least one road satellite navigation signals, described at least one road satellite navigation signals demodulation is generated at least one road satellite synchronization pps pulse per second signal, and described at least one road satellite synchronization pps pulse per second signal is sent to described processor and described clock generator;
Described at least one road satellite synchronization pps pulse per second signal that described processor sends for receiving at least one satellite navigation receiver described, selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal, generate control command described control command is sent to described clock generator according to selection result;
Described high stability crystal oscillator is used for generating reference frequency signal and described reference frequency signal is sent to described clock generator;
The described reference frequency signal that described clock transmitter sends for receiving described high stability crystal oscillator, receive the described control command that described processor sends, and according to described control command receive that at least one satellite navigation receiver described sends as described in the satellite synchronization pps pulse per second signal of target pps pulse per second signal, generate standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
In the implementation that the first is possible, in conjunction with first aspect, described clock generator comprises: system clock generator, control unit, digital phase-locked loop, digital to analog converter, filtering forming circuit and clock distributor;
Wherein, described system clock generator, for receiving the described reference clock signal that described high stability crystal oscillator sends, produces system clock frequency according to described reference clock signal;
Described control unit, for receiving the described control command that described processor sends, and according to described control command control that described input switch unit receives that at least one satellite navigation receiver described sends as described in the satellite synchronization pps pulse per second signal of target pps pulse per second signal, and by described input switch unit, described target pps pulse per second signal is sent to described digital phase-locked loop;
Described digital phase-locked loop, for receiving the described target pps pulse per second signal that described input switch unit sends, generating digital signal with reference to described target pps pulse per second signal and described system clock frequency, and described digital signal is sent to digital to analog converter;
Described digital to analog converter, for receiving the described digital signal that described digital phase-locked loop sends, described digital signal is changed into analog signal, and after described analog signal is carried out filtering process by described filtering forming circuit, carry out clock distribution by described clock distributor and export described standard-frequency signal.
In the implementation that the second is possible, in conjunction with the first possible implementation of first aspect, described digital phase-locked loop comprises: Direct Digital Frequency Synthesizers, digital loop filters, frequency divider, phase discriminator and frequency adjustment word generator;
Wherein, described Direct Digital Frequency Synthesizers, for generating digital signal with reference to described system clock frequency, is sent to described frequency divider by described digital signal;
Described frequency divider, for receiving the digital signal that described Direct Digital Frequency Synthesizers sends, by scaling down processing, isolating the inner pps pulse per second signal in a road, and sending described inner pps pulse per second signal to described phase discriminator from described digital signal;
Described phase discriminator, for receiving the described inner pps pulse per second signal of described target pps pulse per second signal and the transmission of described frequency divider, measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal, and after described phase difference is carried out filtering process by described digital loop filters, be sent to described frequency adjustment word generator;
Described frequency adjustment word generator, for receiving the described phase difference that described phase discriminator sends, according to the tuning word of described phase difference generated frequency, and is sent to described Direct Digital Frequency Synthesizers by described frequency tuning word;
Described Direct Digital Frequency Synthesizers, also for receiving the described frequency tuning word that described frequency adjustment word generator sends, and according to described frequency tuning regulation the frequency of digital signal.
In the implementation that the third is possible, the implementation that the second in conjunction with first aspect is possible, described Direct Digital Frequency Synthesizers is specifically for according to formula
regulate the frequency of described digital signal, wherein, F
ddsfor the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator, f
xtalfor the frequency of described reference clock signal.
In the 4th kind of possible implementation, in conjunction with the implementation that the second of first aspect is possible, described processor is also for recording described frequency tuning word, when at least one satellite navigation receiver described is all in out-of-lock condition, the described frequency tuning word of record is sent to described clock generator;
Described clock generator, also for being received the described frequency tuning word of the record that described processor sends by described control unit, and the described frequency tuning word of described record is forwarded to described Direct Digital Frequency Synthesizers by described frequency adjustment word generator, so that the frequency of described Direct Digital Frequency Synthesizers digital signal according to described frequency tuning regulation.
In the 5th kind of possible implementation, in conjunction with the clock source described in above-mentioned any one, described clock source also comprises: display screen;
At least one satellite navigation receiver described also for the satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information, and sends described UTC temporal information to described processor;
Described processor, also for receiving described UTC temporal information, select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information, and described target time information is sent to display screen;
Described display screen, for receiving the described target time information that described processor sends, and shows described temporal information.
Second aspect, embodiments of the invention provide a kind of method of clock signal process, comprising:
Clock source receives at least one road satellite navigation signals;
Described at least one road satellite navigation signals demodulation is generated at least one road satellite synchronization pps pulse per second signal;
Selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal;
Generating reference frequency signal, generates standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
In the implementation that the first is possible, in conjunction with first aspect, described with reference to described reference frequency signal and described target pps pulse per second signal generation standard-frequency signal, comprising:
System clock frequency is produced according to described reference frequency signal;
Digital signal is generated with reference to described target pps pulse per second signal and described system clock frequency;
Described digital signal is changed into analog signal, described analog signal is carried out filtering process, and the analog signal after filtering process is carried out clock distribution export described standard-frequency signal.
In the implementation that the second is possible, in conjunction with the first possible implementation of first aspect, describedly with reference to described target pps pulse per second signal, described system clock frequency is converted to digital signal, comprises:
Digital signal is generated with reference to described system clock frequency;
By scaling down processing, from described digital signal, isolate inner pps pulse per second signal;
Measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal;
According to the tuning word of described phase difference generated frequency, and according to described frequency tuning regulation the frequency of digital signal.
In the implementation that the third is possible, the implementation that the second in conjunction with first aspect is possible, described according to the tuning word of described phase difference generated frequency, and according to described frequency tuning regulation the frequency of digital signal, comprising:
According to formula
regulate the frequency of described digital signal, wherein F
ddsfor the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of described systematic clock generator, f
xtalfor the frequency of described reference clock signal.
In the 4th kind of possible implementation, the implementation that the second in conjunction with first aspect is possible, described method also comprises:
Record described frequency tuning word;
When described at least one road satellite synchronization pps pulse per second signal is all in out-of-lock condition, the frequency of digital signal described in the described frequency tuning regulation of reference record.
In the 5th kind of possible implementation, in conjunction with above-mentioned either method, described method also comprises:
The satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information;
Select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information;
Show described target time information.
The method of the clock source that the embodiment of the present invention provides and signal transacting thereof, by utilizing a kind of clock generator process satellite synchronization pps pulse per second signal, the synchronous pps pulse per second signal of reference satellite and the direct outputting standard frequency signal of internal reference clock signal, reduce the design complexities of product, shorten the production cycle.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of clock source structural representation that Fig. 1 provides for the embodiment of the present invention;
A kind of clock generator structure figure that Fig. 2 provides for the embodiment of the present invention;
The method flow schematic diagram of a kind of signal transacting that Fig. 3 provides for the embodiment of the present invention;
The method flow schematic diagram of the another kind of signal transacting that Fig. 4 provides for the embodiment of the present invention.
Reference numeral:
11-processor;
12-clock generator;
13-first satellite navigation receiver;
14-second satellite navigation receiver;
15-high stability crystal oscillator;
16-display screen;
21-system clock generator;
22-inputs switch unit;
23-control unit;
24-clock distributor;
25-filtering forming circuit;
26-digital to analog converter;
27-digital phase-locked loop;
271-frequency divider;
272-phase discriminator;
273-digital loop filters;
274-frequency adjustment word generator;
275-Direct Digital Frequency Synthesizers.
Embodiment
A kind of clock source provided the embodiment of the present invention below in conjunction with accompanying drawing and the method for signal transacting thereof carry out in detail, intactly describing.
The embodiment provides a kind of clock source, with reference to shown in Fig. 1, this clock source comprises: at least one satellite navigation receiver is (with the first satellite navigation receiver 13 in Fig. 1, second satellite navigation receiver 14 two satellite navigation is received as example and is described), clock generator 12, processor 11 and high stability crystal oscillator 15, clock generator 12 and high stability crystal oscillator 15, processor 11 and two satellite navigation receivers directly connect, processor 11 is directly connected with clock generator 12 and two satellite navigation receivers, wherein, processor 11 is by four-wire system SPI (SerialPeripheralInterface, synchronous serial Peripheral Interface) bus is connected with clock generator 12.The quantity of satellite navigation receiver preferably 2 ~ 8, here be not specifically limited, because GPS global positioning system is unified, Beidou satellite navigation system is Application comparison two kinds of satellite navigation systems widely, so be described for the clock signal of these two kinds of satellites at this, the clock signal of other satellites also can receive.
First satellite navigation receiver 13 and the second satellite navigation receiver 14 are for receiving at least one road satellite navigation signals, the satellite navigation signals of two satellite navigation receiver difference receiving world locational systems and Beidou satellite navigation system, at least one road satellite navigation signals demodulation received is generated at least one road satellite synchronization pps pulse per second signal, and at least one road satellite synchronization pps pulse per second signal generated is sent to processor 11 and clock generator 12.
The satellite synchronization pps pulse per second signal that processor 11 sends for receiving two satellite navigation receivers, selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal, generate control command control command is sent to clock generator 12 according to selection result.Wherein, priority can be the primary and backup relation of user-defined two satellite navigation receivers, and namely when satellite navigation receiver is main receiver, priority is higher, and when satellite navigation receiver is emergency receiver, priority is lower.
High stability crystal oscillator 15 is for generating reference frequency signal and be sent to clock generator 12 with reference to frequency signal, and optionally, the frequency of this signal adopts 10MHz.
The control command that clock transmitter sends for the reference frequency signal and processor 11 receiving high stability crystal oscillator 15 transmission, according to control command receiving target pps pulse per second signal, generates standard-frequency signal with reference to reference frequency signal and target pps pulse per second signal.Wherein, the frequency of the final standard-frequency signal exported can pass through clock generator sets itself according to user's request, and the general standard-frequency signal commonly used exported can be the signal etc. of 1PPS (pps pulse per second signal), 10MHz.Now clock source is operated in taming pattern.
The clock source that the embodiment of the present invention provides, by utilizing clock generator process satellite synchronization pps pulse per second signal, the synchronous pps pulse per second signal of reference satellite and the direct outputting standard frequency signal of internal reference clock signal, reduce the design complexities of product, shorten the production cycle.
Embodiments of the invention additionally provide a kind of concrete clock source, with reference to shown in Fig. 1, this clock source comprises: the first satellite navigation receiver 13, second satellite navigation receiver 14, clock generator 12, processor 11, high stability crystal oscillator 15 and display screen 16, clock generator 12 is directly connected with high stability crystal oscillator 15, processor 11 and two satellite navigation receivers, and processor 11 is directly connected with clock generator 12, display screen 16 and two satellite navigation receivers.
Optionally, with reference to shown in Fig. 2, clock generator 12 specifically comprises: system clock generator 21, input switch unit 22, control unit 23, digital phase-locked loop 27, digital to analog converter 26, filtering forming circuit 25 and clock distributor 24.
With reference to shown in Fig. 2, digital phase-locked loop 27 specifically comprises: frequency divider 271, phase discriminator 272, digital loop filters 273, frequency adjustment word generator 274, Direct Digital Frequency Synthesizers 275.
Wherein, first satellite navigation receiver 13 and the second satellite navigation receiver 14 are for receiving at least one road satellite navigation signals, the satellite navigation signals of two satellite navigation receiver difference receiving world locational systems and Beidou satellite navigation system, at least one road satellite navigation signals demodulation received is generated at least one road satellite synchronization pps pulse per second signal and UTC (UniversalTimeCoordinated, Coordinated Universal Time(UTC)) temporal information, at least one road satellite synchronization pps pulse per second signal and UTC temporal information are sent to processor 11 and clock generator 12.
Processor 11 is for receiving satellite synchronization pps pulse per second signal and the UTC temporal information of two satellite navigation receivers transmissions, selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal, generate control command according to selection result and control command is sent to clock generator 12, simultaneously, select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information, target time information is sent to display screen 16, the target time information that display screen 16 sends for receiving processor 11, and displaying time information.
Here, priority can be the primary and backup relation of user-defined two satellite navigation receivers, and namely when satellite navigation receiver is main receiver, priority is higher, and when satellite navigation receiver is emergency receiver, priority is lower.
High stability crystal oscillator 15 is for generating reference frequency signal and be sent to clock generator 12 with reference to frequency signal, and generally, the frequency of this signal is 10MHz.
Inner at clock generator 12, system clock generator 21, for receiving the reference clock signal of high stability crystal oscillator 15, produces system clock frequency according to reference clock signal.
Control unit 23, for the control command that receiving processor 11 sends, and receive the satellite synchronization pps pulse per second signal as target pps pulse per second signal of satellite navigation receiver transmission according to control command control inputs switch unit 22, and by input switch unit 22, target pps pulse per second signal is sent to digital phase-locked loop 27.Wherein, input switch unit 22 carries out can accomplishing seamless switching time input switches to the pps pulse per second signal that different satellite sends, and can not bring SPA sudden phase anomalies when namely switching.
In digital phase-locked loop 27, Direct Digital Frequency Synthesizers 275, generates digital signal for reference target pps pulse per second signal and system clock frequency, digital signal is sent to frequency divider 271.
Frequency divider 271, for receiving the digital signal that Direct Digital Frequency Synthesizers 275 sends, by scaling down processing, isolating the inner pps pulse per second signal in a road, and sending inner pps pulse per second signal to phase discriminator 272 from digital signal.
Phase discriminator 272, for the inside pps pulse per second signal that receiving target pps pulse per second signal and frequency divider 271 send, measure the phase difference of inner pps pulse per second signal and target pps pulse per second signal, and after phase difference is carried out filtering process by digital loop filters 273, be sent to frequency adjustment word generator 274.
Frequency adjustment word generator 274, for receiving the phase difference that phase discriminator 272 sends, according to the tuning word of phase difference generated frequency, and is sent to Direct Digital Frequency Synthesizers 275 by frequency tuning word.
Direct Digital Frequency Synthesizers 275, for the frequency tuning word that receive frequency regulates word generator 274 to send, and according to the frequency of frequency tuning regulation digital signal.
Concrete, Direct Digital Frequency Synthesizers 275 is according to formula
regulate the frequency of digital signal, wherein, F
ddsfor the frequency of digital signal, M is frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator 102, f
xtalfor the frequency of reference clock signal.
Digital phase-locked loop 27 is by frequency divider 271, phase discriminator 272, digital loop filters 273, frequency adjustment word generator 274, Direct Digital Frequency Synthesizers 275 circulates the tuning word of generated frequency, at first, Direct Digital Frequency Synthesizers 275 frame of reference clock frequency generates unstable digital signal, from this digital signal, divide the inner pps pulse per second signal in the road that occurs frequently to compare with the target pps pulse per second signal received, produce the frequency that frequency tuning word regulates this digital signal, again the digital signal after adjustment is fed back to frequency divider 271, generate new inside pps pulse per second signal, itself and the target pps pulse per second signal again received are compared, the frequency of further this digital signal of adjustment, so constantly this digital signal is compared with outside target impulse signal and regulate, inner pps pulse per second signal can be made to remain consistent with the frequency of the target pps pulse per second signal received.
Said process, clock source is operated in taming pattern, in order to ensure when at least one satellite navigation receiver is all in out-of-lock condition, clock source is still enough exports comparatively accurate standard-frequency signal, in the process of the tuning word of generated frequency, the frequency tuning word of record, also for the tuning word of recording frequency, when at least one satellite navigation receiver is all in out-of-lock condition, is sent to clock generator 12 by processor 11.
Clock generator 12 passes through control unit 23 by the frequency tuning word of receiving record, by frequency adjustment word generator 274, the frequency tuning word of record is sent to Direct Digital Frequency Synthesizers 275, so that Direct Digital Frequency Synthesizers 275 is according to the frequency of the frequency tuning regulation digital signal of record.
Like this, in an out-of-lock condition, the frequency of the frequency tuning word digital signal that regulates direct digital synthesiser to produce during lock-out state by record, the digital signal exported can be made still to keep higher accuracy and stability in the out-of-lock condition of short-term, and now clock source is operated in Holdover mode.
Digital to analog converter 26, for receiving the digital signal that Direct Digital Frequency Synthesizers 275 sends, digital signal is changed into analog signal, and analog passband signal is crossed after filtering forming circuit 25 carries out filtering process and carry out clock distribution outputting standard frequency signal by clock distributor 24.Herein, the frequency of standard-frequency signal can need sets itself according to user, and the most frequently used is 1PPS signal and 10MHz signal, and, clock distributor 24 can distribute multichannel standard-frequency signal simultaneously, and preferred situation is output 4 road standard-frequency signal.
Concrete, the first satellite navigation receiver 103 in the embodiment of the present invention and the second satellite navigation receiver 104 select M12T timing-type GPS receiver and Beidou II time service type receiver respectively, high stability crystal oscillator selects MV89 high stability crystal oscillator, STM32F107VC microprocessor selected by processor, and clock generator 102 selects AD9548 chip as clock generator.
The clock source that the embodiment of the present invention provides, by utilizing clock generator process satellite synchronization pps pulse per second signal, the synchronous pps pulse per second signal of reference satellite and the direct outputting standard frequency signal of internal reference clock signal, reduce the design complexities of product, shorten the production cycle.
The embodiment provides a kind of processing method of signal, with reference to shown in Fig. 3, the method comprises:
301, clock source receives at least one road satellite navigation signals.
302, the satellite navigation signals demodulation of at least one road is generated at least one road satellite synchronization pps pulse per second signal.
303, select be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal.
304, generating reference frequency signal, generates standard-frequency signal with reference to reference frequency signal and target pps pulse per second signal.
The method of the signal transacting that the embodiment of the present invention provides, by utilizing clock generator process satellite synchronization pps pulse per second signal, the synchronous pps pulse per second signal of reference satellite and the direct outputting standard frequency signal of internal reference clock signal, reduce the design complexities of product, shorten the production cycle.
Embodiments of the invention additionally provide the method for another kind of signal transacting, and with reference to shown in Fig. 4, the method comprises:
401, clock source receives at least one road satellite navigation signals.
402, the satellite navigation signals demodulation of at least one road is generated at least one road satellite synchronization pps pulse per second signal and UTC temporal information.
403, select be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal, select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information, and show this target time information.
404, generating reference frequency signal, produces system clock frequency according to reference frequency signal.
405, frame of reference clock frequency generates digital signal.
406, from digital signal, isolate the inner pps pulse per second signal in a road, and measure the phase difference of inner pps pulse per second signal and target pps pulse per second signal.
407, according to the tuning word of phase difference generated frequency, and according to the frequency of frequency tuning regulation digital signal.
Concrete, according to formula
regulate the frequency of digital signal, wherein F
ddsfor the frequency of digital signal, M is frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator 102, f
xtalfor the frequency of reference clock signal.
408, the tuning word of recording frequency, when at least one road satellite synchronization pps pulse per second signal is all in out-of-lock condition, the frequency of the frequency tuning regulation digital signal of reference record.
409, digital signal is changed into analog signal.
410, analog signal is carried out filtering process, and the analog signal after filtering process is carried out clock distribution outputting standard frequency signal.
The method of the signal transacting that the embodiment of the present invention provides, by utilizing clock generator process satellite synchronization pps pulse per second signal, the synchronous pps pulse per second signal of reference satellite and the direct outputting standard frequency signal of internal reference clock signal, reduce the design complexities of product, shorten the production cycle.
Above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (12)
1. a clock source, it is characterized in that, comprise: at least one satellite navigation receiver, clock generator, processor and high stability crystal oscillator, described clock generator is directly connected with described high stability crystal oscillator, described processor and at least one satellite navigation receiver described, described processor is directly connected with described clock generator and at least one satellite navigation receiver described, wherein
At least one satellite navigation receiver described is for receiving at least one road satellite navigation signals, described at least one road satellite navigation signals demodulation is generated at least one road satellite synchronization pps pulse per second signal, and described at least one road satellite synchronization pps pulse per second signal is sent to described processor and described clock generator;
Described at least one road satellite synchronization pps pulse per second signal that described processor sends for receiving at least one satellite navigation receiver described, selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal, generate control command described control command is sent to described clock generator according to selection result;
Described high stability crystal oscillator is used for generating reference frequency signal and described reference frequency signal is sent to described clock generator;
The described reference frequency signal that described clock transmitter sends for receiving described high stability crystal oscillator, receive the described control command that described processor sends, and according to described control command receive that at least one satellite navigation receiver described sends as described in the satellite synchronization pps pulse per second signal of target pps pulse per second signal, standard-frequency signal is generated with reference to described reference frequency signal and described target pps pulse per second signal, when described at least one road satellite synchronization pps pulse per second signal is all in out-of-lock condition, described standard-frequency signal is that the frequency tuning word of reference record generates.
2. clock source according to claim 1, is characterized in that, described clock generator comprises: system clock generator, control unit, digital phase-locked loop, digital to analog converter, filtering forming circuit and clock distributor;
Wherein, described system clock generator, for receiving the described reference clock signal that described high stability crystal oscillator sends, produces system clock frequency according to described reference clock signal;
Described control unit, for receiving the described control command that described processor sends, and according to described control command control inputs switch unit receive that at least one satellite navigation receiver described sends as described in the satellite synchronization pps pulse per second signal of target pps pulse per second signal, and by described input switch unit, described target pps pulse per second signal is sent to described digital phase-locked loop;
Described digital phase-locked loop, for receiving the described target pps pulse per second signal that described input switch unit sends, generating digital signal with reference to described target pps pulse per second signal and described system clock frequency, and described digital signal is sent to digital to analog converter;
Described digital to analog converter, for receiving the described digital signal that described digital phase-locked loop sends, described digital signal is changed into analog signal, and after described analog signal is carried out filtering process by described filtering forming circuit, carry out clock distribution by described clock distributor and export described standard-frequency signal.
3. clock source according to claim 2, is characterized in that, described digital phase-locked loop comprises: Direct Digital Frequency Synthesizers, digital loop filters, frequency divider, phase discriminator and frequency adjustment word generator;
Wherein, described Direct Digital Frequency Synthesizers, for generating digital signal with reference to described system clock frequency, is sent to described frequency divider by described digital signal;
Described frequency divider, for receiving the described digital signal that described Direct Digital Frequency Synthesizers sends, by scaling down processing, isolating the inner pps pulse per second signal in a road, and sending described inner pps pulse per second signal to phase discriminator from described digital signal;
Described phase discriminator, for receiving the described inner pps pulse per second signal of described target pps pulse per second signal and the transmission of described frequency divider, measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal, and after described phase difference is carried out filtering process by described digital loop filters, be sent to described frequency adjustment word generator;
Described frequency adjustment word generator, for receiving the described phase difference that described phase discriminator sends, according to the tuning word of described phase difference generated frequency, and is sent to described Direct Digital Frequency Synthesizers by described frequency tuning word;
Described Direct Digital Frequency Synthesizers, also for receiving the described frequency tuning word that described frequency adjustment word generator sends, and according to described frequency tuning regulation the frequency of digital signal.
4. clock source according to claim 3, is characterized in that,
Described Direct Digital Frequency Synthesizers is specifically for according to formula
regulate the frequency of described digital signal, wherein, F
ddsfor the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator, f
xtalfor the frequency of described reference clock signal.
5. clock source according to claim 3, is characterized in that,
The described frequency tuning word of record, also for recording described frequency tuning word, when at least one satellite navigation receiver described is all in out-of-lock condition, is sent to described clock generator by described processor;
Described clock generator, also for being received the described frequency tuning word of the record that described processor sends by described control unit, and the described frequency tuning word of described record is forwarded to described Direct Digital Frequency Synthesizers by described frequency adjustment word generator, so that the frequency of described Direct Digital Frequency Synthesizers digital signal according to described frequency tuning regulation.
6. the clock source according to any one of Claims 1 to 5, is characterized in that, described clock source also comprises: display screen;
At least one satellite navigation receiver described also for the satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information, and sends described UTC temporal information to described processor;
Described processor, also for receiving described UTC temporal information, select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information, and described target time information is sent to display screen;
Described display screen, for receiving the described target time information that described processor sends, and shows described temporal information.
7. a method for clock signal process, is characterized in that, comprising:
Clock source receives at least one road satellite navigation signals;
Described at least one road satellite navigation signals demodulation is generated at least one road satellite synchronization pps pulse per second signal;
Selection be in the lock state and priority comparatively Gao mono-road satellite synchronization pps pulse per second signal as target pps pulse per second signal;
Generating reference frequency signal, standard-frequency signal is generated with reference to described reference frequency signal and described target pps pulse per second signal, when described at least one road satellite synchronization pps pulse per second signal is all in out-of-lock condition, described standard-frequency signal is that the frequency tuning word of reference record generates.
8. method according to claim 7, is characterized in that, described with reference to described reference frequency signal and described target pps pulse per second signal generation standard-frequency signal, comprising:
System clock frequency is produced according to described reference frequency signal;
Digital signal is generated with reference to described target pps pulse per second signal and described system clock frequency;
Described digital signal is changed into analog signal, described analog signal is carried out filtering process, and the analog signal after filtering process is carried out clock distribution export described standard-frequency signal.
9. method according to claim 8, is characterized in that, describedly with reference to described target pps pulse per second signal, described system clock frequency is converted to digital signal, comprising:
Digital signal is generated with reference to described system clock frequency;
By scaling down processing, from described digital signal, isolate the inner pps pulse per second signal in a road;
Measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal;
According to the tuning word of described phase difference generated frequency, and according to described frequency tuning regulation the frequency of digital signal.
10. method according to claim 9, is characterized in that, described according to the tuning word of described phase difference generated frequency, and according to described frequency tuning regulation the frequency of digital signal, comprising:
And according to formula
regulate the frequency of described digital signal, wherein F
ddsfor the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of described systematic clock generator, f
xtalfor the frequency of described reference clock signal.
11. methods according to claim 9, is characterized in that, described method also comprises:
Record described frequency tuning word;
When described at least one road satellite synchronization pps pulse per second signal is all in out-of-lock condition, the frequency of digital signal described in the described frequency tuning regulation of reference record.
12. methods according to any one of claim 7 ~ 11, it is characterized in that, described method also comprises:
The satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information;
Select to be in the lock state and the priority UTC temporal information corresponding compared with Gao mono-road satellite synchronization pps pulse per second signal as target time information;
Show described target time information.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9385769B2 (en) * | 2014-12-05 | 2016-07-05 | Xilinx, Inc. | Phase-locked loop with an adjustable output divider |
| CN106877963B (en) * | 2016-12-29 | 2018-10-09 | 河北远东通信***工程有限公司 | A kind of synchronised clock holding system and method with learning functionality |
| CN107222210B (en) * | 2017-06-07 | 2020-08-04 | 中国电子科技集团公司第二十四研究所 | DDS system capable of configuring digital domain clock phase by SPI |
| CN109814370B (en) * | 2019-01-30 | 2020-10-23 | 深圳国人通信股份有限公司 | Clock synchronization system |
| CN111427074B (en) * | 2020-06-10 | 2020-10-09 | 天津七一二通信广播股份有限公司 | GBAS-based high-reliability time system service equipment |
| CN113644910B (en) * | 2021-08-18 | 2022-03-25 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN114994727B (en) * | 2022-07-18 | 2022-12-02 | 成都迅翼卫通科技有限公司 | Equipment for realizing high-precision time calibration and satellite positioning |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1770634A (en) * | 2004-10-26 | 2006-05-10 | 大唐移动通信设备有限公司 | Clock phase-locked loop apparatus |
| US20070182467A1 (en) * | 2006-02-08 | 2007-08-09 | Fujitsu Limited | DPLL circuit having holdover function |
| CN101321051A (en) * | 2008-05-28 | 2008-12-10 | 京信通信***（中国）有限公司 | Clock synchronization apparatus and method for radio frequency remote unit |
| CN202026300U (en) * | 2011-04-06 | 2011-11-02 | 江汉大学 | Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer |
| CN202150850U (en) * | 2011-07-05 | 2012-02-22 | 上海埃威航空电子有限公司 | Frequency synthesizing device using GNSS second pulse for rapid modification |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102447470A (en) * | 2010-10-15 | 2012-05-09 | 卢珊 | Direct digital frequency synthesis (DDS)-based signal source |
| CN102064853B (en) * | 2010-10-27 | 2013-05-01 | 西安空间无线电技术研究所 | Method for simulating frequency dynamic of radio frequency signal at intermediate frequency by using two DDSs |
| CN102468868B (en) * | 2010-11-03 | 2016-03-30 | 苏州普源精电科技有限公司 | DDS signal generator and frequency-hopping method |
| CN203261316U (en) * | 2013-05-28 | 2013-10-30 | 中国人民解放军63921部队 | Clock source |
-
2013
- 2013-05-28 CN CN201310203139.1A patent/CN103281076B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1770634A (en) * | 2004-10-26 | 2006-05-10 | 大唐移动通信设备有限公司 | Clock phase-locked loop apparatus |
| US20070182467A1 (en) * | 2006-02-08 | 2007-08-09 | Fujitsu Limited | DPLL circuit having holdover function |
| CN101321051A (en) * | 2008-05-28 | 2008-12-10 | 京信通信***（中国）有限公司 | Clock synchronization apparatus and method for radio frequency remote unit |
| CN202026300U (en) * | 2011-04-06 | 2011-11-02 | 江汉大学 | Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer |
| CN202150850U (en) * | 2011-07-05 | 2012-02-22 | 上海埃威航空电子有限公司 | Frequency synthesizing device using GNSS second pulse for rapid modification |
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