CN103281067A - False-operation resistant buffering port - Google Patents
False-operation resistant buffering port Download PDFInfo
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- CN103281067A CN103281067A CN2013102334820A CN201310233482A CN103281067A CN 103281067 A CN103281067 A CN 103281067A CN 2013102334820 A CN2013102334820 A CN 2013102334820A CN 201310233482 A CN201310233482 A CN 201310233482A CN 103281067 A CN103281067 A CN 103281067A
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Abstract
The invention discloses a false-operation resistant buffering port which comprises a false-operation resistant circuit and a buffering circuit. The false-operation resistant circuit comprises a triode Q1 and a control circuit. The buffering circuit is arranged between a grid electrode of a field-effect tube Q2 and a port of the field-effect tube Q2 and comprises a trigger JK, a timer HM and an electronic switch J. The false-operation resistant buffering port has the advantages that the false-operation resistant buffering port is arranged between a switch port and an internal circuit and the buffering circuit is firstly started and can be completely started in a set time, so that damage caused by surging and over-voltage to a following circuit is avoided; then the false operation resistant circuit is started, a capacitor in the circuit needs to be charged firstly, and then the switch port is connected with the internal circuit, so that start of a switch is effective. Therefore, when the switch is operated by mistake, the switch is rapidly switched off and the switch port is not connected with the internal circuit in the period, so that no influence is generated and an electronic device is protected.
Description
Technical field
The present invention relates to a kind of protective circuit, particularly relate to a kind of faulty action preventing buffered port.
Background technology
The switch of a lot of electronic devices is often opened because bump by mistake, bring a lot of inconvenience to the user, need meticulous in use, expend the very big mind, and a switch of running into comparison danger, the damage of electronic device may be caused, even cause the accident that some are difficult to estimate, and electronic equipment is frequent because of the moment unlatching, and phenomenons such as overvoltage, surge occur, thereby causes the interior circuit of electronic equipment to be destroyed.
Summary of the invention
The objective of the invention is to overcome the shortcoming and defect of above-mentioned prior art, a kind of faulty action preventing buffered port is provided, the switch that overcomes existing electronic device is accidents caused because bumped by mistake, and the defective that circuit often damages because of overvoltage, surge appearance in the electronic equipment.
Purpose of the present invention is achieved through the following technical solutions: the faulty action preventing buffered port, comprise faulty action preventing circuit and buffering circuit, described faulty action preventing circuit comprises triode Q1 and control circuit, the collector electrode of described triode Q1 is connected to port, emitter is connected to internal circuit, control circuit one end connectivity port, the other end connects triode Q1, described control circuit comprises comparison circuit and comparator M, described comparison circuit comprises first comparison circuit and second comparison circuit, first comparison circuit comprises field effect transistor Q2, resistance R 1 and capacitor C, the source electrode of field effect transistor Q2 is connected to power supply, its drain electrode is successively by resistance R 1, capacitor C ground connection, the grid of field effect transistor Q2 is connected to port, described second comparison circuit comprises resistance R 2 and voltage stabilizing didoe D, the negative pole of described voltage stabilizing didoe D is connected to power supply by resistance R 2, its plus earth, the input of described comparator M is connected the end of capacitor C connecting resistance R1, its other end is connected the negative pole of voltage stabilizing didoe D, described buffer circuit is arranged between the grid and port of field effect transistor Q2, comprise trigger JK, timer HM and electronic switch J, described electronic switch J one end connectivity port, the other end connects the grid of field effect transistor Q2, the input of trigger JK is connected to port, its output is connected to timer HM, and the output of timer HM is connected to the control end of electronic switch J.
Between the setting of this circuit and switch port and the internal circuit, use triode Q1 to come control port to connect internal circuit, when pressing port, port can not be communicated to internal circuit immediately, because at this moment triode Q ends, the voltage of port is opened field effect transistor Q2 earlier, make the comparison circuit of winning connect power supply, capacitor C is charged, when the voltage on the capacitor C during greater than the voltage stabilizing value of voltage stabilizing didoe D, comparator M just output voltage makes triode Q connection to the base stage of triode Q1, the comparator M of this circuit just has output voltage for when the input voltage that connects capacitor C during greater than the input voltage of connection voltage stabilizing didoe D.Buffer circuit also is set in this circuit, when port rigidly connects electricity, the electric current of port flows into trigger JK, thereby open trigger JK, trigger JK opens timer HM again and carries out timing, namely transmits a signal to electronic switch J behind the timing certain hour, unlocking electronic switch J, can open being connected of port and faulty action preventing circuit, this circuit delay electronic equipment start-up time, reduced the occurrence probability of surge and overvoltage phenomenon.
Further, be provided with a preventative resistance R3 between the grid of above-mentioned field effect transistor Q2 and the source electrode, protection field effect transistor Q2.
Further, above-mentioned comparator M employing model is the comparator of LM339.
The invention has the beneficial effects as follows: this circuit is arranged between the switch port and internal circuit of electronic device; at first open buffer circuit; buffer circuit can start in setting-up time fully; avoided surge and overvoltage to the destruction of subsequent conditioning circuit like this; be the faulty action preventing circuit afterwards; electric capacity will be recharged earlier in this circuit; just can open port then to the connection of internal circuit; at this moment switch open is effective; when the malfunction switch, as long as the quick closedown switch, port does not connect upward internal circuit in the meantime like this; do not have any influence, protected electronic device.
Description of drawings
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the structural representation of embodiment 2.
Embodiment
The present invention is described in further detail below in conjunction with embodiment, but structure of the present invention is not limited only to following examples:
[embodiment 1]
As shown in Figure 1, the faulty action preventing buffered port, comprise faulty action preventing circuit and buffering circuit, described faulty action preventing circuit comprises triode Q1 and control circuit, the collector electrode of described triode Q1 is connected to port, emitter is connected to internal circuit, control circuit one end connectivity port, the other end connects triode Q1, described control circuit comprises comparison circuit and comparator M, described comparison circuit comprises first comparison circuit and second comparison circuit, first comparison circuit comprises field effect transistor Q2, resistance R 1 and capacitor C, the source electrode of field effect transistor Q2 is connected to power supply, its drain electrode is successively by resistance R 1, capacitor C ground connection, the grid of field effect transistor Q2 is connected to port, described second comparison circuit comprises resistance R 2 and voltage stabilizing didoe D, the negative pole of described voltage stabilizing didoe D is connected to power supply by resistance R 2, its plus earth, the input of described comparator M is connected the end of capacitor C connecting resistance R1, its other end is connected the negative pole of voltage stabilizing didoe D, described buffer circuit is arranged between the grid and port of field effect transistor Q2, comprise trigger JK, timer HM and electronic switch J, described electronic switch J one end connectivity port, the other end connects the grid of field effect transistor Q2, the input of trigger JK is connected to port, and its output is connected to timer HM, and the output of timer HM is connected to the control end of electronic switch J.
Between the setting of this circuit and switch port and the internal circuit, use triode Q1 to come control port to connect internal circuit, when pressing port, port can not be communicated to internal circuit immediately, because at this moment triode Q ends, the voltage of port is opened field effect transistor Q2 earlier, make the comparison circuit of winning connect power supply, capacitor C is charged, when the voltage on the capacitor C during greater than the voltage stabilizing value of voltage stabilizing didoe D, comparator M just output voltage makes triode Q connection to the base stage of triode Q1, the comparator M of this circuit just has output voltage for when the input voltage that connects capacitor C during greater than the input voltage of connection voltage stabilizing didoe D.Buffer circuit also is set in this circuit, when port rigidly connects electricity, the electric current of port flows into trigger JK, thereby open trigger JK, trigger JK opens timer HM again and carries out timing, namely transmits a signal to electronic switch J behind the timing certain hour, unlocking electronic switch J, can open being connected of port and faulty action preventing circuit, this circuit delay electronic equipment start-up time, reduced the occurrence probability of surge and overvoltage phenomenon.
It is the comparator of LM339 that above-mentioned comparator M adopts model.
[embodiment 2]
As Fig. 2, the structure of present embodiment and embodiment 1 basically identical, difference is to be provided with a preventative resistance R3 between the grid of field effect transistor Q2 and the source electrode, protection field effect transistor Q2.
Claims (3)
1. faulty action preventing buffered port, it is characterized in that, comprise faulty action preventing circuit and buffering circuit, described faulty action preventing circuit comprises triode Q1 and control circuit, the collector electrode of described triode Q1 is connected to port, emitter is connected to internal circuit, control circuit one end connectivity port, the other end connects triode Q1, described control circuit comprises comparison circuit and comparator M, described comparison circuit comprises first comparison circuit and second comparison circuit, first comparison circuit comprises field effect transistor Q2, resistance R 1 and capacitor C, the source electrode of field effect transistor Q2 is connected to power supply, its drain electrode is successively by resistance R 1, capacitor C ground connection, the grid of field effect transistor Q2 is connected to port, described second comparison circuit comprises resistance R 2 and voltage stabilizing didoe D, the negative pole of described voltage stabilizing didoe D is connected to power supply by resistance R 2, its plus earth, the input of described comparator M is connected the end of capacitor C connecting resistance R1, its other end is connected the negative pole of voltage stabilizing didoe D, described buffer circuit is arranged between the grid and port of field effect transistor Q2, comprise trigger JK, timer HM and electronic switch J, described electronic switch J one end connectivity port, the other end connects the grid of field effect transistor Q2, the input of trigger JK is connected to port, and its output is connected to timer HM, and the output of timer HM is connected to the control end of electronic switch J.
2. faulty action preventing buffered port according to claim 1 is characterized in that, is provided with a preventative resistance R3 between the grid of described field effect transistor Q2 and the source electrode.
3. faulty action preventing buffered port according to claim 1 is characterized in that, it is the comparator of LM339 that described comparator M adopts model.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102334820A CN103281067A (en) | 2013-06-14 | 2013-06-14 | False-operation resistant buffering port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102334820A CN103281067A (en) | 2013-06-14 | 2013-06-14 | False-operation resistant buffering port |
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| CN103281067A true CN103281067A (en) | 2013-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013102334820A Pending CN103281067A (en) | 2013-06-14 | 2013-06-14 | False-operation resistant buffering port |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109308038A (en) * | 2018-11-12 | 2019-02-05 | 国核自仪***工程有限公司 | The logic processing module of anti-error driving |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2339248Y (en) * | 1998-08-15 | 1999-09-22 | 江西三星电子有限公司 | Electric ignition starter for airosol fire distinguisher |
| CN2588522Y (en) * | 2002-11-26 | 2003-11-26 | 柳玉高 | Multi-function direct loading type leakage relay |
| US6966261B2 (en) * | 2003-05-20 | 2005-11-22 | Alliant Techsystems Inc. | Fuze explosive ordnance disposal circuit |
| CN201243400Y (en) * | 2008-05-20 | 2009-05-20 | 朱其银 | Electronic trigger |
| CN101963792A (en) * | 2010-10-29 | 2011-02-02 | 珠海市鑫和电器有限公司 | Time sequence control circuit and control method thereof |
| CN102209409A (en) * | 2010-03-31 | 2011-10-05 | 鸿富锦精密工业（深圳）有限公司 | Light-controlled electronic switching circuit |
| CN102739213A (en) * | 2012-07-18 | 2012-10-17 | 常州电子研究所有限公司 | Permanent magnetic coil driving circuit |
-
2013
- 2013-06-14 CN CN2013102334820A patent/CN103281067A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2339248Y (en) * | 1998-08-15 | 1999-09-22 | 江西三星电子有限公司 | Electric ignition starter for airosol fire distinguisher |
| CN2588522Y (en) * | 2002-11-26 | 2003-11-26 | 柳玉高 | Multi-function direct loading type leakage relay |
| US6966261B2 (en) * | 2003-05-20 | 2005-11-22 | Alliant Techsystems Inc. | Fuze explosive ordnance disposal circuit |
| CN201243400Y (en) * | 2008-05-20 | 2009-05-20 | 朱其银 | Electronic trigger |
| CN102209409A (en) * | 2010-03-31 | 2011-10-05 | 鸿富锦精密工业（深圳）有限公司 | Light-controlled electronic switching circuit |
| CN101963792A (en) * | 2010-10-29 | 2011-02-02 | 珠海市鑫和电器有限公司 | Time sequence control circuit and control method thereof |
| CN102739213A (en) * | 2012-07-18 | 2012-10-17 | 常州电子研究所有限公司 | Permanent magnetic coil driving circuit |
Non-Patent Citations (1)
| Title |
|---|
| 陆建敏: "光敏传感器的应用-声光控开关电路", 《企业科技与发展》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109308038A (en) * | 2018-11-12 | 2019-02-05 | 国核自仪***工程有限公司 | The logic processing module of anti-error driving |
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Application publication date: 20130904 |