CN103280503B - Semiconductor device - Google Patents
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- CN103280503B CN103280503B CN201310198971.7A CN201310198971A CN103280503B CN 103280503 B CN103280503 B CN 103280503B CN 201310198971 A CN201310198971 A CN 201310198971A CN 103280503 B CN103280503 B CN 103280503B
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Abstract
The invention provides a semiconductor device, belonging to the technical field of semiconductors and solving the problems that inevitable lattice mismatch and heat expansion mismatch exist between the existing substrate and an epitaxial layer, and the internal electric field problem caused by spontaneous polarization and voltage polarization also exists. The semiconductor device comprises a substrate and an action layer, wherein an n-type semiconductor which is provided with an n-type electrode and a p-type semiconductor which is provided with a p-type electrode grow on the substrate, and a buffering layer capable of reducing the influence of defects of crystals on the substrate on the semiconductor device grows between the substrate and the action layer. Through growing the buffering layer capable of reducing the influence of defects of the crystals on the substrate on the semiconductor device between the substrate and the action layer, better reliability and higher efficiency can be realized.
Description
Technical field
The invention belongs to technical field of semiconductors, it is related to semiconductor devices, particularly in lining
Not only the p-type semiconductor containing p-type electrode but also the n-type semiconductor containing n-type electrode on bottom
Semiconductor devices.
Background technology
In prior art, the not only p-type semiconductor containing p-type electrode but also contain on substrate
The semiconductor devices of the n-type semiconductor of n-type electrode is simply simply by power output.By
There is crystal defect in substrate in itself, in this case, substrate also will pass through heterogeneous
Epitaxy technology grown epitaxial layer, and backing material is different from the material of epitaxial layer, because
Inevitably there is lattice mismatch in this substrate and epitaxial layer（lattice mismatch）
With the problem of heat expansion mismatch, there is also spontaneous polarization and voltage polarizing simultaneously and cause
The problem of internal electric field, have impact on luminous efficiency.
In addition, the efficiency of Internal Quantum has very strong inverse ratio pass with the density of crystal defect
System, therefore, it is all extremely difficult for improving its design and controlling.Also be necessary into
One step ground improves power output efficiency, increases horsepower output.For reaching this purpose,
Need to enter on the basis of all few high-quality crystallization of crystal defect and impurity content
OK, and also to reduce Internal Quantum non-luminescent in conjunction with ratio, improve internal amount
Son efficiency so that develop make efficient semiconductor devices.
Content of the invention
The present invention there are the problems referred to above for existing technology it is proposed that a kind of semiconductor device
Part, the technical problem to be solved：For p-type electrode had both been contained on substrate
The p-type semiconductor again n-type semiconductor containing n-type electrode semiconductor devices, how
The impact to action layer for the crystal defect of minimizing substrate, and then improve the effect of semiconductor devices
Rate and reliability.
The present invention is realized by following technical proposal：Semiconductor devices includes substrate and moves
Make layer, growth over the substrate has the n-type semiconductor being provided with n-type electrode and growth to have
It is provided with the p-type semiconductor of p-type electrode it is characterised in that in described substrate and action layer
Between growth have and can reduce the cushion that substrate crystal defect affects on semiconductor devices.
Because the crystal defect of substrate is inevitable, the present invention passes through in substrate growth extension
Surface on grown buffer layer come to reduce substrate crystal defect on semiconductor devices affect, from
And improve efficiency and the reliability of semiconductor devices.
In above-mentioned semiconductor devices, described substrate is monocrystalline Al2O3, monocrystal SiC,
Monocrystalline GaN, monocrystalline Ga2O3, single crystal ZnO, monocrystalline GaAs, monocrystalline InP or single crystalline Si；
Or Al2O3、SiC、GaN、Ga2O3, ZnO or Si single material is in polycrystalline state
Upper one layer of monocrystalline of combination and formed integration substrate；Or above-mentioned single material is non-
The substrate of integration is formed with reference to one layer of monocrystalline on crystalline state.Above-mentioned material refers to
Al2O3、SiC、GaN、Ga2O3, ZnO, GaAs, InP or Si, these materials have list
Crystalline state, polycrystalline state and non-crystalline state.
In above-mentioned semiconductor devices, described substrate forms III group-III nitride and partly leads
Body or the action of group Ⅲ-Ⅴ compound semiconductor or group Ⅱ-Ⅵ compound semiconductor
Layer.Action layer is one layer in chip, can produce power output, such as light output, signal
Output.
In above-mentioned semiconductor devices, described III group-III nitride semiconductor refer to containing
One or more and the mixed crystal compound semiconductor that formed of GaN, InN or AlN；Institute
The group Ⅲ-Ⅴ compound semiconductor stated refers to containing GaAs, InAs, InP or AlAs
One or more and the mixed crystal compound semiconductor that formed；II-VI described compounds of group
Semiconductor refers to containing ZnO, ZnS, ZnSe, CdO, MgO, MgZnO, MgS, MgSe
Or one or several and the mixed crystal compound semiconductor that formed of CdS.
In above-mentioned semiconductor devices, described substrate is used for growing the rough surface of extension
Degree is limited to below 15nm.
In above-mentioned semiconductor devices, described substrate is given birth to by chemical vapour deposition technique
Length has GaN low temperature depositing layer or AlGaN layer or AlN layer to form first buffer layer；
Or described Grown has in GaN low temperature depositing layer, AlGaN layer or AlN layer
Two-layer or hybrid multilayer form first buffer layer；Or epitaxial lateral is passed through on described substrate
The growth of undue growth method have in GaN low temperature depositing layer, AlGaN layer or AlN layer one layer or
Multilayer and the first buffer layer that formed.
In above-mentioned semiconductor devices, growth in described first buffer layer has second to delay
Rush layer, second buffer layer is that the GaN/InAlGaN/AlGaN containing InAlGaN layer is combined
Layer, GaN/InAlGaN/AlGaN composite bed refers to grow InAlGaN layer in GaN layer,
On InAlGaN layer, growth has AlGaN layer；Or containing above-mentioned
The sandwich construction of GaN/InAlGaN/AlGaN composite bed is as second buffer layer.
In above-mentioned semiconductor devices, the InAlGaN in described second buffer layer is：
InxAlyGazN, 0.05<x<0.11,y=4.66x,z=1-x-y.
In above-mentioned semiconductor devices, grow ZnO low temperature depositing layer over the substrate
Or CaF2 layer becomes cushion, or in Grown ZnO low temperature depositing layer and
CaF2 layer, ZnO low temperature depositing layer and CaF2 layer form composite bed and as cushion.?
Can be by forming multiple ZnO/CaF2Composite bed is as cushion.
In above-mentioned semiconductor devices, grow GaAs, InAs, InP over the substrate
Or one or more of AlAs are as cushion.Be cushion be GaAs, InAs,
In one of InP or AlAs, or GaAs, InAs, InP or AlAs
Two kinds and the composite bed that formed by both form MULTILAYER COMPOSITE layer, or
Three kinds in GaAs, InAs, InP or AlAs and the composite bed that formed by these three
Formed MULTILAYER COMPOSITE layer, or four kinds in GaAs, InAs, InP or AlAs with
And the composite bed being formed by these four forms MULTILAYER COMPOSITE layer.
Compared with prior art, the present invention passes through growth buffering between substrate and action layer
Layer come to reduce substrate crystal defect on semiconductor devices affect, have preferable high reliability and
Higher efficiency.In addition, can using growing second buffer layer in first buffer layer
Enough relax the crystal defect because lattice mismatch leads to and spontaneous polarization and voltage polarizing and draw
The generation of the internal electric field rising, to both p-type semiconductor containing p-type electrode on substrate
The semiconductor devices of the n-type semiconductor containing n-type electrode can accomplish controlled Gao Gong again
Rate exports, and also also can be used the substrate of poor quality simultaneously, improves lining
The utilization rate at bottom.
Brief description
Fig. 1 is the structural representation of semiconductor devices.
Fig. 2 is the structural representation of semiconductor epitaxial crystal piece.
Fig. 3 is the graphic layer structure of epitaxy junction wafer layers extension.
Fig. 4 is the graphic layer structure of embodiment 2 epitaxy junction wafer layers extension.
Fig. 5 is the graphic layer structure of embodiment 3 epitaxy junction wafer layers extension.
Fig. 6 is the graphic layer structure of embodiment 4 epitaxy junction wafer layers extension.
Fig. 7, Fig. 8 are the graphic layer structures of embodiment 5 epitaxy junction wafer layers extension.
Fig. 9 is the constituent of In in cushion in InxAlyGazN layer polarization phenomena right
Answer table.
In figure, 1, substrate；2nd, cushion；21st, first buffer layer；22nd, second delays
Rush layer；3rd, N-shaped cladding layer；4th, action layer；5th, p-type cladding layer；6th, p-type contact
Layer；7th, n-contact layer.
Specific embodiment
The following is the specific embodiment of the present invention and combine accompanying drawing, the technical side to the present invention
Case is further described, but the present invention is not limited to these embodiments.
Embodiment 1：
Semiconductor devices of the present invention includes substrate and action layer, is provided with Grown
The n-type semiconductor of n-type electrode and growth have the p-type semiconductor being provided with p-type electrode,
Grow to have between substrate life and action layer and can reduce substrate crystal defect to semiconductor devices
The cushion of impact.Taking following concrete structure as a example：
Semiconductor devices as depicted in figs. 1 and 2, it includes substrate 1, in substrate 1
On cushion 2 and the n-contact layer 7 in substrate 1 opposite side, on the buffer layer 2
There are N-shaped cladding layer 3, action layer 4, p-type cladding layer 5 and P type contact layer 6, p-type
Connect p-type electrode on contact layer 6, n-contact layer 7 connects n-type electrode.This knot
It is configured to have the n-type semiconductor connecting n-type electrode and growth to have connection in Grown
The semiconductor devices of the p-type semiconductor of p-type electrode, both both contained on substrate and was provided with p
The p-type semiconductor of type electrode contains the semiconductor of the n-type semiconductor being provided with n-type electrode again
Device.
Because cushion can reduce substrate crystal defect, semiconductor devices is affected, therefore,
The technical requirements for materials of substrate just can be reduced, substrate can be monocrystalline Al2O3, monocrystalline
SiC, monocrystalline GaN, monocrystalline Ga2O3, single crystal ZnO, monocrystalline GaAs, monocrystalline InP or
Single crystalline Si.These monocrystal materials can also from some second-rate as substrate to reduce
Cost, or directly using Al2O3、SiC、GaN、Ga2O3、ZnO、GaAs、InP
Or Si material forms the substrate of integration on polycrystalline state with reference to one layer of monocrystalline；Use
Above-mentioned single material forms the lining of integration on non-crystalline state with reference to one layer of monocrystalline
Bottom.Also the cost of backing material can further be reduced using these substrates.
Substrate passes through be epitaxially-formed III group-III nitride semiconductor or III-V
The action layer of compound semiconductor or group Ⅱ-Ⅵ compound semiconductor.III group-III nitride
Semiconductor or group Ⅲ-Ⅴ compound semiconductor can be to send visible ray or ultraviolet
The light output semiconductor of linear light or infrared ray.
III group-III nitride semiconductor refers to one or more containing GaN, InN or AlN
And the mixed crystal compound semiconductor being formed；Described group Ⅲ-Ⅴ compound semiconductor refers to contain
There are one or more and the mixed crystal compound that formed of GaAs, InAs, InP or AlAs
Semiconductor；Described group Ⅱ-Ⅵ compound semiconductor refer to containing ZnO, ZnS, ZnSe,
CdO, MgO, MgZnO, MgS, MgSe or CdS one or several and formed
Mixed crystal compound semiconductor.
In order to improve the power of semiconductor devices, substrate is used for growing the surface of extension
Roughness is limited to below 15nm.According to reciprocal space（Reciprocal lattice
space）Construction, the form of epitaxial surface and the result of structural analysis, substrate is used for
The surface roughness of growth extension is limited to during below 15nm and can make substrate 1 and epitaxy junction
The mixed proportion of the hexagonal crystal of the faying face between chip and cubic crystal controls below 1%.
Mixed proportion controls the spontaneous polarization effect that can reduce Internal Quantum in 1%, improves and sends out
Light efficiency.
For the action layer of III group-III nitride semiconductor, cushion has first buffer layer and life
Long second buffer layer in first buffer layer.Chemical vapour deposition technique is passed through on substrate
Growth has GaN low temperature depositing layer or AlGaN layer or AlN layer to form first buffer layer；
Or described Grown has in GaN low temperature depositing layer, AlGaN layer or AlN layer
Two-layer or hybrid multilayer form first buffer layer；Or epitaxial lateral is passed through on described substrate
The growth of undue growth method has in GaN layer, AlGaN layer or AlN layer one or more layers and shape
The first buffer layer becoming.Second buffer layer is containing InAlGaN layer
GaN/InAlGaN/AlGaN composite bed, GaN/InAlGaN/AlGaN composite bed refers to
InAlGaN layer is grown, growth on InAlGaN layer has AlGaN layer in GaN layer；Or
Person contains the sandwich construction of above-mentioned GaN/InAlGaN/AlGaN composite bed as the second buffering
Layer.InAlGaN in second buffer layer is：InxAlyGazN, 0.05<
x<0.11,y=4.66x,z=1-x-y.InxAlyGazThe component ratio of N layer exists
0.05<x<When in 0.11, y=4.66x, z=1-x-y scope, can relax because of lattice mismatch
The crystal defect leading to and spontaneous polarization and piezoelectric polarization and the product of internal electric field that causes
Raw.As shown in figure 9, Fig. 9 is the constituent of In in cushion in InxAlyGazN layer
The corresponding table of polarization phenomena, by this corresponding table, when the constituent of In exists
When between 0.05-0.11, polarization phenomena are between 0.042-0.06, can relax because
Crystal defect that lattice mismatch leads to and spontaneous polarization and piezoelectric polarization and the inside that causes
The generation of electric field.
For the action layer of group Ⅱ-Ⅵ compound semiconductor, cushion is：Grown
ZnO low temperature depositing layer or CaF2 layer become cushion, or in Grown ZnO
Low temperature depositing layer and CaF2 layer, ZnO low temperature depositing layer and CaF2 layer form composite bed and
As cushion.Can also be by forming multiple ZnO/CaF2Composite bed is as cushion.
For the action layer of group Ⅲ-Ⅴ compound semiconductor, cushion is：Raw on substrate
One or more of long GaAs, InAs, InP or AlAs are as cushion.It is slow
Rush layer be one of GaAs, InAs, InP or AlAs, or GaAs, InAs,
Two kinds in InP or AlAs and the composite bed that formed by both form MULTILAYER COMPOSITE
Layer, or three kinds in GaAs, InAs, InP or AlAs and by these three shapes
The composite bed becoming forms MULTILAYER COMPOSITE layer, or GaAs, InAs, InP or AlAs
In four kinds and the composite bed that formed by these four form MULTILAYER COMPOSITE layer.
It is substrate 1 with SiC below and growing group III nitride semiconductor epitaxial crystal piece is
Example：
As shown in figure 3, first by the surface of SiC substrate 1 after treatment, roughness drops
To below 15nm, reuse chemical gaseous phase deposition MOCVD (Metal-organic
Chemical Vapor Deposition) equipment by epitaxial crystallization growth method grow extension,
Form epitaxy junction chip.
Make epitaxy junction chip with MOCVD epitaxy crystalline growth legal system in SiC substrate 1
Process is as follows：In SiC substrate 1, growth a layer thickness is 0.1 μm of doping Si concentration
For 5E18/cm3N-GaN low temperature accumulation horizon, this low temperature accumulation horizon is grown to the first buffering
Layer 21, then growth thickness is 5E18/cm for 50nm doping Si concentration3's
n-AlxGa1-xN layer, in this example, x=0.09；Regrowth thickness is 0.2 μm of doping
Si concentration is 5E18/cm3N-GaN layer, next growth thickness 50nm doping Si
Concentration is 5E18/cm3N-In0.09Al0.32Ga0.59N layer, 0.2 μm of regrowth thickness is mixed
Miscellaneous Si concentration is 5E18/cm3N-GaN layer；n-AlxGa1-xN layer, n-GaN layer,
n-In0.09Al0.32Ga0.59N layer and n-GaN layer constitute second buffer layer 22.
After having grown second buffer layer 22, growing 0.5 μm of doping Si of thickness successively
Concentration 5E18/cm3N-AlxGa1-xN cladding layer, x=0.15；In 0.2 μm of thickness of growth
Undoped concentration<1E16/cm3I-InyGa1-yN action layer 4, wherein y=0.2；Secondly
0.5 μm of doping Mg concentration 1E19/cm of growth thickness3P-AlxGa1-xN cladding layer,
x=0.15；0.1 μm of doping Mg concentration 1E19/cm of regrowth thickness3P-GaN electrode
Contact layer.Semiconductor epitaxial crystal piece will be obtained, this optoelectronic semiconductor after completing
Epitaxy junction chip is also referred to as semiconductor wafer, semiconductor wafer is cut into fritter and can get
Semiconductor chip for semiconductor devices.Pass through series of process again by semiconductor chip
Make semiconductor devices.
Embodiment 2：
As shown in figure 4, it is with embodiment 1 difference, first buffer layer 21 is one
Thickness degree is 0.11 μm of doping Si concentration is 5E18/cm3AlGaN layer, in AlGaN
On layer, growth a layer thickness is 0.18 μm of Si concentration of adulterating for 5E18/cm3GaN layer
Regrowth second buffer layer 22 afterwards, other guide, with embodiment 1, is not stated tired.
Embodiment 3：
As shown in figure 5, it is with embodiment 1 difference, first buffer layer 21 is one
Thickness degree is 0.15 μm of doping Si concentration is 5E18/cm3N-GaN layer and be grown in
On n-GaN layer, thickness is 0.1 μm of Si concentration of adulterating for 5E18/cm3N-AlGaN layer,
The GaN/AlGaN of this two-layer closes layer, and in AlGaN layer, growth a layer thickness is 0.2 μm
Doping Si concentration is 5E18/cm3GaN layer after regrowth second buffer layer 22, other
Content, with embodiment 1, is not stated tired.In addition first buffer layer 21 can be in this embodiment
On the basis of 3, individual layer GaN/AlGaN conjunction layer is changed into multilayer GaN/AlGaN and closes stacking
Plus cushion.
Embodiment 4：
As shown in fig. 6, it is, second buffer layer 22 exists with embodiment 1 difference
In AlGaN layer, growth GaN/InAlGaN closes layer or multilayer GaN/InAlGaN closes layer；
InAlGaN layer is grown on GaN layer, this two-layer is referred to as GaN/InAlGaN and closes layer.And
And can have thickness different from embodiment 1, InAlGaN layer, AlGaN layer and GaN
The thickness of layer is respectively 0.1 μm, 0.3 μm and 0.6 μm.The same embodiment of other guide
1, do not state tired.
Embodiment 5：
As shown in fig. 7, with embodiment 1 difference, it is that substrate 1 adopts sapphire,
I.e. Al2O3, in Sapphire Substrate 1, growth a layer thickness is 0.1 μm of doping Si concentration
For 5E18/cm3GaN low temperature accumulation horizon, this low temperature accumulation horizon is grown to first buffer layer
21, first buffer layer 21 adopts Oxide chemical vapor sedimentation or epitaxial lateral excessive
Growth method grows into.Then growth thickness is 5E18/cm for 40nm doping Si concentration3's
n-AlxGa1-xN layer, in this example, x=0.08；Regrowth growth thickness is mixed for 0.3 μm
Miscellaneous Si concentration is 5E18/cm3N-GaN layer.
Or as shown in figure 8, growth a layer thickness is 0.1 μm in Sapphire Substrate 1
Doping Si concentration is 5E18/cm3N-AlN low temperature accumulation horizon and thickness mix for 0.1nm
Miscellaneous Si concentration is 5E18/cm3N-GaN layer, this low temperature accumulation horizon be grown to first delay
Rush layer 21, then growth thickness is 5E18/cm for 60nm doping Si concentration3's
n-AlxGa1-xN layer, in this example, x=0.09；Regrowth thick layer is 0.3 μm of doping
Si concentration is 5E18/cm3N-GaN layer.
Or further, first buffer layer 21 can also be improved to first buffer layer 21
GaN/AlN for GaN low temperature accumulation horizon and AlN this two-layer of layer closes layer, or first is slow
Rush layer 21 and close layer for multilayer GaN/AlN.
In the case that sapphire is as substrate 1, second buffer layer 22 is GaN layer and life
Long InAlGaN layer in GaN layer, this two-layer is referred to as GaN/InAlGaN and closes layer；Or
Person's second buffer layer is that multilayer GaN/InAlGaN closes the cushion that layer is formed by stacking.Other
Content, with embodiment 1, is not stated tired.
Embodiment 6：
Group Ⅱ-Ⅵ compound semiconductor device, with SiC as substrate, extension life on substrate
Long thick layer is 0.3 μm of doping Si concentration is 5E18/cm3ZnO low temperature accumulation horizon,
Thick layer is 0.1 μm of doping Si concentration is 5E18/cm3SiC layer and thick layer be 0.2
μm doping Si concentration be 5E18/cm3GaN layer become cushion, or on substrate
Growth thick layer is 0.3 μm of doping Si concentration is 5E18/cm3Ga2O3Layer becomes slow
Rush layer.
Claims (5)
1. semiconductor devices, including substrate and action layer, described substrate forms III group-III nitride
The action layer of semiconductor, described III group-III nitride semiconductor refers to containing GaN, InN or AlN one
Plant or mixed crystal compound semiconductor that is several and being formed, growth over the substrate is provided with n-type electrode
N-type semiconductor and growth have the p-type semiconductor being provided with p-type electrode it is characterised in that in described lining
Between bottom and action layer, growth has cushion；Described cushion includes first buffer layer and is grown in the
Second buffer layer on one cushion such that it is able to relax crystal defect because lattice mismatch leads to and
Spontaneous polarization and piezoelectric polarization and the generation of internal electric field that causes；Second buffer layer be containing
The GaN/InAlGaN/AlGaN composite bed of InAlGaN layer, GaN/InAlGaN/AlGaN composite bed refers to
GaN layer grows InAlGaN layer, growth on InAlGaN layer has AlGaN layer；Or containing upper
The sandwich construction stating GaN/InAlGaN/AlGaN composite bed is as second buffer layer.
2. semiconductor devices according to claim 1 is it is characterised in that lead on described substrate
Crossing chemical vapour deposition technique growth has GaN low temperature depositing layer or AlGaN layer or AlN layer to be formed
First buffer layer；Or described Grown has GaN low temperature depositing layer, AlGaN layer or AlN
In layer, two-layer or hybrid multilayer form first buffer layer；Or epitaxial lateral mistake is passed through on described substrate
Degree growth method growth have in GaN layer, AlGaN layer or AlN layer one or more layers and formed first
Cushion.
3. semiconductor devices according to claim 1 is it is characterised in that described second buffers
Layer in InAlGaN be：InxAlyGazN, 0.05<x<0.11, y=4.66x, z=1-x-y.
4. the semiconductor devices according to claim 1 or 2 or 3 is it is characterised in that described
The surface roughness that substrate is used for growing extension is limited to below 15nm.
5. semiconductor devices according to claim 4 is it is characterised in that described substrate is single
Brilliant Al2O3, monocrystal SiC, monocrystalline GaN, monocrystalline Ga2O3, single crystal ZnO, monocrystalline GaAs, monocrystalline
InP or single crystalline Si；Or above-mentioned material forms integration on its polycrystalline with reference to its monocrystalline
Substrate；Or above-mentioned material forms the substrate of integration on it is noncrystalline with reference to its monocrystalline.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1706033A (en) * | 2002-10-15 | 2005-12-07 | 住友化学株式会社 | Production method for thin-film crystal wafer, semiconductor device using it and production method therefor |
| CN1868070A (en) * | 2003-10-14 | 2006-11-22 | 昭和电工株式会社 | Group-III nitride semiconductor device |
| CN1937246A (en) * | 2006-10-16 | 2007-03-28 | 中国电子科技集团公司第五十五研究所 | Composite buffer layer nitride high electronic migration rate transmistor epitaxial structure and its manufacturing method |
| CN101410992A (en) * | 2006-03-31 | 2009-04-15 | 昭和电工株式会社 | GaN semiconductor light emitting element and lamp |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4304984B2 (en) * | 2003-01-07 | 2009-07-29 | 日亜化学工業株式会社 | Nitride semiconductor growth substrate and nitride semiconductor device using the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1706033A (en) * | 2002-10-15 | 2005-12-07 | 住友化学株式会社 | Production method for thin-film crystal wafer, semiconductor device using it and production method therefor |
| CN1868070A (en) * | 2003-10-14 | 2006-11-22 | 昭和电工株式会社 | Group-III nitride semiconductor device |
| CN101410992A (en) * | 2006-03-31 | 2009-04-15 | 昭和电工株式会社 | GaN semiconductor light emitting element and lamp |
| CN1937246A (en) * | 2006-10-16 | 2007-03-28 | 中国电子科技集团公司第五十五研究所 | Composite buffer layer nitride high electronic migration rate transmistor epitaxial structure and its manufacturing method |
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