CN103269222A - Achieving method and device of variable code element rate vector signal - Google Patents

Abstract

The invention discloses an achieving method and device of a variable code element rate vector signal. The method comprises the steps of carrying out modulation mapping processing on a received signal, and obtaining an I modulating signal and a Q modulating signal; carrying out forming filtering processing and sigma-delta modulating conversion on each modulating signal, and obtaining code element rates of output signals; carrying out digital filtering on each modulating signal, and further eliminating interference between the code element rates and digitized mantissa modulating interference brought by decimal conversion; then, carrying out digital modulation on the I modulating signal and the Q modulating signal after the digital filtering to obtain a modulating signal, carrying out D/A conversion on the modulating signal after the digital modulation, and obtaining an analog signal; finally, mixing the analog signal to an expected frequency point. Due to the sigma-delta modulation conversion, the code element rates with various modulation forms, high resolution and large ranges can be rapidly obtained, and vector modulating signals can be offered to development and productive maintenance of communication devices, chips and terminals.

Description

Implementation method and the device of variable symbol rate vector signal

Technical field

The present invention relates to communication technical field, relate in particular to a kind of implementation method and device of variable symbol rate vector signal.

Background technology

In order to comply with the demand of development in science and technology, the digital modulation signals source is proposed by people, and it is fully integrated numeral, vector, analog-modulated function in a signal source first.For various digital standard and various numeral modulation provide comprehensive modulation capability.Existing digital modulation signals method mainly realizes by a binary channels random wave generator, guarantee that by the calculating of utilization interpolate value with by Sampling techniques waveform is accurate simultaneously, and satisfy the test request of wireless digital communication system now by the mode storing sample of dark storage depth.Realize that at present variable symbol rate vector signal mainly is to realize by the clock of D/A converter.

But realize also synchronous change of clock that variable symbol speed needs the postorder processing module by the clock of D/A converter, and time delay is difficult to control between the module, becomes present problem demanding prompt solution so how to realize a kind of simple and controlled change bit rate vector signal.

Summary of the invention

In view of above-mentioned analysis, the present invention aims to provide a kind of implementation method and device of variable symbol rate vector signal, has effectively avoided adopting the also problem of synchronous change of clock that the clock of D/A converter realizes that variable symbol speed needs the postorder processing module.

Purpose of the present invention mainly is achieved through the following technical solutions:

A kind of implementation method of variable symbol rate vector signal comprises:

The signal that receives is modulated mapping handle, obtain I, Q two-way modulation signal;

Every road modulation signal is formed filtering respectively handle, eliminate the interference between the chip rate of each road modulation signal;

Each road modulation signal after the shaping filter processing is carried out the sigma-delta modulating transformation, obtain the output signal of predetermined chip rate;

The output signal of the predetermined chip rate that obtains is carried out digital filtering, further eliminate the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

Described I road behind the digital filtering and described Q road modulation signal are carried out the numeral modulation obtain one road modulation signal, and road modulation signal after the numeral modulation is carried out the D/A conversion, obtain one tunnel analog signal;

This analog signal is mixed on the expection frequency.

Preferably, each the road modulation signal after the shaping filter processing is carried out the sigma-delta modulating transformation, the step that obtains the output signal of predetermined chip rate specifically comprises:

Each road modulation signal after the shaping filter processing is carried out integer insert processing and decimal insertion processing, the output signal of the chip rate that obtains being scheduled to.

Preferably, each the road modulation signal after shaping filter handled carries out integer and inserts and handle and decimal inserts and handles, and the step that obtains being scheduled to the output signal of chip rate specifically comprises:

If the integer part of insertion rate is N, fractional part is .F;

Every road insertion rate is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm], wherein [] is for keeping the implication of integer part;

Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

Preferably, the described signal that receives comprises noise sequence, standard code data or User Defined data.

The present invention is a kind of implement device of variable symbol rate vector signal also, comprising:

The IQ modulating unit is used for the signal that receives is modulated mapping, obtains I, Q two-way modulation signal;

The shaping filter unit is used for that described I road and described Q road modulation signal are formed filtering respectively and handles, and eliminates the interference between the chip rate of each road modulation signal;

Variable insertion unit is used for the sigma-delta modulating transformation is carried out on the described I road after the described shaping filter cell processing and described Q road modulation signal respectively, obtains the output signal of predetermined chip rate;

The digital filtering unit is used for the output signal of the predetermined chip rate that obtains after the described variable insertion cell processing is carried out digital filtering, further eliminates the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

The numeral modulating unit is used for that the described I road after the described digital filtering cell processing and described Q road modulation signal are carried out numeral and modulates and obtain one road modulation signal;

The D/A converter unit is used for the road modulation signal that described digital modulating unit is handled after numeral is modulated is carried out the D/A conversion, obtains one tunnel analog signal, and this analog signal is mixed on the expection frequency.

Preferably, described variable insertion unit specifically is used for, and each the road modulation signal after shaping filter is handled carries out integer and inserts processing and decimal insertion processing, obtains the output signal of predetermined chip rate.

Preferably, described variable insertion unit specifically is used for, and the integer part of establishing the insertion rate is N, and fractional part is .F;

Every road insertion rate is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm], wherein [] is for keeping the implication of integer part;

Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

Preferably, the described signal that receives comprises noise sequence, standard code data or User Defined data.

Beneficial effect of the present invention is as follows:

The present invention has carried a kind of implementation method and device of variable symbol rate vector signal, can obtain the insertion rate fast by the sigma-delta modulating transformation, further obtain output signal, and this kind modulation can obtain multiple modulation format, the large-scale chip rate of high-resolution, and can be the research and development of communication equipment, chip, terminal and producing maintenance provides the Vector Modulation signal.

Other features and advantages of the present invention will be set forth in the following description, and becoming apparent from specification of part perhaps understood by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of writing, claims and accompanying drawing.

Description of drawings

Fig. 1 is the flow chart of the implementation method of variable symbol rate vector signal in the embodiment of the invention 1;

Fig. 2 is sigma-delta modulating transformation figure in the embodiment of the invention 1;

Fig. 3 hints obliquely at for orthogonal PSK (QPSK) modulation format planisphere in the embodiment of the invention 1;

Fig. 4 hints obliquely at for 8 system phase shift keyings (8PSK) modulation format planisphere in the embodiment of the invention 1;

Fig. 5 hints obliquely at for 16 ary quadrature amplitude keying (16QAM) modulation format planispheres in the embodiment of the invention 1;

Fig. 6 is the implement device schematic diagram of variable symbol rate vector signal in the embodiment of the invention 2.

Embodiment

Specifically describe the preferred embodiments of the present invention below in conjunction with accompanying drawing, wherein, accompanying drawing constitutes the application's part, and is used from explaination principle of the present invention with embodiments of the invention one.

Embodiment 1

The embodiment of the invention provides a kind of implementation method of variable symbol rate vector signal, referring to Fig. 1, comprising: S101, the signal that receives is modulated mapping handle, obtain I, Q two-way modulation signal;

The signal that receives described in the embodiment of the invention comprises noise sequence, standard code data or User Defined data.

S102, every road modulation signal is formed filtering respectively handle, eliminate the interference between the chip rate of each road modulation signal;

S103, each the road modulation signal after shaping filter handled carry out the sigma-delta modulating transformation, obtain the chip rate of output signal;

Wherein, the shaping filter in the embodiment of the invention is treated to FIR(Finite Impulse Response, and limit for length's unit impulse response is arranged) shaping filter handles to eliminate intersymbol interference and digitlization mantissa modulated interferer;

In the embodiment of the invention each the road modulation signal after the shaping filter processing is carried out integer and insert processing and decimal insertion processing, obtain integer part and the fractional part of the chip rate of output signal, as shown in Figure 2, wherein this step specifically comprises:

If the integer part of the chip rate of output signal is N, fractional part is .F;

Insertion rate to every road modulation signal is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N _Div], wherein [] is for keeping the implication of integer part;

Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

S104, every road modulation signal is carried out digital filtering, further eliminate the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

S105, the described I road behind the digital filtering and described Q road modulation signal are carried out the numeral modulation obtain one road modulation signal, and road modulation signal after the numeral modulation is carried out the D/A conversion, obtain one tunnel analog signal;

Because modulation mapping processing, shaping filter processing and digital filtering and data modulated process are the known technology of this area, the present invention does not do improvement at receiver side to these contents, so locate not describe in detail.

S106, with this analog signal be mixed to the expection frequency on.

The embodiment of the invention can obtain output signal data speed and chip rate ratio fast by the sigma-delta modulating transformation, namely obtain integer part and the fractional part of insertion rate, and this kind modulation can obtain multiple modulation format, the large-scale chip rate of high-resolution, and can be the research and development of communication equipment, chip, terminal and producing maintenance provides the Vector Modulation signal.

It is the reference point planisphere of QPSK, 8QPSK and 16QAM among Fig. 3-5.Corresponding one of two bits that are modulated to of QPSK are answered real number, and I is real, and Q is the imaginary part of plural number.In when test, the planisphere that receives signal respectively with the distributional class of Fig. 3-5 seemingly.The signal quality of implementation method of variable symbol rate vector signal that is the embodiment of the invention is higher.

Embodiment 2

The embodiment of the invention is in the vector signal source of multiple standards, multiple modulation format, chip rate variation on a large scale, solution is fully integrated numeral, vector, analog-modulated function in a signal source, comprehensive modulation capability is provided, comprise various digital standard WCDMA, CMDA2000, TD-SCDMA etc., various numeral modulation FSK, PSK, QAM etc.Satisfy the test request of wireless digital communication system now.Explanation a kind of high accuracy, high-resolution variable chip rate vector signal method for generation and device among this embodiment.To comprise 10 modules: data flow generation module, IQ modulation is hinted obliquely at, FIR shaping filter module, integer insert module, decimal insert module, digital filtering module, numeral modulation, D/A conversion module, up-conversion module and sigma-delta modulating transformation module.The present invention carries out the IQ modulation with data flow according to modulation format earlier and hints obliquely at; FIR filter shaping filter then; The process integral multiple inserts again, utilizes sigma-delta modulating transformation unit controls decimal insertion unit to finish decimal and doubly inserts function, makes the chip rate that vector signal takes place need not to link up with the clock of D/A conversion, just can realize high accuracy, high-resolution; Through the digital filtering unit, eliminate the digitlization mantissa modulation that the sigma-delta modulating transformation brings, give digital modulation module at last, modulate the signal on the carrier wave, by the D/A conversion that modulation signal is simulated, upconvert to radio frequency output again.This contrive equipment provides the digital modulation signals authentication of Vector Modulation signal, certification authority, the occasions such as test of communication device when mainly applying to research and development such as communication equipment, chip, terminal, production and maintenance.Specifically carry out as follows:

(1) apparatus of the present invention produce PN sequence, standard code data or User Defined data earlier by data flow generation module;

(2) IQ modulation is hinted obliquely at module and is carried out data according to modulation format and hint obliquely at, and forms IQ two-way modulation signal;

(3) through FIR molding filtration module IQ two-way modulation signal is carried out the FIR molding filtration, eliminate between data chips and disturb;

(4) carrying out integral multiple by the integer insert module earlier according to the requirement of the chip rate of output signal inserts;

(5) pass through the clock rate that the decimal insert module is adjusted into the speed of output signal output the D/A conversion again;

(6) sigma-delta modulating transformation unit purpose control decimal insert module realizes that I circuit-switched data stream Idata, Q circuit-switched data stream Qdata resample, and reach the 5th step purpose.

The concrete model of sigma-delta modulating transformation unit has adopted m stable single order loop to constitute the cascade form, integer part N and the fractional part .F of the insertion rate of input expection, E as shown in Figure 2 _qIt is quantizing noise.The transfer function of integrator is 1/ (1-Z ^-1), the transfer function of differentiator is 1-Z ^-1, Z is the Laplace variable in the discrete time-domain, and integrator uses accumulator to finish, and full amount is overflowed as its output, and this process is a modulo operation, feedback quantity is a time delay Z of unit ^-1, the loop relation is as follows:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Output insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm] _Round

The I circuit-switched data flows I like this _Data, Q circuit-switched data stream Q _DataThrough forming new I circuit-switched data stream I after the decimal insert module _Newdata, Q circuit-switched data stream Q _Newdata

(7) pass through the FIR digital filtering module again, eliminate the digitlization mantissa modulation that intersymbol interference and sigma-delta modulating transformation bring, factors such as frequency response in the band, the interior ripple of band, the outer inhibition of band are mainly considered in the Finite Impulse Response filter design, guarantee the analysis quality of signal, eliminate the digitlization mantissa modulation that the sigma-delta modulating transformation brings simultaneously.

(8) digital modulation module produces modulation signal according to following formula;

S _data=I _newdata*A*sin2πf _ct+Q _newdata*A*cos2πf _ct；

Wherein A is carrier amplitude, f _cBe carrier frequency, t is the sampling time, S _DataModulation signal for the digital modulation module generation;

(9) convert IQ numeral digital modulation signals to analog signal by the D/A conversion module, signal(-) carrier frequency is f _c, D/A conversion module clock f wherein _A/DBe signal(-) carrier frequency f _cIntegral multiple;

(10) by the up-conversion module signal is mixed on the Frequency point of expection needs, produces the Vector Modulation signal like this and satisfy the demand that real work is carried out.

Embodiment 3

The embodiment of the invention provides a kind of implement device of variable symbol rate vector signal, referring to Fig. 6, comprising:

The IQ modulating unit is used for the signal that receives is modulated mapping, obtains I, Q two-way modulation signal;

The shaping filter unit is used for that described I road and described Q road modulation signal are formed filtering respectively and handles, and eliminates the interference between the chip rate of each road modulation signal;

Variable insertion unit is used for the sigma-delta modulating transformation is carried out on the described I road after the described shaping filter cell processing and described Q road modulation signal respectively, obtains the output signal of predetermined chip rate;

The digital filtering unit is used for the output signal of the predetermined chip rate that obtains after the described variable insertion cell processing is carried out digital filtering, further eliminates the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

The numeral modulating unit is used for that the described I road after the described digital filtering cell processing and described Q road modulation signal are carried out numeral and modulates and obtain one road modulation signal;

The D/A converter unit is used for the road modulation signal that described digital modulating unit is handled after numeral is modulated is carried out the D/A conversion, obtains one tunnel analog signal, and this analog signal is mixed on the expection frequency.

Wherein, described variable insertion unit specifically is used for, and the integer part of establishing the chip rate of output signal is N, and fractional part is .F;

Insertion rate to every road modulation signal is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm], wherein [] is for keeping the implication of integer part; Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

In sum, the embodiment of the invention has been carried a kind of implementation method and device of variable symbol rate vector signal, can obtain the data rate and chip rate ratio of output signal fast by the sigma-delta modulating transformation, namely obtain integer part and the fractional part of insertion rate, and this kind modulation can obtain multiple modulation format, the large-scale chip rate of high-resolution, and can be the research and development of communication equipment, chip, terminal and producing maintenance provides the Vector Modulation signal.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims (8)

1. the implementation method of a variable symbol rate vector signal is characterized in that, comprising:

The signal that receives is modulated mapping handle, obtain I, Q two-way modulation signal;

Every road modulation signal is formed filtering respectively handle, eliminate the interference between the chip rate of each road modulation signal;

Each road modulation signal after the shaping filter processing is carried out the sigma-delta modulating transformation, obtain the output signal of predetermined chip rate;

The output signal of the predetermined chip rate that obtains is carried out digital filtering, further eliminate the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

Described I road behind the digital filtering and described Q road modulation signal are carried out the numeral modulation obtain one road modulation signal, and road modulation signal after the numeral modulation is carried out the D/A conversion, obtain one tunnel analog signal;

This analog signal is mixed on the expection frequency.

2. method according to claim 1 is characterized in that, each the road modulation signal after shaping filter is handled carries out the sigma-delta modulating transformation, and the step that obtains the output signal of predetermined chip rate specifically comprises:

Each road modulation signal after the shaping filter processing is carried out integer insert processing and decimal insertion processing, the output signal of the chip rate that obtains being scheduled to.

3. method according to claim 2 is characterized in that, each the road modulation signal after shaping filter is handled carries out integer and inserts processing and decimal insertion processing, and the step that obtains the output signal of predetermined chip rate specifically comprises:

If the integer part of insertion rate is N, fractional part is .F;

Every road insertion rate is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E _q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm], wherein [] is for keeping the implication of integer part;

Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

4. according to any described method of claim 1-3, it is characterized in that the described signal that receives comprises noise sequence, standard code data or User Defined data.

5. the implement device of a variable symbol rate vector signal is characterized in that, comprising:

The IQ modulating unit is used for the signal that receives is modulated mapping, obtains I, Q two-way modulation signal;

The shaping filter unit is used for that described I road and described Q road modulation signal are formed filtering respectively and handles, and eliminates the interference between the chip rate of each road modulation signal;

Variable insertion unit is used for the sigma-delta modulating transformation is carried out on the described I road after the described shaping filter cell processing and described Q road modulation signal respectively, obtains the output signal of predetermined chip rate;

The digital filtering unit is used for the output signal of the predetermined chip rate that obtains after the described variable insertion cell processing is carried out digital filtering, further eliminates the digitlization mantissa modulated interferer that interference between chip rate and little transformation of variables bring;

The numeral modulating unit is used for that the described I road after the described digital filtering cell processing and described Q road modulation signal are carried out numeral and modulates and obtain one road modulation signal;

The D/A converter unit is used for the road modulation signal that described digital modulating unit is handled after numeral is modulated is carried out the D/A conversion, obtains one tunnel analog signal, and this analog signal is mixed on the expection frequency.

6. device according to claim 5 is characterized in that,

Described variable insertion unit specifically is used for, and each the road modulation signal after shaping filter is handled carries out integer and inserts processing and decimal insertion processing, obtains the output signal of predetermined chip rate.

7. device according to claim 6 is characterized in that,

Described variable insertion unit specifically is used for, and the integer part of establishing the insertion rate is N, and fractional part is .F;

Every road insertion rate is carried out following calculating respectively:

N ₁(Z)=.F(Z)+(1-Z ^-1)E _q1(Z)；

N ₂(Z)=-E ^q1(Z)+(1-Z ^-1)E _q2(Z)；

……

N _m(Z)=-E _qm-1(Z)+(1-Z ^-1)E _qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N _OutFor: N _Out=[N.F (Z)+(1-Z ^-1) ^mE _Qm], wherein [] is for keeping the implication of integer part;

Wherein, Z is Laplce's variable, E _Q1-E _QmBe the quantizing noise signal, m=1,2,3,4 or 5.

8. according to any described device of claim 5-7, it is characterized in that the described signal that receives comprises noise sequence, standard code data or User Defined data.

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