CN103268889B - A kind of without the horizontal tunneling field-effect transistor of knot type - Google Patents
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Abstract
The present invention proposes a kind of without the horizontal tunneling field-effect transistor of knot type, comprise: source region, drain region, channel region, control grid and auxiliary grid, wherein, source region, drain region and channel region form an entirety, adopting same doping type semiconductor material, identical to raceway groove to drain region doping content from source region, control grid and auxiliary grid are positioned at the same side of raceway groove, wherein control grid is used for conducting and the closedown of control device, and auxiliary grid are for making the semiconductor regions generation transoid of the lower section of auxiliary grid. Being different from without the horizontal tunneling field-effect transistor of knot type of the embodiment of the present invention traditional has PN junction tunneling field-effect transistor device, and the present invention is a kind of doping type only, it is not necessary to makes PN knot, reduces technology difficulty; Device of the present invention is more conducive to reducing of device size, suppresses short-channel effect, increases switch current ratio, improves sub-threshold slope.
Description
Technical field
The invention belongs to technical field of semiconductors, it is specifically related to a kind of without the horizontal tunneling field-effect transistor of knot type.
Background technology
It is well known that metal oxide semiconductor field effect transistor (MOSFET) (MOSFET) is the basic unit in modern electronics, transistors all at present all has semiconducter junction, such as PN knot, heterojunction, schottky junction. Specifically, the most common PN homojunction engages the N-type doped region of excess electrons with having by the P type doped region having excessive hole on same semiconductor material, the PN knot that heterojunction (Hetero-junction) is made up of two kinds of different semiconductor materials, schottky junction (Schottkyjunction) is then made up of metal and semiconductor contact.
Typically, traditional MOSFET element comprises a source-channel junction, a leakage-channel junction and a grid stacking (comprising gate medium and gate electrode), and the stacking effect of grid is that control is from source region to the electric current in drain region. Such as, a N-type channel device has N-P-N structure, and grid are stacking to be positioned at above territory, p type island region; A P-type channel device has a P-N-P structure, and grid are stacking is positioned at N-type overlying regions. The past 50 for many years, the development of silicon base MOSFET follows Moore's Law, and the lifting of its performance is obtained by constantly reducing of characteristic dimension. Along with technology node enters into nanoscale, the challenge of a series of key needs to solve. Wherein, the most outstanding is to be reduced short-channel effect, increase ON state current and reduce power dissipation. For this reason, academia and industry member introduce many improvement opportunity, are commonly referred to technology thruster.
Such as, in order to reduce voltage of supply and sub-threshold slope, make sub-threshold slope break through this limit of conventional MOS FET device 60mV/decade, there has been proposed tunneling field-effect transistor (TunnelFieldEffectTransistor, TFET), its structure is based on grid-control P-I-N structure. As shown in Figure 1, it is respectively typical N-type and the structural representation of P type TFET, as seen from the figure, with common MOSFET the difference is that, for N-type TFET, its source region is P type heavy doping, and channel region is intrinsic doping or the doping of weak N-type, drain region is still N-type heavy doping, P type TFET then contrast. Visible, the doping type in TFET device source region and drain region is contrary, and type is identical basic difference for this point and conventional MOS FET source district and drain region doping.
Currently, along with constantly reducing of device feature size enters into 22nm technology for, time following, traditional MOSFET and TFET device all requires to form super steep doping shape looks between source, drain region and raceway groove. In order to overcome this difficult problem, there has been proposed a kind of without junction type field effect transistor (JunctionlessFieldEffectTransistor, JLFET). This transistor characteristic feature is that source, leakage and raceway groove have identical doping type and doping content, does not exist " knot " at channel direction. As shown in Figure 2, sets forth the structure iron of n type without knot type JLFET and p-type JLFET, the doping type in its source, raceway groove, drain region can be configured to N+-N+-N+Or P+-P+-P+, and doping content is identical.
Owing to there is the current-voltage characteristic of approximate ideal, excellent scaled down ability and extremely simple manufacturing process without junction type field effect transistor, it it is a hot fields of device research over the past two years. But, along with people are for the urgent needs of super low-power consumption device, the sub-threshold slope theoretical limit without junction type field effect transistor is still 60mV/decade, limits the reduction of voltage of supply.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or at least provides a kind of useful business to select. For this reason, it is an object of the invention to propose a kind of to be conducive to reducing of device size, suppress short-channel effect, increase switch current ratio, improve sub-threshold slope without knot type transverse direction tunneling field-effect transistor.
According to embodiments of the present invention without the horizontal tunneling field-effect transistor (JunctionlessHorizontalVerticalFieldEffectTransistor of knot type, JLHTFET), comprise: source region, drain region, channel region, control grid and auxiliary grid, wherein, described source region, drain region and channel region form an entirety, adopt same doping type semiconductor material, identical to raceway groove to drain region doping content from source region, described control grid and auxiliary grid are positioned at the same side of described raceway groove, wherein said control grid is used for conducting and the closedown of control device, described auxiliary grid are for making the semiconductor regions generation transoid of the lower section of described auxiliary grid.
In one embodiment of the invention, being longitudinally distributed to of the doping content that the entirety that described source region, drain region and channel region are formed extends in body along grid lower semiconductor surface is uniformly distributed, Gaussian distribution or stepped profile.
In one embodiment of the invention, described control grid is identical with the work function of the electrode of described auxiliary grid or not identical.
In one embodiment of the invention, distance between described control grid and described auxiliary grid is Liso, described Liso��0nm��
In one embodiment of the invention, the material of the gate medium of described control grid and described auxiliary grid is SiO2��Si3N4��HfO2��TiO2��La2O3��Al2O3In one or more combination.
In one embodiment of the invention, the semiconductor material of described source region, drain region and channel region is IV race semi-conductor, Group III-V compound semiconductor, carbon nanotube, Graphene or Mo2One or more combination in S.
In one embodiment of the invention, the described grid structure without the horizontal tunneling field-effect transistor of knot type is single grid structure, double-gate structure, three grid structures or surrounds grid structure.
In sum, being different from without the horizontal tunneling field-effect transistor of knot type of the embodiment of the present invention traditional has PN junction TFET device, and this device is a kind of doping type only, it is not necessary to makes PN knot, reduces technology difficulty; Device of the present invention is more conducive to reducing of device size, suppresses short-channel effect, increases switch current ratio, improves sub-threshold slope.
The additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by the practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage from accompanying drawing below combining to the description of embodiment becoming obviously and it should be readily understood that wherein:
Fig. 1 is n type and p-type tunneling field-effect transistor (TFET) structural representation of prior art;
Fig. 2 is that the n type of prior art and p-type are without junction type field effect transistor (JLFET) structural representation;
Fig. 3 is that the n type of the embodiment of the present invention and p-type are without horizontal tunneling field-effect transistor (JLHTFET) structural representation of knot type;
Fig. 4 is the energy band diagram during n type of embodiment of the present invention tunneling field-effect transistor closing condition horizontal without knot type;
Fig. 5 is the energy band diagram during n type of embodiment of the present invention tunneling field-effect transistor opened condition horizontal without knot type;
Fig. 6 be the embodiment of the present invention without the horizontal tunneling field-effect transistor of knot type genesis analysis of doping content in Si film in soi structure;
Fig. 7 is the genesis analysis without the horizontal tunneling field-effect transistor doping content in SiFin or nano wire of knot type of the embodiment of the present invention.
Embodiment
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish. It is exemplary below by the embodiment being described with reference to the drawings, it is intended to for explaining the present invention, and limitation of the present invention can not be interpreted as.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", it is based on orientation shown in the drawings or position relation that the orientation of the instruction such as " counterclockwise " or position are closed, it is only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device referred to or element must have specific orientation, with specific orientation structure and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " the 2nd " are only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technology feature. Thus, be limited with " first ", the feature of " the 2nd " can express or implicit comprise one or more these features. In describing the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, it is possible to be fixedly connected with, it is also possible to be removably connect, or connects integratedly; Can be mechanically connected, it is also possible to be electrical connection; Can be directly be connected, it is also possible to be indirectly connected by intermediary, it is possible to be the connection of two element internals. For the ordinary skill in the art, it is possible to understand above-mentioned term concrete implication in the present invention according to particular case.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or D score can comprise the first and second features and directly contact, it is also possible to comprise the first and second features be not directly contact but by the other characterisation contact between them. And, fisrt feature second feature " on ", " top " and " above " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is higher than second feature. Fisrt feature second feature " under ", " lower section " and " below " comprise fisrt feature immediately below second feature and tiltedly lower section, or only represent that fisrt feature level height is less than second feature.
According to embodiments of the present invention without the horizontal tunneling field-effect transistor of knot type as shown in Figure 3, comprise: source region, drain region, channel region, control grid and auxiliary grid, wherein, source region, drain region and channel region form an entirety, adopt same doping type semiconductor material, identical to raceway groove to drain region doping content from source region, control grid and auxiliary grid are positioned at the same side of described raceway groove, wherein control grid is used for conducting and the closedown of control device, and auxiliary grid are for making the semiconductor regions generation transoid of the lower section of auxiliary grid. Noticing, in n type and p-type are without the horizontal tunneling field-effect transistor of knot type, the naming method of auxiliary grid, is pgate and ngate, it is intended that emphasize N respectively+And P+There is transoid in region.
In one embodiment of the invention, being longitudinally distributed to of the doping content that the entirety that source region, drain region and channel region are formed extends in body along grid lower semiconductor surface is uniformly distributed, Gaussian distribution or stepped profile.
In one embodiment of the invention, control grid is identical with the work function of the electrode of auxiliary grid or not identical. In order to obtain suitable threshold voltage, the work function without junction type field effect transistor device gate material needs special consideration. Such as, if Si is as raceway groove, for N-type JLFET, it is necessary to use grid material (the such as P of big work function+Polysilicon etc.), for P type JLFET, it is necessary to grid material (the such as N using work function less+Polysilicon etc.).
But, for the present invention without the horizontal tunneling field-effect transistor (JLHTFET) of knot type, on the one hand, the effect of control grid is conducting and the closedown of control transistor. Rough estimation, according to the maximum depletion layer width formula of MOS device��sFor the specific inductivity of semi-conductor,For the difference of gate electrode and the work function of semi-conductor, N is the impurity doping concentration of semi-conductor. Such as, equally for Si as channel material, the electron affinity of Si is 4.05eV, and raceway groove is N-type doping, and impurity concentration is about 4 �� 1019cm-3, gate electrode work function is 5.05eV, it is possible to calculate W=6nm; In other words, if in order to make 6nm raceway groove occur all to exhaust, the difference of the work function of gate work-function and Si must be greater than 1eV, and so the work function of gate electrode can be chosen as 5.1eV, material can be P+The material such as polysilicon or Pd, like this, when the applying bias of control grid is 0V (closing condition), transistor is in closedown, it does not have electric current passes through. On the other hand, for same condition, and assist the semiconductor regions generation transoid of the lower section making auxiliary grid during the effect of grid, so, it is possible to have two kinds of ways, one is the work function of auxiliary grid and the same of control grid, and it being applied with a negative bias voltage (such as ,-0.5V) simultaneously, another kind of way is the work function of auxiliary grid and the different of control grid, can electing 5.7eV as, material is Pt.
In one embodiment of the invention, the distance remembered between control grid and auxiliary grid is Liso, Liso>=0nm. The materials such as the material that the isolated material between control grid with auxiliary grid can adopt gate medium identical can also be conventional medium with low dielectric constant, the porous silicon of the silicon oxide of such as doping carbon, porous silicon or doping carbon.
In one embodiment of the invention, the material of the gate medium of control grid and auxiliary grid can be SiO2��Si3N4��HfO2�� TiO2��La2O3��Al2O3Deng the combination of one or more in high dielectric constant material.
In one embodiment of the invention, the semiconductor material of source region, drain region and channel region is IV race semi-conductor, Group III-V compound semiconductor, carbon nanotube, Graphene or Mo2One or more combination in the two dimension planar materials such as S.
In one embodiment of the invention, grid structure without the horizontal tunneling field-effect transistor of knot type be single grid structure, double-gate structure, three grid structures or encirclement grid structure. It should be noted that, single grid structure herein, double-gate structure, three grid structures or " grid " that surround in grid structure refer to pair of control grid and the combination of auxiliary grid, instead of single control grid or auxiliary grid, such as soi structure, control grid and auxiliary grid are positioned at the top of Si film, form single grid structure; For SiFIN structure, control grid and auxiliary grid coated Si FIN, form three grid structures; With reason, for Sinanowire structure, control grid and auxiliary grid coated Si FIN, form the encirclement grid structure of ring-type.
Below for n type JLHTFET, the principle of work without the horizontal tunneling field-effect transistor of knot type of the present invention is made detail by composition graphs 4 and Fig. 5. Assuming that semiconductor material be the thickness of Si, Si film is 6nm, the doping type of source and drain district and channel region is N-type, and doping content is 1 �� 1019cm-3, the electron affinity of Si is 4.05eV; Gate medium is HfO2, thickness is 3nm; The work function of auxiliary grid (pgate) is 5.9eV, and length is 15nm; The work function of control grid (cgate) is 5.3eV, and length is 15nm; The distance L of control grid and auxiliary gridisoFor 5nm. When device is in OFF state, all applying bias are 0V, so, due to the difference of grid and Si work function so that the N-type region territory transoid below auxiliary grid, namely defines the p type island region of a heavy doping, and below control grid, defining the region of a depletion region so that device turns off; Along with the voltage of control grid increases so that the region below control grid accumulates, material is thus formed a grid-control P-I-N structure, corresponding energy band diagram is as shown in Figure 4.
When device is in ON state, the bias voltage of auxiliary grid is 0V; Control grid is 1V; Source electrode is 0V, drains as 1V; Owing to control grid and drain electrode are applied with forward bias, make it possible to take to drop-down, below control grid the conduction band in Si region pull down to auxiliary grid below the valence band in Si region maintain an equal level and following time, just there occurs and take band tunnelling (band-to-bandtunneling) to, device is opened, and corresponding energy band diagram is as shown in Figure 5. It should be noted that, when device is in ON state, auxiliary grid can also apply negative pressure, such as-a 0.5V so that the Si region transoid below auxiliary grid obtains more severe, namely becomes the p type island region that is equal to very heavy doping. For the JLHTFET of p-type, the doping content of raceway groove is P type heavy doping, source ground, drain electrode voltage is negative voltage of supply, so, in order to realize raceway groove transoid, auxiliary grid need to apply positive voltage, and the control grid that work apply negative voltage, and raceway groove is accumulated.
In the present invention without in the middle of knot type tunneling transistor, source, leakage, channel region all adopt same doping type, identical to raceway groove to drain region doping content from source region, namely there is not PN knot along channel direction. It can be then multiple situation that source, leakage, channel region extend the genesis analysis of doping content from grid lower semiconductor surface in body. The first situation the simplest is for being uniformly distributed, and (for soi structure) as shown in the solid line in Fig. 6, that is the doping type of whole semiconductor structure is identical with concentration, and this kind of structural manufacturing process is simple. 2nd kind of situation is uneven distribution, such as the dotted line in Fig. 6 be Gaussian distribution or stepped profile (for soi structure) shown in long and short dash line. Because without knot type device when OFF state (grid voltage is 0V), rely on the work function official post of gate electrode and semiconductor channel to obtain raceway groove and it is in and exhausts completely, thus realize the closedown of device. But, when semiconductor channel is thicker, must by adopting higher work function difference that raceway groove just can be made to exhaust, namely the work function of gate electrode is higher, but from the character of metal or metal alloy material, their work function can not meet the requirement of device parameters design completely, and this brings huge difficulty just to the selection of gate electrode and preparation.
Adopting this kind of the present invention near gate medium surface high density, away from the non-uniform doping structure of gate medium surface lower concentration, for identical work function difference, equivalence is in the thickness reducing raceway groove widely, so that the electric leakage of transistor OFF state significantly reduces; Namely this kind of doping content lateral distribution is identical and even, and the identical but uneven doped structure of genesis analysis improves the on/off ratio of device drive current. For double-gate structure or encirclement grid structure (cross section along center), still can be designed to non-uniform Distribution as shown in phantom in fig. 7 from semiconductor surface to the dopant profiles in body, give two-way Gaussian distribution schematic diagram. Noticing, for based semiconductor Fin tri-grid structure, owing to the depth-width ratio (aspectratio) of Fin is much larger than 1, the contribution of electric current can be ignored by top grid substantially, is equal to double-gate structure roughly.
Realizing Axinlly nonuniform dopant profiles and can adopt conventional ion implantation technology, the Gaussian distribution of impurity can be provided by following formula:
In formula, NdFor dopant profiles, and it it is the function of y; NpFor the doping content at semiconductor surface place, �� is the standard deviation of Gaussian distribution. Such as, for soi structure, Si film thickness is 10nm, Si surface doping concentration NpIt is 1 �� 1019cm-3, when �� is 4, it is possible to the doping content calculating Si and insulation buried regions (BOX) interface is about 4.4 �� 1017cm-3; When �� is 3, it is possible to the doping content calculating Si and insulation buried regions (BOX) interface is about 3.9 �� 1016cm-3. By formula it may be seen that the numerical value of �� is more big, the deviation of genesis analysis is more little; �� numerical value is more little, and the deviation of genesis analysis is more big, is more conducive to the shutoff of device.
It is noted that the lateral distribution of the doping content for source region, channel region and drain region, in fact can also be form N+-N--N+Or P+-P--P+Etc. structure, it is intended that make device zero partially time, raceway groove depletion region increases, and is convenient to the selection of control grid work function, and is easy to the semiconductor regions generation transoid that makes below auxiliary grid. In order to facilitate for the purpose of device preparation, the lateral distribution of the doping content in the preferred source region of the present invention, channel region and drain region is identical situation.
In sum, being different from without the horizontal tunneling field-effect transistor of knot type of the embodiment of the present invention traditional has PN junction TFET device, and this device is a kind of doping type only, it is not necessary to makes PN knot, reduces technology difficulty; Device of the present invention is more conducive to reducing of device size, suppresses short-channel effect, increases switch current ratio, improves sub-threshold slope.
In the description of this specification sheets, at least one embodiment that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to be contained in the present invention in conjunction with concrete feature, structure, material or feature that this embodiment or example describe or example. In this manual, the schematic representation of above-mentioned term is not necessarily referred to identical embodiment or example. And, the concrete feature of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although above it has been shown and described that embodiments of the invention, it is understandable that, above-described embodiment is exemplary, can not being interpreted as limitation of the present invention, above-described embodiment can be changed when not departing from principle and the objective of the present invention, revises, replace and modification by the those of ordinary skill of this area within the scope of the invention.
Claims (5)
1. one kind without the horizontal tunneling field-effect transistor of knot type, it is characterised in that: comprising: source region, drain region, channel region, control grid and auxiliary grid,
Wherein, described source region, drain region and channel region form an entirety, adopt same doping type semiconductor material, identical to raceway groove to drain region doping content from source region,
Described control grid and auxiliary grid are positioned at the same side of described raceway groove, and wherein said control grid is used for conducting and the closedown of control device, and described auxiliary grid are for making the semiconductor regions generation transoid of the lower section of described auxiliary grid;
Described control grid is identical with the work function of the electrode of described auxiliary grid;
The entirety that described source region, drain region and channel region are formed is longitudinally distributed to Gaussian distribution or stepped profile along the surperficial doping content extended in body of grid lower semiconductor.
2. as claimed in claim 1 without the horizontal tunneling field-effect transistor of knot type, it is characterised in that, the distance between described control grid and described auxiliary grid is Liso, described Liso��0nm��
3. as claimed in claim 1 without the horizontal tunneling field-effect transistor of knot type, it is characterised in that, the material of the gate medium of described control grid and described auxiliary grid is SiO2��Si3N4��HfO2��TiO2��La2O3��Al2O3In one or more combination.
4. as claimed in claim 1 without the horizontal tunneling field-effect transistor of knot type, it is characterised in that, the semiconductor material of described source region, drain region and channel region is IV race semi-conductor, Group III-V compound semiconductor, carbon nanotube, Graphene or Mo2One or more combination in S.
5. as claimed in claim 1 without the horizontal tunneling field-effect transistor of knot type, it is characterised in that, the described grid structure without the horizontal tunneling field-effect transistor of knot type is single grid structure, double-gate structure, three grid structures or surrounds grid structure.
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| CN103606563B (en) * | 2013-10-22 | 2016-06-01 | 清华大学 | Without knot type tunneling field-effect transistor and forming method thereof |
| CN103545375B (en) * | 2013-10-29 | 2017-10-27 | 沈阳工业大学 | The discrete control type non-impurity-doped field-effect transistor of the nearly nearly drain-gate of source grid |
| CN103531592B (en) * | 2013-10-29 | 2016-11-23 | 沈阳工业大学 | Three gate control type nodeless mesh body pipes of high mobility low source and drain resistance |
| CN104282751B (en) * | 2013-11-20 | 2017-07-21 | 沈阳工业大学 | High integration high mobility source and drain grid auxiliary control type nodeless mesh body pipe |
| CN104282750B (en) * | 2013-11-20 | 2017-07-21 | 沈阳工业大学 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
| KR102374118B1 (en) * | 2014-10-31 | 2022-03-14 | 삼성전자주식회사 | Graphene layer, method of forming the same, device including graphene layer and method of manufacturing the device |
| CN104465775B (en) * | 2014-12-12 | 2018-01-05 | 西安邮电大学 | Double its manufacture method of drain region semiconductor devices and application based on trap generation mechanism |
| CN104465776B (en) * | 2014-12-12 | 2017-09-15 | 西安邮电大学 | A kind of its manufacture method of the semiconductor devices of double grid electrode and application |
| CN104485358B (en) * | 2014-12-12 | 2018-01-05 | 西安邮电大学 | A kind of its manufacture method of the semiconductor devices based on trap generation mechanism and application |
| EP3185301A1 (en) * | 2015-12-22 | 2017-06-28 | IMEC vzw | Multi-gate tunnel field-effect transistor (tfet) |
| WO2018014170A1 (en) * | 2016-07-19 | 2018-01-25 | 华为技术有限公司 | Tunnel field effect transistor, and manufacturing method thereof |
| KR101852424B1 (en) | 2016-10-07 | 2018-04-27 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | The method for enhancing the driving current of junctionless transistor |
| CN107342320B (en) * | 2017-07-18 | 2021-02-02 | 清华大学 | Junction-free tunneling field effect transistor and preparation method thereof |
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2013
- 2013-05-23 CN CN201310195830.XA patent/CN103268889B/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
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| "Junctionless Tunnel Field Effect Transistor";Bahniman Ghosh;《IEEE ELECTRON DEVICE LETTERS》;20130412;第34卷(第5期);第584-586页 * |
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