CN103268216A - Shared storage mechanism-based quasi-cyclic matrix serial multiplier - Google Patents

Abstract

The invention provides a shared storage mechanism-based quasi-cyclic matrix serial multiplier, which is used for realizing multiplication operation between a vector m and a quasi-cyclic matrix F in quasic-low-density parity-check (QC-LDPC) approximate low triangular coding. The multiplier comprises a generator polynomial lookup table, a u-bit time delay unit, u b-bit buffers, u b-bit binary multipliers, u b-bit binary adders and u b-bit shift registers, wherein the generator polynomial lookup table is used for pre-storing cyclic matrix generator polynomials in the matrix F; the u-bit time delay unit is used for storing data bits of the vector m in a sliding way; the u b-bit buffers are used for caching the generator polynomials; the u b-bit binary multipliers are used for performing scalar multiplication on the data bits of the vector m and the generator polynomials; the u b-bit binary adders are used for performing modulo-2 addition on products and contents of the shift registers; and the u b-bit shift registers are used for storing sums of which each is rotated left by one bit. The quasi-cyclic matrix serial multiplier has the advantages of low power consumption, simple structure, low memory consumption, low cost and the like.

Description

Based on the accurate circular matrix serial multiplier of sharing memory mechanism

Technical field

The present invention relates to field of channel coding, particularly the accurate circular matrix serial multiplier in a kind of QC-LDPC near lower triangular coding.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) sign indicating number is one of channel coding technology efficiently, and QC-LDPC(Quasic-LDPC, QC-LDPC) sign indicating number is a kind of special LDPC sign indicating number.Generator matrix G and the check matrix H of QC-LDPC sign indicating number all are the arrays that is made of circular matrix, have the characteristics of segmentation circulation, so be called as the QC-LDPC sign indicating number.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip fully.Usually, the first trip of circular matrix is called as its generator polynomial.

When adopting the near lower triangular coding method that the QC-LDPC sign indicating number is encoded, by the ranks exchange, check matrix H is transformed near lower triangular shape H _ALT, it is composed as follows by 6 sub-matrixes:

$H_{\mathrm{ALT}}=\left[\begin{array}{ccc}A& B& L\\ C& D& E\end{array}\right]---\left(1\right)$

Wherein, L is lower triangular matrix.H _ALTCorresponding code word v _ALT=(s, p, q), and matrix A and C corresponding informance vector s, the corresponding a part of verification vector of matrix B and D p, matrix L and E be corresponding remaining verification vector q then.The method of calculating section verification vector p is as follows:

p＝s(C+EL ^-1A) ^Τ((D+EL ^-1B) ^-1) ^Τ (2)

Wherein, subscript ^-1With ^ΤRepresent respectively matrix inversion and transposition.Order

m＝s(C+EL ^-1A) ^Τ (3)

F＝((D+EL ^-1B) ^-1) ^Τ (4)

Then vectorial m and matrix F satisfy following relation:

p＝mF (5)

Matrix F is by following u * u b * b rank circular matrix F _{I, j}(0≤i＜u, the accurate circular matrix that 0≤j＜u) constitutes:

Capable and the b of the continuous b of F row are called as the capable and piece row of piece respectively.By formula (6) as can be known, F has the capable and u piece row of u piece.Make f _{I, j}Be circular matrix F _{I, j}Generator polynomial.

Make vectorial m=(e ₀, e ₁..., e _{U * b-1}), part verification vector p=(d ₀, d ₁..., d _{U * b-1}).Be one section with the b bit, vectorial m and part verification vector p all are divided into the u section, i.e. m=(m ₀, m ₁..., m _U-1) and p=(p ₀, p ₁..., p _U-1).By formula (5) as can be known, the j section p of part verification vector _jSatisfy

p _j＝m ₀F _0,j+m ₁F _1,j+…+m _iF _i,j+…+m _u-1F _u-1,j (7)

Wherein, 0≤i＜u, 0≤j＜u.Order

With

Be respectively generator polynomial f _{I, j}The result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (7) equal sign the right is deployable is

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{r\left(0\right)}+e_{i\×b+1}{f}_{i,j}^{r\left(1\right)}+\·\·\·+e_{i\×b+b-1}{f}_{i,j}^{r(b-1)}---\left(8\right)$

Formula (5) relates to the multiplication of vector and accurate circular matrix, and u the I type shift register that be based on that extensively adopts adds totalizer (Type-I Shift-Register-Adder-Accumulator, SRAA-I) scheme of circuit at present.Fig. 1 is the functional block diagram of single SRAA-I circuit, and vectorial m serial by turn sends into this circuit.When using SRAA-I circuit calculation check section p _j(during 0≤j＜u), the generator polynomial look-up table is stored all generator polynomials of the j piece row of accurate circular matrix F in advance, and totalizer is cleared initialization.When the 0th clock period arrived, shift register loaded the 0th row of F, the generator polynomial of j piece row from the generator polynomial look-up table

Bit e ₀Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product

Add with content 0 mould 2 of totalizer and

Deposit back totalizer.When the 1st clock period arrives, 1 of shift register ring shift right, content becomes

Bit e ₁Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product

Content with totalizer Mould 2 add and

Deposit back totalizer.Above-mentioned moving to right-take advantage of-Jia-storing process is proceeded down.When b-1 clock period finishes, bit e _B-1Moved into circuit, that cumulative adder stores is part and m at this moment ₀F _{0, j}, this is array section m ₀To p _jContribution.When b clock period arrived, shift register loaded the 1st row of F, the generator polynomial of j piece row from the generator polynomial look-up table

Repeat above-mentioned moving to right-take advantage of-Jia-storing process.As array section m ₁When moving into circuit fully, cumulative adder stores be the part and m ₀F _{0, j}+ m ₁F _{1, j}Repeat said process, move into circuit up to the whole serials of whole vectorial m.At this moment, that cumulative adder stores is verification section p _jUse u SRAA-I circuit can constitute accurate circular matrix serial multiplier shown in Figure 2, it obtains u verification section simultaneously in u * b clock period.This scheme needs 2 * u * b register, u * b two input and door and u * b two input XOR gate, also needs the generator polynomial of u u * b bit ROM storage circular matrix.

The existing solution of accurate circular matrix serial multiplication is based on u SRAA-I circuit in the QC-LDPC near lower triangular coding, this scheme has two shortcomings: the one, and shift register is in each clock period or load new generator polynomial, 1 of ring shift right, cause the memory contents of single register constantly to change, and then cause the power consumption of circuit big; The 2nd, the generator polynomial of circular matrix is dispersed among a plurality of ROM, as everyone knows, when realizing ROM with the storer in the FPGA sheet, can cause the waste of storer inevitably, the more many wastes of ROM number are more serious, certainly will cause the storer of circuit big, cost is high.

Summary of the invention

The existing implementation of accurate circular matrix serial multiplication exists power consumption height, storer is big, cost is high shortcoming in the QC-LDPC near lower triangular coding, at these technical matterss, the invention provides a kind of based on the accurate circular matrix serial multiplier of sharing memory mechanism.

As shown in Figure 4, the accurate circular matrix serial multiplier in the QC-LDPC near lower triangular coding mainly is made up of 6 parts: generator polynomial look-up table, impact damper, b position binary multiplier, b position binary adder, shift register and chronotron.Multiplication process divided for 5 steps finished: the 1st step, zero clearing chronotron D and shift register R ₀, R ₁..., R _U-1, impact damper B _jWhen arriving, the i * b+j clock period load the generator polynomial f that accurate circular matrix F i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other; The 2nd step, when k clock period arrives, chronotron D input bit e _k(0≤k＜u * b), impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, imported up to whole vectorial m to finish; In the 4th step, when the clock cycle arrived, chronotron D imported filling bit 0, impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1The 5th step repeated the 4th and goes on foot u time, finishes up to 0 input of u filling bit, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Accurate circular matrix serial multiplier provided by the invention is simple in structure, can keep speed and logical resource to expend under the constant condition basically, reduces power consumption, reduces storage requirement, saves cost.

Can be further understood by following detailed description and accompanying drawings about advantage of the present invention and method.

Description of drawings

Fig. 1 is the functional block diagram that I type shift register adds totalizer SRAA-I circuit;

Fig. 2 is the accurate circular matrix serial multiplier that is made of u SRAA-I circuit;

Fig. 3 is the functional block diagram that impact damper adds shift register BASR circuit;

Fig. 4 is a kind of accurate circular matrix serial multiplier based on shared memory mechanism that is made of u BASR circuit.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.

Since the generator polynomial f with circular matrix _{I, j}Ring shift right n position is equivalent to its ring shift left b-n position, namely

Formula (8) can be rewritten as so

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{1\left(b\right)}+e_{i\×b+1}{f}_{i,j}^{1(b-1)}+\·\·\·+e_{i\×b+b-1}{f}_{i,j}^{1\left(1\right)}$

＝(e _i×bf _i,j) ^l(b)+(e _i×b+1f _i,j) ^l(b-1)+…+(e _i×b+b-1f _i,j) ^l(1)

＝(0+e _i×bf _i,j) ^l(b)+(e _i×b+1f _i,j) ^l(b-1)+…+(e _i×b+b-1f _i,j) ^l(1) (9)

＝((0+e _i×bf _i,j) ^l(1)+e _i×b+1f _i,j) ^l(b-1)+…+(e _i×b+b-1f _i,j) ^l(1)

＝(…((0+e _i×bf _i,j) ^l(1)+e _i×b+1f _i,j) ^l(1)+…+e _i×b+b-1f _i,j) ^l(1)

Formula (9) is one to be taken advantage of-process of Jia-move to left-store, and its realization adds shift register (Buffer-Adder-Shift-Register, BASR) circuit with impact damper.Fig. 3 is the functional block diagram of BASR circuit, and vectorial m is sent into this circuit by serial by turn.When using BASR circuit calculation check section p _j(during 0≤j＜u), the generator polynomial look-up table is stored all generator polynomials of the j piece row of accurate circular matrix F in advance, and shift register is cleared initialization.When the 0th clock period arrived, impact damper loaded the 0th row of F, the generator polynomial f of j piece row from the generator polynomial look-up table _{0, j}, bit e ₀Move into circuit, and with the content f of impact damper _{0, j}Carry out scalar and take advantage of, product e ₀f _{0, j}Add with content 0 mould 2 of shift register, and e ₀f _{0, j}Result (the 0+e that ring shift left is 1 ₀f _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.When the 1st clock period arrived, the content of impact damper remained unchanged, bit e ₁Move into circuit, and with the content f of impact damper _{0, j}Carry out scalar and take advantage of, product e ₁f _{0, j}Content (0+e with shift register ₀f _{0, j}) ^{L (1)}Mould 2 adds and (0+e ₀f _{0, j}) ^{L (1)}+ e ₁f _{0, j}The result ((0+e that ring shift left is 1 ₀f _{0, j}) ^{L (1)}+ e ₁f _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.Above-mentioned taking advantage of-Jia-move to left-storing process is proceeded down.When b-1 clock period finishes, bit e _B-1Moved into circuit, that this moment, shift register was stored is part and m ₀F _{0, j}, this is array section m ₀To p _jContribution.When b clock period arrived, impact damper loaded the 1st row of F, the generator polynomial f of j piece row from the generator polynomial look-up table _{1, j}, repeat above-mentioned taking advantage of-Jia-move to left-storing process.As array section m ₁When moving into circuit fully, that shift register is stored is part and m ₀F _{0, j}+ m ₁F _{1, j}Repeat said process, move into circuit up to the whole serials of whole vectorial m.At this moment, that the shift register storage is verification section p _j

Fig. 4 has provided a kind of accurate circular matrix serial multiplier based on shared memory mechanism that is made of u BASR circuit, is made up of generator polynomial look-up table, impact damper, b position binary multiplier, b position binary adder, shift register and six kinds of functional modules of chronotron.The generator polynomial look-up table is used for the generator polynomial of all circular matrixes of storage, and u BASR circuit shared this look-up table, and generator polynomial is therefrom read in timesharing.Impact damper B ₀, B ₁..., B _U-1Difference buffer memory the 0th, 1 ..., the generator polynomial of circular matrix in the u-1 piece row.Impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively with chronotron D in data bit D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, this u scalar multiplication is respectively by b position binary multiplier M ₀, M ₁..., M _U-1Finish.B position binary multiplier M ₀, M ₁..., M _U-1Product respectively with shift register R ₀, R ₁..., R _U-1The content addition, this u nodulo-2 addition is respectively by b position binary adder A ₀, A ₁..., A _U-1Finish.B position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1Data bit D among the chronotron D ₀～D _U-1Slide and store the u Bit data of vectorial m.

Circular matrix generator polynomial among the accurate circular matrix F of generator polynomial look-up table stores stores earlier in the 0th row the 0th, 1 successively,, the generator polynomial that u-1 piece row are corresponding stores in the 1st row the 0th more successively, 1,, the corresponding generator polynomial of u-1 piece row, the rest may be inferred, store successively at last the u-1 piece capable in the 0th, 1 ..., the corresponding generator polynomial of u-1 piece row.

The invention provides a kind of accurate circular matrix serial multiplication based on shared memory mechanism, its multiplication step is described below:

The 1st step, zero clearing chronotron D and shift register R ₀, R ₁..., R _U-1, impact damper B _jWhen arriving, the i * b+j clock period load the generator polynomial f that accurate circular matrix F i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other;

The 2nd step, when k clock period arrives, chronotron D input bit e _k(0≤k＜u * b), impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, imported up to whole vectorial m to finish;

In the 4th step, when the clock cycle arrived, chronotron D imported filling bit 0, impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1

The 5th step repeated the 4th and goes on foot u time, finishes up to 0 input of u filling bit, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Be not difficult to find out that from above step whole computation process needs u * b+u clock period altogether, Duoed u clock period than existing serial multiplication scheme based on u SRAA-I circuit.Usually, u can ignore much smaller than u * b.As seen, the speed of two kinds of multiplication scheme is basic identical.

The existing solution of accurate circular matrix serial multiplication needs 2 * u * b register, u * b two input and door and u * b two input XOR gate, and the present invention needs 2 * u * b+u register, u * b two input and door and u * b two input XOR gate.Two kinds of multiplication scheme expend equal number with door and XOR gate, the present invention has used u register more.Usually, u can ignore much smaller than 2 * u * b.As seen, the register that expends of two kinds of multiplication scheme is also basic identical.

To sum up, two kinds of multiplication scheme have almost completely identical speed and logical resource to expend.Yet the present invention has two clear superiorities, has overcome the shortcoming of the existing solution of accurate circular matrix serial multiplication.In existing solution, shift register is in each clock period or load new generator polynomial, 1 of ring shift right, the memory contents of single register constantly variation causes the power consumption of circuit big, and the present invention uses the generator polynomial of buffer load circular matrix, it is mobile to need not circulation, and the every b of its content clock period changes once, greatly reduced power consumption.This is first advantage of the present invention.Second advantage is to adopt based on shared memory mechanism, use single ROM and same data bus to realize the generator polynomial look-up table, overcome that the waste that a plurality of ROM bring in the existing solution is many, storer is big, the high shortcoming of cost, simplified the project organization of generator polynomial look-up table greatly, farthest save storage space, reduced cost.

In brief, for the accurate circular matrix serial multiplication in the QC-LDPC near lower triangular coding, compare with existing solution, the present invention has kept identical speed and logical resource to expend basically, has that power consumption is little, simple in structure, memory consumption is few, low cost and other advantages.

The above; it only is one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claims were limited.

Claims (4)

1. one kind based on the accurate circular matrix serial multiplier of sharing memory mechanism, when adopting the near lower triangular coding method that the QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, vectorial m=(e ₀, e ₁..., e _{U * b-1}), be one section with the b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), it is characterized in that described multiplier comprises with lower member:

The generator polynomial look-up table, the generator polynomial that is used for storing accurate circular matrix F circular matrix;

Chronotron D, its data bit D ₀, D ₁..., D _U-1Slide and store the u Bit data of vectorial m;

Impact damper B ₀, B ₁..., B _U-1, the accurate circular matrix F the 0th, 1 of difference buffer memory ..., the generator polynomial of circular matrix in the u-1 piece row;

B position binary multiplier M ₀, M ₁..., M _U-1, respectively to data bit D ₀, D ₁..., D _U-1With impact damper B ₀, B ₁..., B _U-1In generator polynomial carry out scalar and take advantage of;

B position binary adder A ₀, A ₁..., A _U-1, respectively to b position binary multiplier M ₀, M ₁..., M _U-1Sum of products shift register R ₀, R ₁..., R _U-1Content carry out mould 2 and add;

Shift register R ₀, R ₁..., R _U-1, store b position binary adder A respectively ₀, A ₁..., A _U-1And be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p _U-1

2. according to claim 1 a kind of based on the accurate circular matrix serial multiplier of sharing memory mechanism, it is characterized in that, circular matrix generator polynomial among the accurate circular matrix F of described generator polynomial look-up table stores, store earlier in the 0th row the 0th successively, 1,, the generator polynomial that u-1 piece row are corresponding stores in the 1st row the 0th more successively, 1,, the corresponding generator polynomial of u-1 piece row, the rest may be inferred, store successively at last the u-1 piece capable in the 0th, 1 ..., the corresponding generator polynomial of u-1 piece row.

3. according to claim 1 a kind of based on the accurate circular matrix serial multiplier of sharing memory mechanism, it is characterized in that described impact damper B ₀, B ₁..., B _U-1Share the generator polynomial look-up table, generator polynomial is therefrom read in timesharing, impact damper B _jWhen arriving, the i * b+j clock period load the generator polynomial f that accurate circular matrix F i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other.

4. one kind based on the accurate circular matrix serial multiplication method of sharing memory mechanism, when adopting the near lower triangular coding method that the QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, vectorial m=(e ₀, e ₁..., e _{U * b-1}), be one section with the b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), it is characterized in that described multiplication method may further comprise the steps:

The 1st step, zero clearing chronotron D and shift register R ₀, R ₁..., R _U-1, impact damper B _jWhen arriving, the i * b+j clock period load the generator polynomial f that accurate circular matrix F i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other;

The 2nd step, when k clock period arrives, chronotron D input bit e _k, impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1, wherein, 0≤k＜u * b;

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, imported up to whole vectorial m to finish;

In the 4th step, when the clock cycle arrived, chronotron D imported filling bit 0, impact damper B ₀, B ₁..., B _U-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _U-1With the data bit D among the chronotron D ₀, D ₁..., D _U-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _U-1Product respectively by b position binary adder A ₀, A ₁..., A _U-1With shift register R ₀, R ₁..., R _U-1The content addition, b position binary adder A ₀, A ₁..., A _U-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _U-1

The 5th step repeated the 4th and goes on foot u time, finishes up to 0 input of u filling bit, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

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