CN103259536A - Apparatus to remove the loop filter resistor noise in charge-pump PLL - Google Patents
Apparatus to remove the loop filter resistor noise in charge-pump PLL Download PDFInfo
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- CN103259536A CN103259536A CN2013101239570A CN201310123957A CN103259536A CN 103259536 A CN103259536 A CN 103259536A CN 2013101239570 A CN2013101239570 A CN 2013101239570A CN 201310123957 A CN201310123957 A CN 201310123957A CN 103259536 A CN103259536 A CN 103259536A
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Abstract
An improved charge pump based phase locked loop where the loop filter resistor noise is reduced by about an order is presented. The voltage controlled oscillator generates a clock signal, and this is input to the phase detector, which, compares the oscillator clock with the reference clock and using the charge pump it generates a current output proportional to the phase difference. The loop filter converts this proportional current to a voltage and connects it to the oscillator input. The loop filter consists of a capacitor, resistor and the apparatus that bypasses most of the resistor noise.
Description
Priority
The application requires on February 20th, 2012 to submit to, title is the U.S. Provisional Application NO.61/600 of " technology (A NOVEL TECHNIQUE TO REMOVE THE LOOP FILTER RESISTOR NOISE IN CHARGE-PUMPPLL) of eliminating charge pump phase lock loop road intermediate ring road filter resistor noise ", 745 priority, its full content is incorporated this paper into as a reference.
Technical field
The application relates generally to a kind of phase-locked loop (PLL), and relates more specifically to eliminate PLL intermediate ring road filter resistors thermal noise.
Background technology
With reference to figure 1, it shows conventional P LL100.Resistor Rcp155 is used to PLL100 being used for stable purpose, in order to produce " zero " and guarantee near the entire gain frequency stability in the loop switch function.Yet the whole phase noise (shake) of PLL can be problematic.
Proposed to solve PLL loop variety of issue, phase noise feature for example, additive method, the U.S. Patent No. 6 of Klemmer for example, 420,917B1, title are " the PLL loop (PLL Loop Filter With Switched-Capacitor Resistor) with switched-capacitor resistor ".Yet, as if there are three shortcomings in this structure: 1) have the demand of additional capacitor and may increase 15% of whole loop filter area, 2) need the non-overlapping clock generator to produce the control signal that is used for switched capacitor, 3) need two big switches to be used for switched capacitor network (Q1 of Fig. 4 of Klemmer patent and Q2), owing to connect by capacitor parasitics, this can increase some switching noises at ' VCTRL ' node.
Therefore, this area exists a kind of demand to handle at least some relevant problems of conventional P LL circuit.
Summary of the invention
First aspect provides a kind of circuit, comprising: phase-frequency detector (PFD); Current switch upwards, it is coupled to the output of comparison phase detectors; Downward current switch, it is coupled to the output of PFD; Current source, it is coupled to node by the current switch that makes progress, downward current source, it is coupled to node by downward current switch, this node is coupled to: a) voltage controlled oscillator (VCO), wherein the input of the output of VCO and PFD connects, and b) loop filter resistance bypass circuit, it comprises: the loop filter resistor, and it is coupled to this node; Capacitor, itself and loop filter resistor in series, this capacitor also is grounded; And first by-pass switch, it is coupled to this node, second by-pass switch, itself and the first by-pass switch coupled in series, this second by-pass switch also is coupled to the anode of capacitor, wherein first by-pass switch and second by-pass switch be one another in series and with the parallel connection of loop filter resistor, wherein when first and second by-pass switches were not closed, this loop filter resistor was used to produce zero point in loop; And first control line, its by the CMOS inverter from current switch upwards to connecting the first bypass resistance element; Second control line, be connected to the second bypass resistance element by another CMOS inverter from the current switch that makes progress, wherein first and second by-pass switches are that complementary cmos is right, wherein when first and second by-pass switches are not closed, the loop filter resistor is used to produce zero utmost point, and when the loop filter resistor was bypassed, the noise of loop filter resistor was bypassed.
Second aspect provides a kind of circuit, comprising: PFD; Current switch upwards, it is coupled to the output of comparison phase detectors; Downward current switch, it is coupled to the output of PFD; Current source, it is coupled to node by the current switch that makes progress; Downward current source, it is coupled to node by downward current switch, and this node is coupled to: a) VCO, and wherein the output of VCO is coupled to the input of PFD, and b) loop filter resistance bypass circuit, it comprises: the loop filter resistor that is connected to this node; With the capacitor that connects with the loop filter resistor in series, this capacitor is ground connection also; And first by-pass switch that is connected to this node, coupled in series is to second by-pass switch of first by-pass switch, second by-pass switch also connects with the anode of capacitor, wherein first by-pass switch and second by-pass switch be coupled to one another in series and and with the parallel connection of loop filter resistor.
The third aspect provides a kind of circuit, comprising: a kind of circuit has: PFD; One current switch upwards, it is coupled to the output of comparison phase detectors; Downward current switch, it is coupled to the output of comparator phase detectors; Current source, it is coupled to node by the current switch that makes progress, downward current source, it is coupled to node by downward current supply switch, this node is coupled to: a) VCO, wherein the output of VCO is connected to the input of PFD, and b) loop filter resistance bypass circuit, it comprises: the loop filter resistor that is connected to this node; With the capacitor that this loop filter resistor in series connects, this capacitor also is grounded; And first by-pass switch, it is coupled to this node, second by-pass switch, itself and the first by-pass switch coupled in series, second by-pass switch also is coupled to the anode of capacitor, wherein first by-pass switch and second by-pass switch be coupled to one another in series and with the parallel connection of loop filter resistor, wherein when first and second by-pass switches were not closed, the loop filter resistor was used to produce zero point in circuit; And first control line, it is connected to the first bypass resistance element from current switch upwards; And second control line, it is connected to the second bypass resistance element from current switch upwards.
Description of drawings
With reference now to following description:
Fig. 1 shows conventional P LL circuit;
Fig. 2 shows has the PLL circuit that the loop filter resistor removes circuit;
Fig. 3 A is the graphical representation of exemplary of Fig. 2 signal when PLL is in stable state among Fig. 2;
Fig. 3 B is the graphical representation of exemplary that Fig. 2 intermediate ring road filter resistors removes the reception signal of circuit; And
Fig. 4 is example modelled figure, has compared the pectrum noise density that has and do not have the loop filter of noise bypass circuit.
Embodiment
With reference to figure 2, it shows the aspect that the loop filtering resistor removes the PLL of circuit 200 that has according to the application's principles of construction.Inventor by the application's appointment understands, and in typical charge pump PLL, the loop filter resistor is one of reason that causes total output PLL phase noise (shake).Remove the loop filter method of resistor by during the part PLL cycle, using, can reduce the loop filter resistor noise of PLL.
Usually, PLL comprises two utmost points and high DC gain in starting point, is unsettled therefore.Resistor is connected in series to capacitor, and to produce zero point in the feedback control loop of PLL, this helps to stablize PLL as the loop filter resistor.Desirable as the inventor, the loop filter resistor, understanding according to the present inventor, more problems have been introduced in the employing of resistor Rcp155 among Fig. 1 in the PLL circuit, as thermal noise, this has increased shake, that is, add thermal noise to PLL and influence final PLL output clock phase noise.According to inventor's understanding, during the high speed low jitter in traditional PLL design was used, the loop filter resistor became one of principal element that causes phase noise.
Common more information about PLL, see also Behzad Razavi " Design of Analog CMOS Integrated Circuits ", chapters and sections 15.2.3, " Basic Charge-Pump PLL ", McGraw Hill International publishes, date of printing calendar year 2001,556-562 page or leaf, this paper merge quotes its full content.It has set forth the PLL loop dynamic, and more specifically, consults the discussion for the two poles of the earth, and it has further introduced the discussion for the zero demand that keeps PLL stability.
In circuit 200, phase-frequency detector (PFD) 210 receives REFCLK signal, i.e. reference clock signal and FDBKCLK signal, i.e. feedback clock signal.PFD210 exports make progress signal UP211 and downward signal DN212, and it drives the switch 222 that makes progress respectively and opens or closes with downward switch 227.Upwards switch 222 is coupled to first charge pump 220, and it is current source.Switch 227 is coupled to second charge pump 225 downwards, and it is current source equally.Upwards switch 222 and downward switch 227 are connected in together at node 229.
What be connected to node 229 is that the loop filter resistor removes circuit 250, and it has VCTRL voltage at node 229.Remove circuit 250 and comprise the loop filter resistor 255 that is connected to node 229.The first switch UPZ260 and second switch DNZ265 are from node 229 coupled in series, and same parallel connection is to loop filter resistor 255.RCP255 also is coupled to filter capacitor 270, described filter capacitor 270 coupled ground connection.Switch 260,265 each can be that complementary cmos is right.
In PLL circuit 200, UP line 222 is by control line 230 and pass inverter 213 and be connected to UPZ switch 260; And switch 227 is connected to DNZ switch 265 by inverter 215 and by control circuit 235 downwards.
When UP211 is logic when high, UPZ switch 260 be opened (logic low).When UP211 was logic low, UPZ switch 260 was closed (logic height).When DN212 is logic when high, DNZ switch 265 be opened (logic low).When DN212 is logic low, DNZ switch 265 is closed (logic height).
Understand as the inventor, typically, in case PLL quilt " setting ", charge pump 220, the 225 only sub-fraction in the whole PLL cycle is activated, for example, and approximate 5% to 10%.Therefore, loop filter Rcp255 only this short relatively blanking time by the loop stability sexual needs.Yet, in traditional PLL, unlike the application's PLL200, the loop filter resistor be connected to node 229 if having time and run through free noise, for example thermal noise of increasing of institute in PLL cycle.
In the suggesting method of the application's theory, when charge pump 220 or charge pump 225 charge or discharge capacitors 270, the loop filter resistor is used, for example Rcp255.Close switch 222 or switch 227 and be associated with the switch 260,265 of unlatching subsequently respectively, thereby add loop filter resistor Rcp255 to be used by PLL200.Yet if UP switch 222 and DN switch 227 are opened, UPZ switch 260 and DNZ switch 265 are closed so, short circuit Rcp255.Note that the resistance combination of switch 260 and 265, even all close and connect and add fashionablely when two, can be the quantity grade less than the resistance of Rcp255, thereby cause the reduction of noise in the circuit.Equally, switch 260 and 265 is complementary cmos switches, and can offset each other from PMOS and NMOS noise.Therefore, have minimum switching noise at node 229.
On the one hand, by the signal operation charge pump 220 and 225 that utilizes PFD210 to generate, the noise that utilizes two gate circuits 260 and 265, PLL loop filter resistor 255 to produce is lowered basically.The signal that is used for PLL circuit 200 parts is used in other parts of circuit 200.In PLL circuit 200, Rcp255 is can uncared-for element at least a portion in PLL cycle, and when needs polarity loop stability, it still keeps its function.
Many-sided, PLL200 can be used to generate the clock signal for signal incremental adjustments device.
Fig. 3 A and 3B show the time-scale of PLL200.
About 3A, as shown, in case PLL200 reaches stable state, clock REFCLK has identical frequency with FDBCLK, and phase alignment.In this state, the charge pump of short duration time durations that will only be activated is avoided the dead band, and this Dead Time is typically at about 5%-10% of clock cycle Tclk.The stable state waveform is illustrated in Fig. 3 A.
About 3B, show switch 222,227 exemplary status.As shown, when UP and DN switch opens/logic high signal be applied to switch 222,227 the time, switch 260 and 265 is opened, and therefore adds loop filter resistor Rcp255 in filter circuit.Yet when shutdown signal is applied to switch 222,227, switch 260 and 265 is closed, so short circuit Rcp255 and add less noise at node 229.Fig. 4 shows the diagram of the noise spectrum density of the loop filter that has and do not have the noise bypass circuit.The representative value supposition is Rcp=8000 ohm, and the all-in resistance of Cap=200pF and by-pass switch is 350 ohm (Ohm), and is switched to ON at 90% clock period by-pass switch.
Fig. 4 shows the exemplary simulated figure of the noise spectral density that has compared the loop filter that has and do not have the noise bypass circuit.From figure, the noise spectral density that does not have bypass circuit is higher than the noise spectral density with bypass circuit, up to some up to frequency (Fcut).This " Fcut " frequency depends on the by-pass switch resistor of combination and the ratio of Rcp.The loop filter noise produces the logical translation function of band to final PLL output, and top cut-out frequency is PLL entire gain bandwidth (UGB).Therefore the desirable whole loop filter noises that surpass PLL UGB frequency will be eliminated by the PLL loop, and therefore by still less concern.Therefore the by-pass switch impedance is carefully designed, and is so that for the loop filter with by-pass switch, littler up to total overall noise energy of PLL UGB.
Relevant with the application other and further increase, deletion, the substitutions and modifications of it will be appreciated by those skilled in the art that can be used among the described embodiment.
Claims (20)
1. circuit comprises:
Phase-frequency detector, i.e. PFD;
Current switch upwards, it is connected to the described relatively output of phase detectors;
Downward current switch, it is connected to the described relatively output of phase detectors;
Current source, it is connected to node by described upwards current switch,
Downward current source, it is connected to node by described downward current switch,
Described node is coupled to:
A) voltage controlled oscillator, i.e. VCO, the output of wherein said VCO is coupled to the input with described PFD, and
B) loop filter resistance bypass circuit comprises:
The loop filter resistor, it is coupled to described node;
Capacitor, it connects with described loop filter resistor in series, and described capacitor also is grounded; And
First by-pass switch, it is coupled to described node, and
Second by-pass switch, itself and the described first by-pass switch coupled in series,
Described second by-pass switch also is coupled to the anode of described capacitor,
Wherein said first by-pass switch and described second by-pass switch be coupled to one another in series and with the parallel connection of described loop filter resistor,
Wherein when described first by-pass switch and described second by-pass switch are not closed, described loop filter resistor is used to produce zero point producing zero utmost point in described circuit, and
First control line, it is connected to the described first bypass resistance element from described upwards current switch; And
Second control line, it is connected to the described second bypass resistance element from described upwards current switch,
Wherein said first by-pass switch and described second by-pass switch are that complementary cmos is right,
Wherein when described first by-pass switch and described second by-pass switch were not closed, described loop filter resistor was used to produce zero point and produces described zero utmost point in described circuit, and
When the loop filter resistor was bypassed, the noise of described loop filter resistor was bypassed.
2. circuit according to claim 1, wherein said circuit comprises phase-locked loop, i.e. PLL.
3. circuit according to claim 1, wherein said first by-pass switch and described second by-pass switch are that complementary cmos is right.
4. circuit according to claim 1 further comprises:
First control line is connected to the described first bypass resistance element by first inverter from described upwards contactor; And
Second control line is connected to the described second bypass resistance element by second inverter from described upwards current switch.
5. circuit according to claim 1 comprises that further wherein said circuit is configured to open and close substantially simultaneously source current source and first switch.
6. circuit according to claim 1 comprises that further wherein said circuit is configured to open and close substantially simultaneously reverse current source and second switch.
7. circuit according to claim 1, wherein described first switch and the described second switch bypass that are closed of resistive element.
8. circuit according to claim 1, the resistance that wherein said resistive element has are ten times of combined resistance of described first by-pass switch and described second by-pass switch at least.
9. circuit according to claim 1, wherein when described first by-pass switch and described second by-pass switch were not closed, described loop filter resistor was used to produce zero point in described circuit.
10. circuit according to claim 2, wherein when described loop filter resistor was bypassed, the noise of described loop filter resistor was bypassed, and therefore obtained shake less in the PLL loop.
11. a circuit comprises:
Phase-frequency detector, i.e. PFD;
Current switch upwards, it is connected to the output of comparison phase detectors;
Downward current switch, it is connected to described output than phase detectors;
Current source, it is connected to node by described upwards current switch;
Current source is connected to node by described downward current switch downwards,
Described node is coupled to:
A) voltage controlled oscillator, i.e. VCO, the output of wherein said VCO is coupled to the input of described PFD, and
B) loop filter resistance bypass circuit comprises:
The loop filter resistor, it is coupled to described node;
Capacitor, it connects with described loop filter resistor in series, and described capacitor also is grounded; And
First by-pass switch, it is coupled to described node,
Second by-pass switch, it is arrived described first by-pass switch by coupled in series,
Described second by-pass switch also is coupled to the anode of described capacitor,
Wherein said first by-pass switch and described second by-pass switch be coupled to one another in series and with the parallel connection of described loop filter resistor.
12. circuit according to claim 11, wherein said circuit comprises phase-locked loop, i.e. PLL.
13. circuit according to claim 11, wherein said first by-pass switch and described second by-pass switch are that complementary cmos is right.
14. circuit according to claim 11 further comprises:
First control line, it is connected to the described first bypass resistance element from described upwards current switch; And
Second control line, it is connected to the described second bypass resistance element from described upwards current switch.
15. circuit according to claim 11 comprises that further wherein said circuit is configured to open and close substantially simultaneously source current source and first switch.
16. circuit according to claim 11 comprises that further wherein said circuit is configured to open and close substantially simultaneously reverse current source and second switch.
17. circuit according to claim 11, wherein first switch and the second switch bypass that are closed of resistive element.
18. circuit according to claim 17, wherein when described loop filter resistor was bypassed, the noise of described loop filter resistor was bypassed, and therefore obtained the less shake in the described PLL loop.
19. a circuit comprises:
Phase-frequency detector, i.e. PFD;
Current switch upwards, it is coupled to the output of comparison phase detectors;
Downward current switch, it is coupled to the described relatively output of phase detectors;
Current source, it is connected to node by described upwards current switch,
Downward current source, it is connected to node by described downward current switch,
Described node is connected to:
A) voltage controlled oscillator, i.e. VCO, the output of wherein said VCO is coupled to the input of described PFD, and
B) loop filter resistance bypass circuit comprises:
The loop filter resistor, it is coupled to described node;
Capacitor, it connects with described loop filter resistor in series, and described capacitor also is grounded; And
First by-pass switch, it is coupled to described node, and
Second by-pass switch, itself and the described first by-pass switch coupled in series,
Described second by-pass switch also connects with the anode of described capacitor, wherein
Wherein said first by-pass switch and described second by-pass switch be coupled to one another in series and with the parallel connection of described loop filter resistor,
Wherein when described first by-pass switch and described second by-pass switch were not closed, described loop filter resistor was used to produce zero point in described circuit, and
First control line, it is connected to the described first bypass resistance element from described upwards current switch; And
Second control line, it is connected to the described second bypass resistance element from described upwards current switch.
20. circuit according to claim 19, wherein said circuit comprises phase-locked loop, i.e. PLL.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261600745P | 2012-02-20 | 2012-02-20 | |
| US61/600,745 | 2012-02-20 | ||
| US13/462,973 US8593188B2 (en) | 2012-02-20 | 2012-05-03 | Apparatus to remove the loop filter resistor noise in charge-pump PLL |
| US13/462,973 | 2012-05-03 |
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| CN103259536A true CN103259536A (en) | 2013-08-21 |
| CN103259536B CN103259536B (en) | 2018-12-18 |
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| CN201310123957.0A Active CN103259536B (en) | 2012-02-20 | 2013-02-20 | Eliminate the device of charge pump phase lock loop road loop filter resistor noise |
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Cited By (5)
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| CN104426479A (en) * | 2013-08-29 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Low-power consumption, low-jitter, and wide working-range crystal oscillator circuit |
| CN104426536A (en) * | 2013-09-09 | 2015-03-18 | 索尼公司 | Phase Locked Loop Circuit, Phase Locked Loop Module, And Phase Locked Loop Method |
| US9160952B2 (en) | 2013-05-07 | 2015-10-13 | Shanghai Huali Microelectronics Corporation | CMOS charge pump circuit |
| CN108075773A (en) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | For the start-up circuit and phaselocked loop of phaselocked loop |
| CN109716655A (en) * | 2016-09-22 | 2019-05-03 | 高通股份有限公司 | Switched-capacitor circuit in PLL |
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| CN109716655A (en) * | 2016-09-22 | 2019-05-03 | 高通股份有限公司 | Switched-capacitor circuit in PLL |
| CN108075773A (en) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | For the start-up circuit and phaselocked loop of phaselocked loop |
| CN108075773B (en) * | 2016-11-14 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Starting circuit for phase-locked loop and phase-locked loop |
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