CN103257940A - Data writing method and device for SoC (system on chip) - Google Patents
Data writing method and device for SoC (system on chip) Download PDFInfo
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- CN103257940A CN103257940A CN2013101033489A CN201310103348A CN103257940A CN 103257940 A CN103257940 A CN 103257940A CN 2013101033489 A CN2013101033489 A CN 2013101033489A CN 201310103348 A CN201310103348 A CN 201310103348A CN 103257940 A CN103257940 A CN 103257940A
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Abstract
The invention provides data writing method and device for a SoC (system on chip). The SoC comprises a clock signal with door control. The method includes: sending out a write command and a target address by a receiving source; sending the write command to a target according to the target address; receiving a signal of approving the write command, returned from the target, and initiating the clock signal; writing the received data from the terminal into the target according to the clock signal; and stopping the clock signal when last data from the source is received and sent to the target. The data writing method for the SoC has the advantage that clock flip consumption can be reduced.
Description
Technical field
The present invention relates to SOC (system on a chip) SoC technical field of data processing, particularly relate to method and device that a kind of SOC (system on a chip) SoC writes data.
Background technology
Along with the lifting of integrated circuit technology node, also greatly improving of chip integration also caused the increase rapidly of power consumption simultaneously.In addition, market makes system power dissipation become an important indicator of system performance to the heavy demand of electronic equipment, and the height of power consumption has become one of focus of chip manufacturer competitive power, and power consumption control and management have become the problem of most chip manufacturer overriding concern.The power consumption of SoC design comprises two parts: quiescent dissipation and dynamic power consumption.Quiescent dissipation is caused by leakage current that mainly under 130nm technology, quiescent dissipation is less relatively, can ignore.Dynamic power consumption mainly comprises short-circuit dissipation and upset power consumption, is the chief component of design consumption.Short-circuit dissipation is internal power consumption, refers to by device inside because P pipe and N pipe cause in the instantaneous short-circuit that certain conducting simultaneously in a flash causes.The upset power consumption is discharged and recharged by the output terminal load capacitance of cmos device and causes.During chip operation, power consumption is that if clock network is bigger, this part power consumption penalty that causes can be very big because the upset of clock network consumes greatly.For the upset of the register group in the design owing to clock signal clk, the register group can continue to read at the rising edge of CLK the data of data input pin temporarily, and the data that at this moment read are constant, and this has just consumed extra power consumption.
Therefore, those skilled in the art press for one of problem of solution and are, propose method and device that a kind of SOC (system on a chip) SoC writes data, in order to reduce the upset consumption of clock.
Summary of the invention
Technical matters to be solved by this invention provides method and the device that a kind of SOC (system on a chip) SoC writes data, in order to reduce the upset consumption of clock.
In order to address the above problem, the invention discloses the method that a kind of SOC (system on a chip) SoC writes data, comprise the clock signal of being with gate among the described SOC (system on a chip) SoC, described method comprises:
The write order that the reception sources end sends and destination end address;
Address according to described destination end is sent to destination end with described write order;
Receive the signal of the described write order of agreement that described destination end returns and open clock signal;
The data that the described source end that will receive according to described clock signal sends write described destination end;
When receiving and sending last data that described source end sends to destination end, close described clock signal.
Preferably, after the data that the described described source end that will receive according to clock signal sends write the step of described destination end, also comprise:
Receive the effective signal of data that described source end sends according to the described data of sending;
Receive the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
Preferably, after the data that the described source end that will receive according to described clock signal sends write the step of described destination end, also comprise:
The signal that whether normally writes the data that described source end sends that receives that described destination end returns.
Preferably, the signal of the described write order of agreement that returns of described receiving target end and the step of opening clock signal comprise:
The signal of the described write order of agreement that the receiving target end returns;
Signal according to the described write order of described agreement generates the clock enable signal;
Open clock signal according to described clock enable signal.
Preferably, described when receiving and sending last data that described source end sends to destination end, the step of closing described clock signal comprises:
Receive last data that described source end sends and be sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
Receive the data that described destination end sends and receive signal;
Receive signal according to described data and generate the clock shutdown signal;
Close clock signal according to described clock shutdown signal.
The embodiment of the invention also discloses a kind of SOC (system on a chip) SoC and write the device of data, comprise the clock signal of being with gate among the described SOC (system on a chip) SoC, described device comprises:
The write order receiver module is used for write order and destination end address that the reception sources end sends;
The write order sending module is used for according to the address of described destination end described write order being sent to destination end;
The clock opening module be used for to receive the signal of the described write order of agreement that described destination end returns and opens clock signal;
Write data module, be used for writing described destination end according to the data that the described source end that described clock signal will receive sends;
The clock closing module is used for when reception and when sending last data that described source end sends to destination end, closes described clock signal.
Preferably, described device also comprises:
Source end useful signal receiver module is used for receiving the effective signal of data that described source end sends according to the described data of sending;
Destination end useful signal module is used for receiving the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
Preferably, described device also comprises:
The normal writing module of destination end is used for receiving that described destination end returns whether normally writes the signal of the data that described source end sends.
Preferably, described clock opening module comprises:
Approval signal receives submodule, is used for the signal of the described write order of agreement that the receiving target end returns;
Enable signal generates submodule, is used for generating the clock enable signal according to the signal of the described write order of described agreement;
Clock enables submodule, is used for opening clock signal according to described clock enable signal.
Preferably, described clock closing module comprises:
Final data receives submodule, is used for receiving last data that described source end sends and is sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
The signal that finishes receives submodule, and the data of sending for the described destination end of reception receive signal;
Shutdown signal generates submodule, is used for receiving signal according to described data and generates the clock shutdown signal;
Clock closes closed submodule, is used for closing clock signal according to described clock shutdown signal.
Compared with prior art, the present invention includes following advantage:
The present invention initiates write order and receives fully between the signal that the destination end feedback receives sending the source end by bus master controller MASTER, generates the un-gate signal of clock signal clock, has in bus under the situation of data transmission to enable clock.Owing to only under bus has the situation of data transmission, just enable clock, so can reduce the upset consumption of clock signal.In addition, because the present invention adopts AMBA (Advanced Microcontroller Bus Architecture, Advanced Microcontroller Bus Architecture) data communication between the realization IP kernel, have and connect simply, interconnection architecture is realized flexibly, be convenient to integrated, be convenient to the expansion, characteristics such as bandwidth availability ratio height.
Description of drawings
Fig. 1 is the flow chart of steps that a kind of SOC (system on a chip) SoC of the present invention writes the method embodiment of data;
Fig. 2 is the sequential chart that a kind of AMBA3.0AXI bus of the present invention is write data flow;
Fig. 3 is the structured flowchart that a kind of SOC (system on a chip) SoC of the present invention writes the device embodiment of data.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
One of core idea of the present invention is, initiate write order and receive destination end fully to feed back between the signal that receives at the source of transmission end by bus master controller MASTER, generate the un-gate signal of clock signal clock, have in bus under the situation of data transmission to enable clock.Owing to only under bus has the situation of data transmission, just enable clock, so can reduce the upset consumption of clock signal.
With reference to Fig. 1, show the flow chart of steps that a kind of SOC (system on a chip) SoC of the present invention writes the method embodiment of data, comprise the clock signal of being with gate among the described SOC (system on a chip) SoC, described method specifically can comprise the steps:
Step 101, the write order that the reception sources end sends and destination end address;
In specific implementation, have bus on the SOC (system on a chip) SoC, be used for the data between each port of transmission.For example, can write operations such as data between source end and destination end mutually, reach the purpose of transmission data with this.When the source end is initiated write order, write order and the destination end address of carrying out this write order are sent on the bus.
Step 102, the address of the described destination end of foundation is sent to destination end with described write order;
After bus interface is received write order and destination end address, according to the destination end address write order is sent on the port of intended target end.
Step 103 receives the signal of the described write order of agreement that described destination end returns and opens clock signal;
In a preferred embodiment of the present invention, described step 103 can comprise following substep:
Substep S11, the signal of the described write order of agreement that the receiving target end returns;
Substep S12 is according to the signal generation clock enable signal of the described write order of described agreement;
Substep S13 opens clock signal according to described clock enable signal.
Particularly, if destination end is agreed the write order that execution source end is initiated, then send the signal of agreeing described write order and arrive bus, when bus interface is received the signal that this agrees described write order, generate clock enable signal un-gate, decontrol clock signal, the source end can begin will write data to destination end according to the clock signal of bus.
Step 104, the data that the described source end that will receive according to described clock signal sends write described destination end;
In specific implementation, when the clock signal at clear, the source end can begin data are sent on the bus, and bus interface sends to destination end according to clock signal with data after receiving data.
In a preferred embodiment of the present invention, described method can also comprise the steps:
Receive the effective signal of data that described source end sends according to the described data of sending;
Receive the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
Preferably, when the source end sent to destination end with data, if the data that the source end sends are active datas, then the source end sent the data useful signal that data are valid data; Whether if the data that destination end receives are active datas, the data that destination end is sent reception are active data useful signals, effective with the data of this real-time monitoring source end and destination end transmission.
In a preferred embodiment of the present invention, described method can also comprise the steps:
The signal that whether normally writes the data that described source end sends that receives that described destination end returns.
In embodiments of the present invention, if the data sent of the normal reception sources end of destination end, then return the signal that normally writes the data that described source end sends.
Step 105 when receiving and sending last data that described source end sends to destination end, is closed described clock signal.
In a preferred embodiment of the present invention, described step 105 can comprise following substep:
Substep S21 receives last data that described source end sends and is sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
Substep S22 receives the data that described destination end sends and receives signal;
Substep S23 receives signal according to described data and generates the clock shutdown signal;
Substep S24 closes clock signal according to described clock shutdown signal.
Preferably, when the source end sent out last data to destination end, bus received that destination end sends data and receive signal, and bus is received after data receive signal and closed clock signal, avoids because the clock consumption that the clock upset brings.
Need to prove, in the present invention except the write order to SOC (system on a chip) SoC, can realize all that to the command operation of transmission data such as read command the present invention is not restricted this.
In order to make those skilled in the art further understand the embodiment of the invention, illustrate that below by a concrete example bus of the present invention writes the process of data.
Write the sequential chart of data flow with reference to of the present invention a kind of AMBA3.0AXI bus shown in Figure 2.Wherein, the source end is master, and destination end is slave.From top to bottom, each row sequential is represented respectively:
ACLK_GATE: the clock behind the band gate; The write address that AWADDR:master sends out; AWVALID:master send out with effect; The AWREADY:slave feedback receives with effect; WDATA:master sends out writes data; WLAST:master send out this organize last valid data; The data useful signal that WVALID:master sends out; The reception useful signal of WREADY:slave feedback; Whether the BRESP:slave feedback data correctly receives signal; The BVALID:slave feedback data has write the signal that finishes; BREADY:slave signal working properly.
ACLK_GATE is the clock behind the band gate among the figure, can enable or close clock signal according to the bus behavior of master and slave, reaches the purpose of saving power consumption with this.It is as follows that bus is write the concrete steps flow process of data:
1, Master is write order (master send out with imitating signal), and the destination end address (write address that master sends out) of carrying out this write order, sends to bus;
2, bus sends to slave with what master sent out with imitating signal according to the write address that master sends out;
3, salve receive that master sends out after imitate signal, if agree to carry out write operation, then receive with imitating signal to the bus feedback;
4, bus interface receives that the tranmitting data register enable signal is opened clock after imitate signal, and bus can begin the data A0 that will receive from master, A1, and A2, A3 etc. send to salve according to clock signal;
5, when master receives last valid data of source end transmission, generate data and receive signal, namely the OK signal feedback is to bus, and the expression data receive, and last bus generation is closed clock signal and clock signal is closed.
Preferably, because the present invention adopts the data communication between the bus mode realization IP kernel, wherein, the AMBA bus specification of employing is to obtain one of interconnect standard of extensively supporting among the SOC (system on a chip) SoC that uses always, has greatly promoted the development of SOC (system on a chip) SoC design.2003, the AMBA2.0AHB standard be convenient to integrated, be convenient on the basis of advantages such as expanding, ARM has expanded performance and the dirigibility of AMBA technology, issued AMBA3.0AXI, accelerate design and checking based on the SOC (system on a chip) SoC of AMBA3.0AXI framework with this, and the AMBA3.0AXI agreement has obtained the support of many companies, this agreement is made significant improvement such as out of order emission, out of order return data, bus bandwidth is farthest taken full advantage of, and can satisfy the demand of high-performance SOC (system on a chip) SoC design.The numerous characteristics of AMBA3.0AXI makes it be fit to become sub-micron interconnection system at a high speed of future generation.For adapting to SOC (system on a chip) SoC of future generation design, the AMBA3.0AXI agreement is fit to high bandwidth, low delay design, supports high frequencies of operation and need not complicated bridging and connect, and has the AMBA2.0 system to be connected simply with oneself, and its interconnection architecture realization is flexible.Because it is interconnected that all IP kernels on the chip all pass through bus, bus requirements is supported high frequencies of operation simultaneously, therefore bus is carried out in good time Clock gating and operates and just can greatly reduce the clock power consumption of dynamically overturning.
Need to prove, for method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the application is not subjected to the restriction of described sequence of movement, because according to the application, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action might not be that the application is necessary.
With reference to Fig. 3, show the structured flowchart that a kind of SOC (system on a chip) SoC of the present invention writes the device embodiment of data, be with the clock signal that comprises of gate among the described SOC (system on a chip) SoC, described device specifically can comprise as lower module:
Write order receiver module 201 is used for write order and destination end address that the reception sources end sends;
Write order sending module 202 is used for according to the address of described destination end described write order being sent to destination end;
In a preferred embodiment of the present invention, described clock opening module 203 can comprise following submodule:
Approval signal receives submodule, is used for the signal of the described write order of agreement that the receiving target end returns;
Enable signal generates submodule, is used for generating the clock enable signal according to the signal of the described write order of described agreement;
Clock enables submodule, is used for opening clock signal according to described clock enable signal.
Write data module 204, be used for writing described destination end according to the data that the described source end that described clock signal will receive sends;
In a preferred embodiment of the present invention, described device can also comprise as lower module:
Source end useful signal receiver module is used for receiving the effective signal of data that described source end sends according to the described data of sending;
Destination end useful signal module is used for receiving the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
In a preferred embodiment of the present invention, described device can also comprise as lower module:
The normal writing module of destination end is used for receiving that described destination end returns whether normally writes the signal of the data that described source end sends.
In a preferred embodiment of the present invention, described clock closing module can comprise following submodule:
Final data receives submodule, is used for receiving last data that described source end sends and is sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
The signal that finishes receives submodule, and the data of sending for the described destination end of reception receive signal;
Shutdown signal generates submodule, is used for receiving signal according to described data and generates the clock shutdown signal;
Clock closes closed submodule, is used for closing clock signal according to described clock shutdown signal.
For device embodiment shown in Figure 3, because it is similar substantially to the method embodiment that Fig. 1 shows, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
Those skilled in the art should understand that the application's embodiment can be provided as method, device or computer program.Therefore, the application can adopt complete hardware embodiment, complete software embodiment or in conjunction with the form of the embodiment of software and hardware aspect.And the application can adopt the form of the computer program of implementing in one or more computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) that wherein include computer usable program code.
The application is that reference is described according to process flow diagram and/or the block scheme of method, equipment (system) and the computer program of the embodiment of the present application.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or the block scheme and/or square frame and process flow diagram and/or the block scheme and/or the combination of square frame.Can provide these computer program instructions to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out by the processor of computing machine or other programmable data processing device produce to be used for the device of the function that is implemented in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, make the instruction that is stored in this computer-readable memory produce the manufacture that comprises command device, this command device is implemented in the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing device, make and carry out the sequence of operations step producing computer implemented processing at computing machine or other programmable devices, thereby be provided for being implemented in the step of the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame in the instruction that computing machine or other programmable devices are carried out.
Although described the application's preferred embodiment, in a single day those skilled in the art get the basic creative concept of cicada, then can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the application's scope.
At last, also need to prove, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having under the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
More than a kind of SOC (system on a chip) SoC provided by the present invention is write method and the device of data, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a SOC (system on a chip) SoC writes the method for data, it is characterized in that comprise the clock signal of being with gate among the described SOC (system on a chip) SoC, described method comprises:
The write order that the reception sources end sends and destination end address;
Address according to described destination end is sent to destination end with described write order;
Receive the signal of the described write order of agreement that described destination end returns and open clock signal;
The data that the described source end that will receive according to described clock signal sends write described destination end;
When receiving and sending last data that described source end sends to destination end, close described clock signal.
2. method according to claim 1 is characterized in that, after the data that the described described source end that will receive according to clock signal sends write the step of described destination end, also comprises:
Receive the effective signal of data that described source end sends according to the described data of sending;
Receive the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
3. method according to claim 1 and 2 is characterized in that, after the data that the described source end that will receive according to described clock signal sends write the step of described destination end, also comprises:
The signal that whether normally writes the data that described source end sends that receives that described destination end returns.
4. method according to claim 1 is characterized in that, the signal of the described write order of agreement that described receiving target end returns and the step of opening clock signal comprise:
The signal of the described write order of agreement that the receiving target end returns;
Signal according to the described write order of described agreement generates the clock enable signal;
Open clock signal according to described clock enable signal.
5. according to claim 1 or 4 described methods, it is characterized in that described when receiving and sending last data that described source end sends to destination end, the step of closing described clock signal comprises:
Receive last data that described source end sends and be sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
Receive the data that described destination end sends and receive signal;
Receive signal according to described data and generate the clock shutdown signal;
Close clock signal according to described clock shutdown signal.
6. a SOC (system on a chip) SoC writes the device of data, it is characterized in that comprise the clock signal of being with gate among the described SOC (system on a chip) SoC, described device comprises:
The write order receiver module is used for write order and destination end address that the reception sources end sends;
The write order sending module is used for according to the address of described destination end described write order being sent to destination end;
The clock opening module be used for to receive the signal of the described write order of agreement that described destination end returns and opens clock signal;
Write data module, be used for writing described destination end according to the data that the described source end that described clock signal will receive sends;
The clock closing module is used for when reception and when sending last data that described source end sends to destination end, closes described clock signal.
7. device according to claim 6 is characterized in that, also comprises:
Source end useful signal receiver module is used for receiving the effective signal of data that described source end sends according to the described data of sending;
Destination end useful signal module is used for receiving the effective signal of data that data that described destination end sends according to the described source end that writes are sent.
8. according to claim 6 or 7 described devices, it is characterized in that, also comprise:
The normal writing module of destination end is used for receiving that described destination end returns whether normally writes the signal of the data that described source end sends.
9. device according to claim 6 is characterized in that, described clock opening module comprises:
Approval signal receives submodule, is used for the signal of the described write order of agreement that the receiving target end returns;
Enable signal generates submodule, is used for generating the clock enable signal according to the signal of the described write order of described agreement;
Clock enables submodule, is used for opening clock signal according to described clock enable signal.
10. according to claim 6 or 9 described devices, it is characterized in that described clock closing module comprises:
Final data receives submodule, is used for receiving last data that described source end sends and is sent to destination end; Wherein, when destination end receives last data that the source end sends, generate data and receive signal and send;
The signal that finishes receives submodule, and the data of sending for the described destination end of reception receive signal;
Shutdown signal generates submodule, is used for receiving signal according to described data and generates the clock shutdown signal;
Clock closes closed submodule, is used for closing clock signal according to described clock shutdown signal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108009107B (en) * | 2017-07-20 | 2019-11-05 | 北京车和家信息技术有限责任公司 | Method, apparatus, storage medium and the system of data transmission |
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| US20050198458A1 (en) * | 2004-03-08 | 2005-09-08 | Samsung Electronics Co., Ltd. | Memory controller having a read-modify-write function |
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| CN1752894A (en) * | 2005-08-18 | 2006-03-29 | 复旦大学 | Dynamic power consumption management method in information safety SoC based on door control clock |
| CN102439535A (en) * | 2011-10-25 | 2012-05-02 | 深圳市海思半导体有限公司 | Method for reducing dynamic power dissipation and electronic device |
| CN102981992A (en) * | 2012-11-28 | 2013-03-20 | 中国人民解放军国防科学技术大学 | On-chip communication method and device of integrated circuit based on asynchronous structure |
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| CN1680930A (en) * | 2004-02-19 | 2005-10-12 | 三星电子株式会社 | System and controller with reduced bus utilization time |
| US20050198458A1 (en) * | 2004-03-08 | 2005-09-08 | Samsung Electronics Co., Ltd. | Memory controller having a read-modify-write function |
| CN1752894A (en) * | 2005-08-18 | 2006-03-29 | 复旦大学 | Dynamic power consumption management method in information safety SoC based on door control clock |
| CN102439535A (en) * | 2011-10-25 | 2012-05-02 | 深圳市海思半导体有限公司 | Method for reducing dynamic power dissipation and electronic device |
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