CN103247676B - Lateral diffused metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Lateral diffused metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN103247676B CN103247676B CN201210024752.2A CN201210024752A CN103247676B CN 103247676 B CN103247676 B CN 103247676B CN 201210024752 A CN201210024752 A CN 201210024752A CN 103247676 B CN103247676 B CN 103247676B
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Abstract
The invention discloses a lateral diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof. The lateral diffused metal oxide semiconductor field effect transistor comprises a substrate, a deep trap formed in the substrate, a shallow trap formed on the deep trap, a groove formed by etching the shallow trap and the deep trap with partial thickness, a drain electrode formed in the shallow trap, grid electrodes formed in the groove and positioned on both sides of the drain electrode, a source electrode formed in the deep trap and under the grid electrodes, wherein the doping types of the deep trap and the shallow trap are opposite; and the doping types of the drain electrode and the source electrode are the same as the doping type of the shallow trap; and the doping densities of the drain electrode and the source electrode are larger than the doping density of the shallow trap. The lateral diffused metal oxide semiconductor field effect transistor provided by the invention reduces ON resistance and improves ON current, thereby effectively improving the driving ability of a device.
Description
Technical field
The present invention relates to IC manufacturing field, more particularly to a kind of LDMOS field effect
(laterally diffused MOSEFT) and its manufacture method should be managed.
Background technology
LDMOS is widely adopted due to being easier compatible with CMOS technology.Compared with MOS transistor, LDMOS is at some
In terms of Primary Component characteristic, such as have in terms of gain, the linearity, switch performance, heat dispersion and reduction series etc. obvious
Advantage.Thus be widely used in high-voltage power integrated circuit, meet high pressure resistant, realize the requirement of the aspects such as Power Control.
In order to improve LDMOS breakdown voltages, increase output, employ various improved technologies, such as drift region
Varying doping, super-junction and surface form G blood pressure lowering layer technologies etc., most common of which and simple and effective process is just
It is that drift region is set between source-drain electrode, the presence of drift region can improve breakdown voltage.With specific reference to shown in Fig. 1, Fig. 1 is P
The profile of type LDMOS, p-type LDMOS include：The source electrode 11 of P type substrate 10, N+ and drain electrode 12, between source-drain electrode
The drift region 13 of N-type, and the grid 14 on substrate active area.Due to the presence of drift region 13, drain electrode can be improved
Resistance to voltage levels, exactly because but the also presence of drift region 13, the series resistance between source electrode 11 and drain electrode 12 is increased, is reduced
Source electrode 11 as indicated by the dashed arrow in fig. 1 have impact on the driving force of device to the ON state current Ion of drain electrode 12.
The content of the invention
It is an object of the invention to provide a kind of LDMOS device, effectively to reduce the ON resistance of device, improves ON state electricity
Stream, boost device driving force.
To reach above-mentioned purpose, the LDMOS device of the present invention, including：
Substrate；
The deep trap being formed in the substrate and the shallow well being formed on the deep trap, the doping of the deep trap and shallow well
Type is contrary；
Etch the groove of the deep trap formation of the shallow well and segment thickness；
The drain electrode being formed in the shallow well；
In being formed at the groove and positioned at the grid of the drain electrode both sides；
The doping type of the source electrode being formed in the deep trap below the grid, the drain electrode and source electrode and the shallow well
Doping type is identical, and the doping content of the drain electrode and source electrode is more than the doping content of the shallow well.
Optionally, in described LDMOS device, the deep trap is p-well, and the shallow well is N traps.
Optionally, in described LDMOS device, the deep trap is N traps, and the shallow well is p-well.
Optionally, in described LDMOS device, described drain electrode thickness range is 50nm~80nm.
Optionally, in described LDMOS device, described shallow well thickness range is 20nm~250nm.
The present invention also provides a kind of manufacture method of the LDMOS device, including：
Substrate is provided；
Deep trap and shallow well are sequentially formed in the substrate；
Cushion and mask layer are sequentially formed over the substrate；
The deep trap for etching the shallow well and segment thickness forms groove；
Sealing coat is formed in the bottom of the groove and side wall；
Remove the sealing coat of the bottom portion of groove；
Gate oxide and polysilicon membrane are sequentially formed on the groove and mask layer；
Etch the gate oxide and polysilicon membrane to form grid in the groove；
Etching removes cushion and sealing coat on the shallow well；
Carry out ion implanting and drain electrode is formed in the shallow well, and in the deep trap below the grid, form source electrode, institute
The doping type for stating drain electrode and source electrode is identical with the doping type of the shallow well, and the doping content of the drain electrode and source electrode is more than
The doping content of the shallow well.
Optionally, in the manufacture method of the LDMOS device, sequentially form in the substrate deep trap and shallow well it
Afterwards, also include：Cushion and mask layer are sequentially formed over the substrate.
Optionally, in the manufacture method of the LDMOS device, sequentially form in the substrate deep trap and shallow well it
Before, also include：Cushion and mask layer are sequentially formed over the substrate.
Optionally, in the manufacture method of the LDMOS device, the cushion is silicon oxide, and the mask layer is nitrogen
SiClx.
Optionally, in the manufacture method of the LDMOS device, the thickness of the mask layer is more than the thickness of cushion.
Optionally, in the manufacture method of the LDMOS device, in the etch step for forming groove, etching is gone
The thickness range of the deep trap for removing is 50nm~200nm.
Optionally, in the manufacture method of the LDMOS device, include the step of formation grid in the groove：
The bottom of the groove and side wall form sealing coat；Remove the sealing coat of the bottom portion of groove；On the groove and mask layer
Sequentially form gate oxide and polysilicon membrane；Etch the gate oxide and polysilicon membrane to form grid in the groove
Pole.
Compared with prior art, the grid of LDMOS of the invention is located at the both sides of drain electrode, and source electrode is formed under the grid
Side deep trap in, i.e., source electrode and drain electrode in grid both sides vertical distribution by way of, make the resistance between source-drain electrode by existing
The series system of technology changes into parallel way, makes the resistance between source-drain electrode be changed into original 1/2, improves ON state current,
So as to effectively improve the driving force of device.
Description of the drawings
Profiles of the Fig. 1 for the LDMOS of prior art；
Profiles of the Fig. 2 for the LDMOS of one embodiment of the invention；
Profiles of Fig. 3-Fig. 8 for device in each step of LDMOS manufacture methods of one embodiment of the invention；
ON state current schematic diagrams of the Fig. 9 for one embodiment of the invention LDMOS.
Specific embodiment
To become apparent the purpose of the present invention, feature, below in conjunction with the accompanying drawings the specific embodiment of the present invention is done
Further instruction.
Fig. 2 is the profile of the LDMOS of one embodiment of the invention, and the LDMOS device includes：
Substrate 200；
The shallow well 220 on deep trap 210 and the deep trap 210 in the substrate 200, the deep trap 210 and shallow well
220 doping type is contrary；
Etch the groove 300 of the formation of deep trap 210 of the shallow well 220 and segment thickness；
Drain electrode 221 in the shallow well 220；
In the groove 300 and positioned at the grid 140 of 221 both sides of the drain electrode；And
Source electrode 211 in deep trap below the grid 140, it is described drain electrode 221 and source electrode 211 doping type with it is described
The doping type of shallow well 220 is identical, and the doping content of the drain electrode 221 and source electrode 211 is dense more than the doping of the shallow well 220
Degree.
Below as a example by forming N-type LDMOS, the manufacture method of LDMOS device of the present invention is discussed in detail with reference to Fig. 3 to Fig. 8,
The manufacture method of LDMOS device of the present invention is comprised the following steps：
As shown in figure 3, providing substrate 200 first, and ion implanting twice is carried out to the substrate 200, it is preferable that first
Secondary ion is injected to vertical ion injection, and injection ion is boron or boron fluoride, and Implantation Energy is 10kev~200kev, is injected
Dosage is 1012cm-2~1014cm-2, to form deep trap 210, second ion implanting is similarly vertical ion injection, injects ion
For phosphorus or arsenic, Implantation Energy is 10kev~100kev, and implantation dosage is 1012cm-2~1014cm-2, to form shallow well 220.Institute
The thickness range for stating deep trap is 200nm~1000nm, and the thickness range of the shallow well is 100nm~300nm.
Then, as shown in figure 4, cushion 160 and mask layer 170 are sequentially formed on the substrate 200.In this enforcement,
Described cushion 160 is made up of silicon oxide, and described mask layer 170 is made up of silicon nitride, it is preferred that described mask layer
170 thickness is greater than the thickness of cushion 160, this is because the effect of the cushion 160 is to solve mask layer 170 and lining
The excessive problem of stress between bottom 200, therefore relatively thin i.e. achievable this purpose of thickness of the cushion 160, and it is described
Mask layer 170 plays a part of hard mask during subsequent etching, therefore the thickness of the mask layer 170 larger is advisable.This
In embodiment, the thickness range 2nm~100nm of the cushion 160, the thickness range of described mask layer 170 is 10~
200nm。
It should be noted that the present embodiment be sequentially form deep trap and shallow well in the substrate is formed after, described
Cushion 160 and mask layer 170 are sequentially formed on substrate, it should be appreciated, however, that in other specific embodiments of the invention,
Can just form cushion 160 and mask layer 170, so before being formed in and deep trap and shallow well being sequentially formed in the substrate
Remain able to realize the purpose of the present invention.
Then, to the substrate 200, using photoetching and the method for etching, remove the part mask layer 170, cushion
160th, the deep trap 210 of shallow well 220 and segment thickness, forms groove 300 as shown in Figure 5.This step can have been etched by three times
Into first time etching technics is used for etching mask layer 170, and second etching technics is used to etch cushion 160, and third time is etched
Technique is used for the deep trap 210 for etching shallow well 220 and segment thickness, and above-mentioned three etching technics can be that wet etching can also
It is dry etch process, by adjusting the etch period or other etching conditions of third time etching technics (such as gas flow, quarter
Erosion liquid temp etc.) thickness of deep trap that removes of adjustable etching, specifically, 210 top surface of remaining deep trap and 300 bottom of groove
Between height H be 50nm~200nm.
Then, as shown in fig. 6, carrying out high-temperature thermal oxidation to the substrate 200, using high-temperature oxydation mode in the groove
300 bottom and side wall form sealing coat 120, and by the use of mask layer 170 as mask, remove groove using dry etch process
The sealing coat of 300 bottoms, so as to the side wall only in groove 300 retains sealing coat 120.
Then, it is sequentially depositing to form oxide layer and polysilicon membrane on the groove 300 and mask layer 170, then profit
Portion of oxide layer and polysilicon membrane are removed with photoetching and etching technics, afterwards, grid oxic horizon are formed in the groove 300
150 and grid 140.Subsequently, etching removes the mask layer 170 and cushion 160 on the shallow well 220, is formed as shown in Figure 7
Structure.
Then, as shown in figure 8, carrying out ion implanting to the substrate 200 and shallow well 220 by mask of grid 140, in institute
Source electrode 211 is formed in stating the deep trap 210 below grid 140, and drain electrode 221 is formed in the shallow well 220, the drain electrode 221
Thickness range 50nm~80nm, the doping type of the drain electrode 221 and source electrode 211 and the doping type phase of the shallow well 220
Together, and it is described drain electrode 221 and source electrode 211 doping content more than the shallow well 220 doping content.Preferably, form drain electrode
221 and the dosage of ion implanting of source electrode 211 be higher than the dosage of the ion implanting to form shallow well 220, to reach 221 Hes of drain electrode
Purpose of the doping content of source electrode 211 more than the doping content of the shallow well 220.In the present embodiment, the ion implanting is vertical
Straight ion implanting, the ion of injection is phosphorus or arsenic, and ion energy is 1kev~100kev, and implantation dosage is 1014cm-2~
1016cm-2。
So far, form LDMOS structure as shown in Figure 2.Compared with prior art, source electrode and drain electrode are vertical being distributed in
Grid both sides, the structure of source-drain electrode vertical distribution so that the resistance between source-drain electrode is changed by the series system of prior art
For parallel way, the resistance between source-drain electrode can be reduced to original 1/2.As shown in figure 9, which is the ON state electricity of LDMOS
Shown in flow diagram, because the series resistance between source-drain electrode is reduced to the 1/2 of prior art, can be by dotted arrow institute in figure
ON state current Ion between the source-drain electrode for showing brings up to 2 times of prior art, such that it is able to the driving energy of effective boost device
Power.
Said method is by taking N-type LDMOS as an example, it will be apparent to a skilled person that p-type LDMOS is only needed to
The dopant ion of opposite types is selected in the step of each ion implanting, the doping type of Each part can be conversely, herein not
Repeat again.
In sum, source electrode of the prior art and drain electrode is distributed horizontally to grid both sides, in order to improve breakdown potential
Pressure, is provided with drift region near drain region between source electrode and drain electrode, but the presence of drift region, also improve source-drain electrode it
Between serial resistance, reduce ON state current.The LDMOS device structure that the present invention is provided, source electrode and drain electrode are vertical distributions
In grid both sides, the structure of source-drain electrode vertical distribution so that the resistance between source-drain electrode is changed by the series system of prior art
It is changed into parallel way, the resistance between source-drain electrode can be reduced to the 1/2 of prior art, so as to improves opening between source-drain electrode
State electric current, effectively improves the driving force of device.
Obviously, those skilled in the art can carry out the spirit of various changes and modification without deviating from the present invention to invention
And scope.So, if these modifications of the present invention and modification belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to including including these changes and modification.
Claims (12)
1. a kind of transverse diffusion metal oxide semiconductor field effect pipe, including：
Substrate；
The deep trap being formed in the substrate and the shallow well for being formed on the deep trap and contacting with the deep trap, the depth
The doping type of trap and shallow well is contrary；
Etch the groove of the deep trap formation of the shallow well and segment thickness；
The drain electrode being formed in the shallow well；
In being formed at the groove and positioned at the grid of the drain electrode both sides；
The doping type of the source electrode being formed in the deep trap below the grid, the drain electrode and source electrode and the doping of the shallow well
Type is identical, and the doping content of the drain electrode and source electrode is more than the doping content of the shallow well.
2. transverse diffusion metal oxide semiconductor field effect pipe as claimed in claim 1, it is characterised in that the deep trap is
P-well, the shallow well are N traps.
3. transverse diffusion metal oxide semiconductor field effect pipe as claimed in claim 1, it is characterised in that the deep trap is
N traps, the shallow well are p-well.
4. transverse diffusion metal oxide semiconductor field effect pipe as claimed in claim 1, it is characterised in that described drain electrode
Thickness range is 50nm~80nm.
5. transverse diffusion metal oxide semiconductor field effect pipe as claimed in claim 1, it is characterised in that described shallow well
Thickness range is 20nm~250nm.
6. a kind of manufacture method of transverse diffusion metal oxide semiconductor field effect pipe, including：
Substrate is provided；
The shallow well for deep trap being sequentially formed in the substrate and being contacted with the deep trap；
The deep trap for etching the shallow well and segment thickness forms groove；
Grid is formed in the groove；
Carry out ion implanting and drain electrode is formed in the shallow well, and in the deep trap below the grid, form source electrode, the leakage
The doping type of pole and source electrode is identical with the doping type of the shallow well, and the doping content of the drain electrode and source electrode is more than described
The doping content of shallow well.
7. method as claimed in claim 6, it is characterised in that after sequentially forming deep trap and shallow well in the substrate, also
Including：Cushion and mask layer are sequentially formed over the substrate.
8. method as claimed in claim 6, it is characterised in that before sequentially forming deep trap and shallow well in the substrate, also
Including：Cushion and mask layer are sequentially formed over the substrate.
9. method as claimed in claim 7 or 8, it is characterised in that the cushion is silicon oxide, the mask layer is nitridation
Silicon.
10. method as claimed in claim 7 or 8, it is characterised in that thickness of the thickness of the mask layer more than cushion.
11. methods as claimed in claim 6, it is characterised in that in the etch step of the formation groove, etch the depth for removing
The thickness range of trap is 50nm~200nm.
12. methods as claimed in claim 8, it is characterised in that the step of grid is formed in the groove includes：
Sealing coat is formed in the bottom of the groove and side wall；
Remove the sealing coat of the bottom portion of groove；
Gate oxide and polysilicon membrane are sequentially formed on the groove and mask layer；
Etch the gate oxide and polysilicon membrane to form grid in the groove.
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