CN103246309A - 基准电压产生装置 - Google Patents

基准电压产生装置 Download PDF

Info

Publication number
CN103246309A
CN103246309A CN2013100508457A CN201310050845A CN103246309A CN 103246309 A CN103246309 A CN 103246309A CN 2013100508457 A CN2013100508457 A CN 2013100508457A CN 201310050845 A CN201310050845 A CN 201310050845A CN 103246309 A CN103246309 A CN 103246309A
Authority
CN
China
Prior art keywords
type
reference voltage
mos transistor
voltage generator
channel doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013100508457A
Other languages
English (en)
Other versions
CN103246309B (zh
Inventor
吉野英生
小山内润
桥谷雅幸
广濑嘉胤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN103246309A publication Critical patent/CN103246309A/zh
Application granted granted Critical
Publication of CN103246309B publication Critical patent/CN103246309B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electromagnetism (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供基准电压产生装置，其具有平坦的温度特性。该基准电压产生装置具备：第一导电类型的耗尽型MOS晶体管(10)，其为了作为电流源发挥功能而进行连接并流过恒定电流；以及第一导电类型的增强型MOS晶体管(20)，其进行二极管连接，具有与耗尽型MOS晶体管(10)的迁移率大致相同的迁移率，基于恒定电流产生基准电压(VREF)，因为耗尽型NMOS晶体管(10)与增强型NMOS晶体管(20)的迁移率大致相同，所以它们的温度特性也大致相同，基准电压(VREF)的温度特性平坦。

Description

基准电压产生装置
技术领域
本发明涉及在半导体集成电路内产生基准电压的基准电压产生装置。
背景技术
采用图2说明在现有的基准电压产生装置中使用的电路。
为了作为电流源发挥功能而连接的耗尽型NMOS晶体管（D型NMOS）10向进行二极管连接的增强型NMOS晶体管（E型NMOS）20流入恒定电流。通过该恒定电流，在E型NMOS20中产生与各个晶体管的阈值电压以及尺寸相应的基准电压。这里，在D型NMOS10的栅极中掺杂有N型的杂质，在E型NMOS的栅极中掺杂有P型的杂质（例如，参照专利文献1（图2））。
专利文献1：日本特开昭59-200320号公报
近年来，在电子设备的高精度化方面取得了进步，与此相伴，在各个方面都要求控制该电子设备的IC的高精度化。例如，为了实现IC的电气特性的高精度化，要求即使温度发生变化，在IC内部，基准电压产生装置也能高精度地产生基准电压，即基准电压的温度特性变得更平坦。
发明内容
本发明是鉴于上述要求而完成的，其课题是提供具有更平坦的温度特性的基准电压产生装置。
本发明为了解决上述课题而采用如下的基准电压产生装置，其特征在于，在基准电压产生装置中具备：第一导电类型的耗尽型MOS晶体管，其为了作为电流源发挥功能而进行连接并流过恒定电流；以及第一导电类型的增强型MOS晶体管，其进行二极管连接，具有与上述耗尽型MOS晶体管的迁移率大致相同的迁移率，基于上述恒定电流产生基准电压。
在本发明中，因为第一导电类型的耗尽型NMOS晶体管与第一导电类型的增强型NMOS晶体管的迁移率大致相同，所以它们的温度特性也大致相同，基准电压的温度特性良好。
附图说明
图1是示出基准电压产生装置的剖面图的图。
图2是示出基准电压产生装置的等效电路的图。
标号说明
10耗尽型NMOS晶体管（D型NMOS）；20增强型NMOS晶体管（E型NMOS）；11、21栅极电极；12、22栅绝缘膜；13、23沟道掺杂区域；14、24源极；15、25漏极；16、26阱；29衬底。
具体实施方式
以下，参照附图来说明本发明的实施方式。
首先，采用图1所示的剖面图来说明基准电压产生装置的基本结构。
基准电压产生装置具备耗尽型NMOS晶体管（D型NMOS）10以及增强型NMOS晶体管（E型NMOS）20。D型NMOS10的栅极电极11以及源极14与基准电压产生端子连接，漏极15与电源端子连接。通过进行这样的连接，D型NMOS10作为电流源发挥作用。E型NMOS20的栅极电极21以及漏极25与基准电压产生端子连接，源极24与接地端子连接。即，进行二极管连接的E型NMOS20与D型NMOS10串联连接。因此，等效电路为图2所示的电路图，与现有电路等效。
为了形成D型NMOS10，首先在P型的衬底29的表面上形成P型的阱16。然后，在阱16的表面上形成N型的沟道掺杂区域13。接着，在沟道掺杂区域13上形成栅绝缘膜12。然后，在栅绝缘膜12上形成N型的栅极电极11。另外，以隔着栅极电极11以及栅绝缘膜12下面的沟道掺杂区域13的方式，在阱16的表面形成N型的源极14以及N型的漏极15。
D型NMOS10的栅极电极11的极性与源极14、漏极15的极性相同，形成为N型。由此，N型的栅极电极11与P型的阱16的功函数之差较大，施加衬底表面反转的方向的电场，所以D型NMOS10的阈值电压降低到D型NMOS10成为耗尽型的程度。此外，由于N型的沟道掺杂区域13，阈值电压降低，沟道形成在衬底内部，形成埋入沟道。这里，适当控制向栅极电极11以及沟道掺杂区域13的杂质注入，使D型NMOS10成为耗尽型。
为了形成E型NMOS20，首先在P型的衬底29的表面上形成P型的阱26。然后，在阱26的表面上形成N型的沟道掺杂区域23。接着，在沟道掺杂区域23上形成栅绝缘膜22。然后，在栅绝缘膜22上形成P型的栅极电极21。另外，以隔着栅极电极21以及栅绝缘膜22下面的沟道掺杂区域23的方式，在阱26的表面形成N型的源极24以及N型的漏极25。
E型NMOS20的栅极电极21的极性与源极24、漏极25的极性不同，形成为P型。由此，P型的栅极电极21与P型的阱26的功函数之差较小，施加空穴在衬底表面上蓄积的方向的电场，所以阈值变高。因此，为了适度地降低阈值，在P型的阱26的表面形成含有N型杂质的沟道掺杂区域23。这里，适当控制向栅极电极21以及沟道掺杂区域23的杂质注入，以使E型NMOS20成为增强型。
此外，衬底29不限于P型，也可以是N型。
为了作为电流源发挥功能而连接的D型NMOS10的源极14向进行二极管连接的E型NMOS20的漏极25流入恒定电流。通过该恒定电流，在E型NMOS20的漏极25（基准电压产生端子）产生基准电压。
接着，说明基准电压产生装置产生的基准电压VREF的温度特性。
这里，假定D型NMOS10的沟道掺杂区域13按照阱16的表面极性反转的程度进行沟道掺杂。在此情况下，沟道掺杂区域13与阱16的杂质极性不同，D型NMOS10为埋入沟道。另一方面，为了降低阈值，E型NMOS20在阱区域表面具有极性与阱26不同的含有N型杂质的沟道掺杂区域23，因此同样可认为是埋入沟道。
此时，在栅极杂质的极性不同的D型NMOS10以及E型NMOS20中，当相同地形成衬底29的表面以下的杂质的轮廓时，可期待产生深度相等的埋入沟道。伴随于此，可期待D型NMOS10与E型NMOS20的温度特性相同、基准电压VREF的温度特性良好。
但是，本发明的发明人经过多角度的实验等专心努力，结果发现了以下所示的现象。在D型NMOS10以及E型NMOS20中，因为栅极电极的杂质的极性不同，所以栅极电极与衬底之间的功函数也不同。此外，用于沟道导通的栅极电压（阈值电压）也不同，沟道导通时的施加给沟道掺杂区域的电场也不同。具体地说，E型NMOS20的阈值电压高于D型NMOS10的阈值电压，相应地，施加给E型NMOS20的沟道的电场变大。因此，在D型NMOS10中，载流子在衬底29的表面以下的区域内流动，在E型NMOS20中，载流子在衬底29的表面附近流动。即，可知D型NMOS10是埋入沟道型、E型NMOS20不是埋入沟道型。这意味着由于E型NMOS20的载流子受到界面态的影响，所以E型NMOS20的迁移率变低，D型NMOS10与E型NMOS20的温度特性不相同。即，基准电压VREF的温度特性不良。
因此，本发明通过在D型NMOS10以及E型NMOS20中适当控制栅极的杂质浓度、栅绝缘膜的材质、栅绝缘膜的膜厚和衬底29的表面以下的杂质轮廓等，使迁移率相同。由此，能够使D型NMOS10与E型NMOS20的温度特性相同，使基准电压VREF的温度特性良好。这里，作为迁移率，可采用能够根据晶体管的电流电压特性容易地求出的迁移率。
【实施例1】
适当选择栅氧化膜22以及栅氧化膜12的材质，使E型NMOS20的栅氧化膜22的介电常数高于D型NMOS10的栅氧化膜12的介电常数。于是，相应地，E型NMOS20的栅氧化膜电容变大，施加给沟道的电场变小，所以迁移率变高。考虑到该效果，当D型NMOS10与E型NMOS20的迁移率大致相同时，它们的温度特性也大致相同，能够使基准电压VREF的温度特性平坦。
【实施例2】
将E型NMOS20的栅氧化膜22形成得比D型NMOS10的栅氧化膜12薄。于是，相应地，E型NMOS20的栅氧化膜电容变大，施加给沟道的电场变小，所以迁移率变高。考虑到该效果，当D型NMOS10与E型NMOS20的迁移率大致相同时，它们的温度特性也大致相同，能够使基准电压VREF的温度特性平坦。
【实施例3】
E型NMOS20的沟道掺杂区域23的杂质为磷，D型NMOS10的沟道掺杂区域13的杂质为砷。于是，因为磷的原子半径小于砷的原子半径，所以磷的平均自由程比砷的平均自由程长，E型NMOS20的迁移率相应地变高。考虑到该效果，当D型NMOS10与E型NMOS20的迁移率大致相同时，它们的温度特性也大致相同，能够使基准电压ⅤREF的温度特性平坦。
此外，只要沟道掺杂区域23的杂质主要是磷、沟道掺杂区域13的杂质主要是砷即可。例如，也可以使沟道掺杂区域23的杂质为磷，沟道掺杂区域13的杂质为砷以及磷。另外，也可以使沟道掺杂区域23的杂质为砷以及磷，沟道掺杂区域13的杂质为砷。另外，也可以使沟道掺杂区域23的杂质为砷以及磷，沟道掺杂区域13的杂质也为砷以及磷。此时，通过适当控制掺杂的砷以及磷的量，使D型NMOS10与E型NMOS20的迁移率相同。
另外，也可适当分割沟道掺杂区域23，设置掺杂磷的磷区域和掺杂砷的砷区域。另外，也可适当分割沟道掺杂区域13。另外，也可适当分割沟道掺杂区域23以及沟道掺杂区域13双方。也可在栅极长度方向上分割沟道掺杂区域23以及沟道掺杂区域13，还可在栅极宽度方向上分割沟道掺杂区域23以及沟道掺杂区域13。此时，通过适当设置磷区域以及砷区域，使D型NMOS10与E型NMOS20的迁移率相同。
【实施例4】
将E型NMOS20的阱26的杂质浓度形成得比D型NMOS10的阱16的杂质浓度低。于是，相应地，E型NMOS20的沟道中的杂质散射的影响减小，迁移率变高。考虑到此效果，当D型NMOS10与E型NMOS20的迁移率大致相同时，它们的温度特性也大致相同，能够使基准电压VREF的温度特性平坦。
以上说明的实施方式可适当进行组合。

Claims (6)

1.一种基准电压产生装置，其特征在于，该基准电压产生装置具备：
流过恒定电流的第一导电类型的耗尽型MOS晶体管；以及
第一导电类型的增强型MOS晶体管，其进行二极管连接，具有与所述耗尽型MOS晶体管的迁移率相同的迁移率，产生基于所述恒定电流的基准电压。
2.根据权利要求1所述的基准电压产生装置，其中，
所述增强型MOS晶体管的栅氧化膜的介电常数高于所述耗尽型MOS晶体管的栅氧化膜的介电常数。
3.根据权利要求1所述的基准电压产生装置，其中，
所述增强型MOS晶体管的栅氧化膜比所述耗尽型MOS晶体管的栅氧化膜薄。
4.根据权利要求1所述的基准电压产生装置，其中，
所述增强型MOS晶体管的沟道掺杂区域的主杂质的原子半径小于所述耗尽型MOS晶体管的沟道掺杂区域的主杂质的原子半径。
5.根据权利要求4所述的基准电压产生装置，其中，
所述增强型MOS晶体管的沟道掺杂区域的主杂质是磷，
所述耗尽型MOS晶体管的沟道掺杂区域的主杂质是砷。
6.根据权利要求1所述的基准电压产生装置，其中，
所述增强型MOS晶体管的阱的杂质浓度比所述耗尽型MOS晶体管的阱的杂质浓度小。
CN201310050845.7A 2012-02-13 2013-02-08 基准电压产生装置 Expired - Fee Related CN103246309B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-028733 2012-02-13
JP2012028733A JP5959220B2 (ja) 2012-02-13 2012-02-13 基準電圧発生装置

Publications (2)

Publication Number Publication Date
CN103246309A true CN103246309A (zh) 2013-08-14
CN103246309B CN103246309B (zh) 2017-07-18

Family

ID=48925883

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310050845.7A Expired - Fee Related CN103246309B (zh) 2012-02-13 2013-02-08 基准电压产生装置

Country Status (5)

Country Link
US (1) US9213415B2 (zh)
JP (1) JP5959220B2 (zh)
KR (1) KR102030982B1 (zh)
CN (1) CN103246309B (zh)
TW (1) TWI550771B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104007778A (zh) * 2013-02-22 2014-08-27 精工电子有限公司 基准电压产生电路
CN104035472A (zh) * 2014-06-24 2014-09-10 吴江圣博瑞信息科技有限公司 一种全cmos参考电压源产生电路
CN104571251A (zh) * 2013-10-28 2015-04-29 精工电子有限公司 基准电压产生装置
CN105929886A (zh) * 2015-02-26 2016-09-07 精工半导体有限公司 基准电压电路以及电子设备
CN107153441A (zh) * 2017-07-10 2017-09-12 长沙方星腾电子科技有限公司 一种基准电压生成电路
CN110119178A (zh) * 2018-02-06 2019-08-13 艾普凌科有限公司 基准电压产生装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013125163A1 (ja) * 2012-02-24 2013-08-29 パナソニック株式会社 基準電圧源回路
US20150200270A1 (en) * 2014-01-16 2015-07-16 Globalfoundries Inc. Field effect transistors for high-performance and low-power applications
TWI595542B (zh) * 2016-12-08 2017-08-11 旺宏電子股份有限公司 半導體結構
JP6805049B2 (ja) * 2017-03-31 2020-12-23 エイブリック株式会社 基準電圧発生装置
TWI634661B (zh) * 2017-07-31 2018-09-01 旺宏電子股份有限公司 半導體結構
CN107678480A (zh) * 2017-11-13 2018-02-09 常州欣盛微结构电子有限公司 一种用于低功耗数字电路的线性电压管理器
US10782723B1 (en) 2019-11-01 2020-09-22 Analog Devices International Unlimited Company Reference generator using fet devices with different gate work functions

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446383A (en) * 1982-10-29 1984-05-01 International Business Machines Reference voltage generating circuit
JP2002110917A (ja) * 2000-09-27 2002-04-12 Ricoh Co Ltd 基準電圧発生回路及びその出力値調整方法並びに電源装置
US20020113642A1 (en) * 2000-10-30 2002-08-22 Masuhide Ikeda Reference voltage circuit
US20020163385A1 (en) * 2000-10-13 2002-11-07 Seiko Epson Corporation Operation amplification circuit, constant voltage circuit and reference voltage circuit
US20070057291A1 (en) * 2005-08-31 2007-03-15 Hideyuki Aota Reference voltage generation circuit, and constant voltage circuit using the reference voltage generation circuit
CN101331437A (zh) * 2006-03-31 2008-12-24 株式会社理光 基准电压产生电路及使用其的供电设备
CN101673743A (zh) * 2008-09-10 2010-03-17 精工电子有限公司 半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200320A (ja) 1983-04-27 1984-11-13 Hitachi Ltd 基準電圧発生回路
JP2007294846A (ja) * 2006-03-31 2007-11-08 Ricoh Co Ltd 基準電圧発生回路及びそれを用いた電源装置
JP2010108419A (ja) 2008-10-31 2010-05-13 Toshiba Corp 基準電圧発生回路およびそれを用いたレギュレータ

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446383A (en) * 1982-10-29 1984-05-01 International Business Machines Reference voltage generating circuit
JP2002110917A (ja) * 2000-09-27 2002-04-12 Ricoh Co Ltd 基準電圧発生回路及びその出力値調整方法並びに電源装置
US20020060600A1 (en) * 2000-09-27 2002-05-23 Naohiro Ueda Reference voltage generation circuit having reduced temperature sensitivity, an output adjusting method, and an electrical power source
US20020163385A1 (en) * 2000-10-13 2002-11-07 Seiko Epson Corporation Operation amplification circuit, constant voltage circuit and reference voltage circuit
US20020113642A1 (en) * 2000-10-30 2002-08-22 Masuhide Ikeda Reference voltage circuit
US6628161B2 (en) * 2000-10-30 2003-09-30 Seiko Epson Corporation Reference voltage circuit
US20070057291A1 (en) * 2005-08-31 2007-03-15 Hideyuki Aota Reference voltage generation circuit, and constant voltage circuit using the reference voltage generation circuit
CN101331437A (zh) * 2006-03-31 2008-12-24 株式会社理光 基准电压产生电路及使用其的供电设备
CN101673743A (zh) * 2008-09-10 2010-03-17 精工电子有限公司 半导体器件

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
叶以正，来逢昌: "《集成电路工程基础》", 31 May 2011, 清华大学出版社 *
王占国，陈立泉，屠海令: "《信息功能材料手册 上》", 30 June 2009, 化学工业出版社 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104007778A (zh) * 2013-02-22 2014-08-27 精工电子有限公司 基准电压产生电路
CN104007778B (zh) * 2013-02-22 2017-03-01 精工半导体有限公司 基准电压产生电路
CN104571251A (zh) * 2013-10-28 2015-04-29 精工电子有限公司 基准电压产生装置
CN104571251B (zh) * 2013-10-28 2017-10-20 精工半导体有限公司 基准电压产生装置
CN104035472A (zh) * 2014-06-24 2014-09-10 吴江圣博瑞信息科技有限公司 一种全cmos参考电压源产生电路
CN105929886A (zh) * 2015-02-26 2016-09-07 精工半导体有限公司 基准电压电路以及电子设备
CN105929886B (zh) * 2015-02-26 2018-10-16 艾普凌科有限公司 基准电压电路以及电子设备
CN107153441A (zh) * 2017-07-10 2017-09-12 长沙方星腾电子科技有限公司 一种基准电压生成电路
CN110119178A (zh) * 2018-02-06 2019-08-13 艾普凌科有限公司 基准电压产生装置

Also Published As

Publication number Publication date
US9213415B2 (en) 2015-12-15
CN103246309B (zh) 2017-07-18
JP5959220B2 (ja) 2016-08-02
KR20130093023A (ko) 2013-08-21
JP2013164808A (ja) 2013-08-22
TW201344847A (zh) 2013-11-01
TWI550771B (zh) 2016-09-21
US20130207636A1 (en) 2013-08-15
KR102030982B1 (ko) 2019-10-11

Similar Documents

Publication Publication Date Title
CN103246309A (zh) 基准电压产生装置
US10229993B2 (en) LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods
US20210391463A1 (en) High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof
US9496335B2 (en) Super junction semiconductor device and method for manufacturing the same
CN104571251B (zh) 基准电压产生装置
US9059329B2 (en) Power device with integrated Schottky diode and method for making the same
CN102832219B (zh) 一种集成可调热敏电阻的自反馈线性恒流器
US10700061B2 (en) Semiconductor device comprising a first transistor and a second transistor
US20130161740A1 (en) Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same
KR101966531B1 (ko) 터널링 전계효과 트랜지스터
US11024712B2 (en) Semiconductor devices and methods for forming semiconductor devices
CN104638021B (zh) 一种横向恒流二极管及其制造方法
JP6192163B2 (ja) 半導体回路装置の製造方法および半導体回路装置
JP5594753B2 (ja) トランジスタ及び半導体装置
JP6095927B2 (ja) 半導体集積回路装置
CN104638022B (zh) 一种soi横向恒流二极管及其制造方法
JP6718612B2 (ja) ＳｉＣ接合型電界効果トランジスタ及びＳｉＣ相補型接合型電界効果トランジスタ
Binbin et al. The complete semiconductor transistor and its incomplete forms
Balachandran et al. MOSFET: Device Physics and Operation
KR20130132085A (ko) 딥 트렌치 필링을 이용한 슈퍼 접합 전력 모스펫
Casolino et al. DESIGN CRITERIA OF LDD MOSFET DEVICES
Mazurak et al. Investigation of current-voltage characteristics of the transistor structures with double-potential barrier DBMOS
Burtone Electrical Characterization of Organic Devices and Solar Cells by Impedance Spectroscopy
Sharma Junction Less Semiconductor Components using Nano Wires
TW201503362A (zh) 垂直通道式之接面場效電晶體

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160406

Address after: Chiba County, Japan

Applicant after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba County, Japan

Applicant before: Seiko Instruments Inc.

GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: DynaFine Semiconductor Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170718