CN103236122A - Tax control verification card based on PCI (peripheral component interconnect) bus interface chip and CPLD (complex programmable logic device) chips - Google Patents
Tax control verification card based on PCI (peripheral component interconnect) bus interface chip and CPLD (complex programmable logic device) chips Download PDFInfo
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Abstract
The invention discloses a tax control verification card based on a PCI (peripheral component interconnect) bus interface chip and CPLD (complex programmable logic device) chips, and belongs to the technical field of information security. The tax control verification card comprises a general control CPLD chip, eight control CPLD chips, eight cryptographic algorithm chips, eight double-port RAM (random access memory) chips, the PCI bus interface chip, a PCI configuration chip, a crystal oscillator and a PCI bus. The general control CPLD chip is connected with the eight control CPLD chips and controls the same. Each control CPLD chip is connected with one double-port RAM chip which is connected with one cryptographic algorithm chip. The general control CPLD chip is connected with the PCI bus interface chip which is connected with the PCI configuration chip. The crystal oscillator is used for providing operating master frequency for the eight cryptographic algorithm chips. The PCI bus interface chip is connected with the PCI bus. By the aid of the tax control verification card, correctness of security codes of invoices can be effectively verified, and capacities of reliable storage and tamper prevention of data are provided.
Description
Technical field
The present invention relates to a kind of information security field technology, specifically a kind of tax control validity check card based on pci bus interface chip and CPLD chip.
Background technology
The taxpayer is in the production and operation process, and employed when opening invoice to possess the product that the tax authority can monitor taxable income be tax-controlling device.The security code of invoice generates at random, be that the taxpayer is when using the tax-controlling device printed invoice, the tax control IC-card can produce a specific security code according to calculation of parameter such as the amount of money of invoice, tax-controlling device number, invoice number, the dates of making out an invoice, and is printed on the invoice.
There are problems such as tax scams, false invoice spread unchecked, administrative vulnerability at present in the tax control industry.If can on the security code of invoice, strict control veritify, then can improve the antifalsification of invoice.
Summary of the invention
Technical assignment of the present invention provides a kind of correctness that can effectively veritify the security code of invoice, possess simultaneously data reliable memory, prevent the function of distorting, can satisfy the tax control validity check card based on pci bus interface chip and CPLD chip of the requirement of tax authority's managing bill.
Technical assignment of the present invention realizes in the following manner, and this tax control validity check card comprises master control CPLD chip, 8 control CPLD chips, 8 cryptographic algorithm chips, 8 dual port RAM chips, pci bus interface chip, PCI configuring chip, crystal oscillator, pci bus; Master control CPLD chip connects 8 control of control CPLD chip; 8 every of control CPLD chips all are connected with 1 dual port RAM chip, and the dual port RAM chip is connected with 1 cryptographic algorithm chip again; Master control CPLD chip connects the pci bus interface chip, and the pci bus interface chip connects the PCI configuring chip; Crystal oscillator provides the work dominant frequency of 8 cryptographic algorithm chips; The pci bus interface chip connects pci bus.
Master control CPLD chipAdopt the EPM7128SLC84 model chip of the U.S. MAX of altera corp 7000 series, the work of each chip module of master control CPLD chip tax control validity check card, the conversion of the address space of realizing this tax control validity check card by programming and the processing of 8 control CPLD chip interrupt and the chip selection signal that produces 8 dual port RAM chips.
The total number of pins 84 of EPM7128SLC84 model chip, wherein the IO number of pins 68, contain 2500 doors, 128 macroelements, 8 logic array blocks; This chip is the control core of tax control validity check card, realizes following function by programming in design:
(1) provide tax control validity check card IO the address 0～3 in space, wherein:
Unique card number of the corresponding tax control validity check card in 0～2 address, driver is read unique card number that this address obtains a 24BIT;
0 address also is multiplexed with the general reset mouth of tax control validity check card, and driver writes data to this address reset the tax control validity check card, writes to make the tax control validity check card be in reset mode for the first time, writes to make the tax control validity check card be in normal condition for the second time;
3 addresses are the interrupt inquiry address of tax control validity check card, and driver is by reading the sequence number that this address obtains sending out in the tax control validity check card control CPLD chip that interrupts;
(2) to the internal memory address decoding, produce the chip selection signal of 8 dual port RAM chips.
Sheet control CPLD chipAll adopt the EPM7064SLC44 model chip of the MAX of U.S. altera corp 7000 series; 8 control CPLD chips are all by being connected of each self-corresponding dual port RAM chip realization and each self-corresponding cryptographic algorithm chip, and finish control to the cryptographic algorithm chip by Programmable Technology.
The total number of pins 44 of EPM7064SLC44 model chip, wherein the IO number of pins 36, contain 1250 doors, 64 macroelements, 4 logic array blocks; Major function is the work of control cryptographic algorithm chip.
In this tax control validity check card course of work, control CPLD chip imports packet in the corresponding dual port RAM chip successively, and corresponding cryptographic algorithm chip takes out packet and carries out computing from the dual port RAM chip; Treat again packet to be write back in the dual port RAM chip after the computing of cryptographic algorithm chip is finished, control packet that the CPLD chip finishes computing again this moment and upload to host computer and produce and interrupt, so far finish the control flow of a packet.Behind all packets of handling host computer, can veritify the correctness of the security code of an invoice by cycle control.
Sheet cryptographic algorithm chipAll adopt tax control special purpose system algorithm chip SSX12-A model chip, the cryptographic algorithm chip carries out encryption and decryption, the veritification computing of data according to the tax control cryptographic algorithm.
SSX12-A model chip is specifically designed to information security fields such as tax control, and function mainly contains and generates key, data encryption, deciphering, veritification payment cipher etc., effectively guarantees the security of data when the user concludes the business.Its principal feature is: every SSX12-A model chip all has separately independently ID number, and all crypto-operations are all finished in sheet, supports 3.3V or 5V duplex to make voltage, when the work dominant frequency is 12MHz, veritifies payment cipher speed greater than 140 times/second.
Sheet dual port RAM chipAll adopt the IDT7130 model chip of IDT company, every dual port RAM chip all is inputoutput buffers of the corresponding cryptographic algorithm chip that connects separately, the cryptographic algorithm chip corresponding with every dual port RAM chip and control CPLD chip by separately independently port control the read-write of this dual port RAM chip respectively.
IDT7130 model chip is that the static SRAM(Static Random of the twoport Access Memory static random of the high speed 1K * 8bit of IDT company product is handled internal memory), have high speed access speed and low in power consumption.
Bus Interface ChipAdopt the PLX9052 model chip of PLX company, the pci bus interface chip is used for the interface logic of realization and pci bus.
PLX9052 model chip is one 32 pci bus target interface circuit chips, low in energy consumption, adopt PQFP type 160 pin package, accord with PCI 2.1 standards, its local bus can be set to 8/16/32 bus by programming, and rate of data signalling can reach 132MB/s.The packet that host computer sends is by being transferred to the control module of 8 corresponding on tax control validity check card cryptographic algorithm chips in the pci bus interface chip.
Configuring chipAdopt the 93LC46B model eeprom chip of Microchip company, the PCI configuring chip is used for the PCI allocation Bus Interface Chip.
Its capacity of 93LC46B model eeprom chip is 1Kbit, and PDIP-8 encapsulates, and is used for storing the configuration information of pci bus interface chip.The tax control validity check card power at every turn back pci bus interface chip at first in the PCI configuring chip load configuration information carry out initialization.
Crystal oscillatorAdopt the active crystal oscillator of 12MHz, the working clock frequency of cryptographic algorithm chip is provided.
CPLD (Complex Programmable Logic Device) CPLD.
EEPROM (Electrically Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memo)--the storage chip that data are not lost after a kind of power down.
Tax control validity check card based on pci bus interface chip and CPLD chip of the present invention is used for the veritification security code business in tax control field, in use needs to be used with encrypted card.8 cryptographic algorithm chips that provide by self are veritified contrast to the security code of the invoice that encrypted card generates, thereby determine the correctness of security code, have only the correct security code of veritification just can print on the bill.The invoice of printing by this step is difficult to be distorted, thereby can satisfy the tax authority to the requirement of managing bill and authentication.
Tax control validity check card based on pci bus interface chip and CPLD chip of the present invention has the following advantages: the correctness that can effectively veritify the security code of invoice, possess simultaneously data reliable memory, prevent from the function of distorting from can satisfying the requirement of tax authority's managing bill; Thereby, have good value for applications.
Description of drawings
The present invention is further described below in conjunction with accompanying drawing.
Accompanying drawing 1 is the structured flowchart based on the tax control validity check card of pci bus interface chip and CPLD chip.
Embodiment
Explain below with reference to Figure of description and specific embodiment the tax control validity check card based on pci bus interface chip and CPLD chip of the present invention being done.
Embodiment:
Tax control validity check card based on pci bus interface chip and CPLD chip of the present invention, this tax control validity check card comprise master control CPLD chip, 8 control CPLD chips, 8 cryptographic algorithm chips, 8 dual port RAM chips, pci bus interface chip, PCI configuring chip, crystal oscillator, pci bus; Master control CPLD chip connects 8 control of control CPLD chip; 8 every of control CPLD chips all are connected with 1 dual port RAM chip, and the dual port RAM chip is connected with 1 cryptographic algorithm chip again; Master control CPLD chip connects the pci bus interface chip, and the pci bus interface chip connects the PCI configuring chip; Crystal oscillator provides the work dominant frequency of 8 cryptographic algorithm chips; The pci bus interface chip connects pci bus.
Master control CPLD chipAdopt the EPM7128SLC84 model chip of the U.S. MAX of altera corp 7000 series, the work of each chip module of master control CPLD chip tax control validity check card, the conversion of the address space of realizing this tax control validity check card by programming and the processing of 8 control CPLD chip interrupt and the chip selection signal that produces 8 dual port RAM chips.
The total number of pins 84 of EPM7128SLC84 model chip, wherein the IO number of pins 68, contain 2500 doors, 128 macroelements, 8 logic array blocks; This chip is the control core of tax control validity check card, realizes following function by programming in design:
(1) provide tax control validity check card IO the address 0～3 in space, wherein:
Unique card number of the corresponding tax control validity check card in 0～2 address, driver is read unique card number that this address obtains a 24BIT;
0 address also is multiplexed with the general reset mouth of tax control validity check card, and driver writes data to this address reset the tax control validity check card, writes to make the tax control validity check card be in reset mode for the first time, writes to make the tax control validity check card be in normal condition for the second time;
3 addresses are the interrupt inquiry address of tax control validity check card, and driver is by reading the sequence number that this address obtains sending out in the tax control validity check card control CPLD chip that interrupts;
(2) to the internal memory address decoding, produce the chip selection signal of 8 dual port RAM chips.
Sheet control CPLD chipAll adopt the EPM7064SLC44 model chip of the MAX of U.S. altera corp 7000 series; 8 control CPLD chips are all by being connected of each self-corresponding dual port RAM chip realization and each self-corresponding cryptographic algorithm chip, and finish control to the cryptographic algorithm chip by Programmable Technology.
The total number of pins 44 of EPM7064SLC44 model chip, wherein the IO number of pins 36, contain 1250 doors, 64 macroelements, 4 logic array blocks; Major function is the work of control cryptographic algorithm chip.
In this tax control validity check card course of work, control CPLD chip imports packet in the corresponding dual port RAM chip successively, and corresponding cryptographic algorithm chip takes out packet and carries out computing from the dual port RAM chip; Treat again packet to be write back in the dual port RAM chip after the computing of cryptographic algorithm chip is finished, control packet that the CPLD chip finishes computing again this moment and upload to host computer and produce and interrupt, so far finish the control flow of a packet.Behind all packets of handling host computer, can veritify the correctness of the security code of an invoice by cycle control.
Sheet cryptographic algorithm chipAll adopt tax control special purpose system algorithm chip SSX12-A model chip, the cryptographic algorithm chip carries out encryption and decryption, the veritification computing of data according to the tax control cryptographic algorithm.
SSX12-A model chip is specifically designed to information security fields such as tax control, and function mainly contains and generates key, data encryption, deciphering, veritification payment cipher etc., effectively guarantees the security of data when the user concludes the business.Its principal feature is: every SSX12-A model chip all has separately independently ID number, and all crypto-operations are all finished in sheet, supports 3.3V or 5V duplex to make voltage, when the work dominant frequency is 12MHz, veritifies payment cipher speed greater than 140 times/second.
Sheet dual port RAM chipAll adopt the IDT7130 model chip of IDT company, every dual port RAM chip all is inputoutput buffers of the corresponding cryptographic algorithm chip that connects separately, the cryptographic algorithm chip corresponding with every dual port RAM chip and control CPLD chip by separately independently port control the read-write of this dual port RAM chip respectively.
IDT7130 model chip is that the static SRAM(Static Random of the twoport Access Memory static random of the high speed 1K * 8bit of IDT company product is handled internal memory), have high speed access speed and low in power consumption.
Bus Interface ChipAdopt the PLX9052 model chip of PLX company, the pci bus interface chip is used for the interface logic of realization and pci bus.
PLX9052 model chip is one 32 pci bus target interface circuit chips, low in energy consumption, adopt PQFP type 160 pin package, accord with PCI 2.1 standards, its local bus can be set to 8/16/32 bus by programming, and rate of data signalling can reach 132MB/s.The packet that host computer sends is by being transferred to the control module of 8 corresponding on tax control validity check card cryptographic algorithm chips in the pci bus interface chip.
Configuring chipAdopt the 93LC46B model eeprom chip of Microchip company, the PCI configuring chip is used for the PCI allocation Bus Interface Chip.
Its capacity of 93LC46B model eeprom chip is 1Kbit, and PDIP-8 encapsulates, and is used for storing the configuration information of pci bus interface chip.The tax control validity check card power at every turn back pci bus interface chip at first in the PCI configuring chip load configuration information carry out initialization.
Crystal oscillatorAdopt the active crystal oscillator of 12MHz, the working clock frequency of cryptographic algorithm chip is provided.
The overall work process of the tax control validity check card based on pci bus interface chip and CPLD chip of the present invention is as follows:
1, the tax control validity check card links to each other with host computer by pci bus;
2, behind the tax control validity check card electrification reset, 8 control CPLD chips are in idle condition, the host computer driver is if any task, the status word of cryptographic algorithm chip 256 bytes of correspondence is written as 0x01, simultaneously data are write dual port RAM chip data buffer zone, write the back to the 254th byte write data of corresponding cryptographic algorithm chip 256 bytes, thereby sent interruption to control CPLD chip;
3, the query State word of having no progeny during control CPLD chip is received, if be 0x01 then send data to the cryptographic algorithm chip, read the clear interrupt bit of 254 bytes after being sent completely, wait for cryptographic algorithm chip return data then, the data that the cryptographic algorithm chip is returned write dual port RAM chip data buffer zone, simultaneously status word is written as 0x04, then to the 255th byte write data, thereby sends interruption to pci bus;
4, the host computer driver is had no progeny in receiving, and reads the interrupt inquiry address (IO3) of tax control validity check card earlier, if the data of reading are 0x00, then the tax control validity check card is not sent out interruption.If the data of reading are not 0x00, then the tax control validity check card has sent interruption, and 1 the cryptographic algorithm chip task of corresponding to is finished.Read the status word in 256 bytes of its correspondence again, and if for 0x04 task finished, thereby read data in the dual port RAM chip data buffer zone, read the 255th byte in 256 bytes of its correspondence simultaneously, remove this interruption;
5, in the work of tax control validity check card, can specify any 1 road or multichannel cryptographic algorithm chip operation of 8 cryptographic algorithm chips, efficient was higher when this had mass data to handle at host computer.As a certain cryptographic algorithm chip that must reset, only need write 0x02 at 256 byte status words of its correspondence, write the 254th byte in 256 bytes of its correspondence simultaneously.
Tax control validity check card based on pci bus interface chip and CPLD chip of the present invention except the described technical characterictic of instructions, is the known technology of those skilled in the art.
Claims (8)
1. based on the tax control validity check card of pci bus interface chip and CPLD chip, it is characterized in that this tax control validity check card comprises master control CPLD chip, 8 control CPLD chips, 8 cryptographic algorithm chips, 8 dual port RAM chips, pci bus interface chip, PCI configuring chip, crystal oscillator, pci bus; Master control CPLD chip connects 8 control of control CPLD chip; 8 every of control CPLD chips all are connected with 1 dual port RAM chip, and the dual port RAM chip is connected with 1 cryptographic algorithm chip again; Master control CPLD chip connects the pci bus interface chip, and the pci bus interface chip connects the PCI configuring chip; Crystal oscillator provides the work dominant frequency of 8 cryptographic algorithm chips; The pci bus interface chip connects pci bus.
2. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1, it is characterized in that master control CPLD chip adopts the EPM7128SLC84 model chip of the U.S. MAX of altera corp 7000 series, the work of each chip module of master control CPLD chip tax control validity check card, the conversion of the address space of realizing this tax control validity check card by programming and the processing of 8 control CPLD chip interrupt and the chip selection signal that produces 8 dual port RAM chips.
3. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1 is characterized in that 8 control CPLD chips all adopt the EPM7064SLC44 model chip of the MAX of U.S. altera corp 7000 series; 8 control CPLD chips are all by being connected of each self-corresponding dual port RAM chip realization and each self-corresponding cryptographic algorithm chip, and finish control to the cryptographic algorithm chip by Programmable Technology.
4. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1, it is characterized in that 8 cryptographic algorithm chips all adopt tax control special purpose system algorithm chip SSX12-A model chip, the cryptographic algorithm chip carries out encryption and decryption, the veritification computing of data according to the tax control cryptographic algorithm.
5. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1, it is characterized in that 8 dual port RAM chips all adopt the IDT7130 model chip of IDT company, every dual port RAM chip all is inputoutput buffers of the corresponding cryptographic algorithm chip that connects separately, the cryptographic algorithm chip corresponding with every dual port RAM chip and control CPLD chip by separately independently port control the read-write of this dual port RAM chip respectively.
6. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1, it is characterized in that the pci bus interface chip adopts the PLX9052 model chip of PLX company, the pci bus interface chip is used for the interface logic of realization and pci bus.
7. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1, it is characterized in that the PCI configuring chip adopts the 93LC46B model eeprom chip of Microchip company, the PCI configuring chip is used for the PCI allocation Bus Interface Chip.
8. the tax control validity check card based on pci bus interface chip and CPLD chip according to claim 1 is characterized in that crystal oscillator adopts the active crystal oscillator of 12MHz, provides the working clock frequency of cryptographic algorithm chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104134298A (en) * | 2014-08-14 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | Control method for PCI bus interface chip |
| CN109669872A (en) * | 2018-12-24 | 2019-04-23 | 郑州云海信息技术有限公司 | A kind of verification method and device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2864830Y (en) * | 2005-12-23 | 2007-01-31 | 航天信息股份有限公司 | False proof tax controlled chip |
| US20070239917A1 (en) * | 2005-12-09 | 2007-10-11 | Ryuji Orita | Interrupt routing within multiple-processor system |
| KR100778715B1 (en) * | 2006-09-29 | 2007-11-22 | 한국전자통신연구원 | Apparatus and method of controlling for multilateral image communication and visitor confirm in service mode connected home server and home automation |
| CN101452439A (en) * | 2008-12-29 | 2009-06-10 | 中国科学院长春光学精密机械与物理研究所 | CompactPCI communication card |
| CN101458852A (en) * | 2009-01-09 | 2009-06-17 | 北京工业大学 | Network tax control cash receiving terminal architecture |
| CN101826229A (en) * | 2010-04-14 | 2010-09-08 | 浪潮电子信息产业股份有限公司 | CPLD-based method for safely managing electronic counterfoil |
-
2013
- 2013-04-08 CN CN201310118808.5A patent/CN103236122B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070239917A1 (en) * | 2005-12-09 | 2007-10-11 | Ryuji Orita | Interrupt routing within multiple-processor system |
| CN2864830Y (en) * | 2005-12-23 | 2007-01-31 | 航天信息股份有限公司 | False proof tax controlled chip |
| KR100778715B1 (en) * | 2006-09-29 | 2007-11-22 | 한국전자통신연구원 | Apparatus and method of controlling for multilateral image communication and visitor confirm in service mode connected home server and home automation |
| CN101452439A (en) * | 2008-12-29 | 2009-06-10 | 中国科学院长春光学精密机械与物理研究所 | CompactPCI communication card |
| CN101458852A (en) * | 2009-01-09 | 2009-06-17 | 北京工业大学 | Network tax control cash receiving terminal architecture |
| CN101826229A (en) * | 2010-04-14 | 2010-09-08 | 浪潮电子信息产业股份有限公司 | CPLD-based method for safely managing electronic counterfoil |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104134298A (en) * | 2014-08-14 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | Control method for PCI bus interface chip |
| CN109669872A (en) * | 2018-12-24 | 2019-04-23 | 郑州云海信息技术有限公司 | A kind of verification method and device |
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| CN103236122B (en) | 2016-03-16 |
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Effective date of registration: 20230403 Address after: 250000 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province Patentee after: Shandong Inspur Scientific Research Institute Co.,Ltd. Address before: No. 1036, Shun Ya Road, Ji'nan high tech Zone, Shandong Province Patentee before: INSPUR GROUP Co.,Ltd. |