CN103235191A - Satellite add-drop separation signal detection device - Google Patents
Satellite add-drop separation signal detection device Download PDFInfo
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- CN103235191A CN103235191A CN2013101568794A CN201310156879A CN103235191A CN 103235191 A CN103235191 A CN 103235191A CN 2013101568794 A CN2013101568794 A CN 2013101568794A CN 201310156879 A CN201310156879 A CN 201310156879A CN 103235191 A CN103235191 A CN 103235191A
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Abstract
The invention discloses a satellite add-drop separation signal detection device, which relates to a detection device and is used for solving the problems of incapability of detecting the pulse width and amplitude of a satellite add-drop separation signal simultaneously and low measuring accuracy existing in the conventional detection device. Under the control of an FPGA (Field Programmable Gate Array) controller, an RS485 bus is used for receiving a command of a host, an AVR single chip microcomputer is used for resolving the command and performing corresponding operation according to a command resolving result, a signal processing circuit, a multi-path analog switch and an A/D (Analog to Digital) converter are used for measuring the amplitude of the satellite add-drop separation signal, the signal processing circuit and a comparator are used for finishing pulse width measurement of the satellite add-drop separation signal, and measured data are uploaded to the host through the RS485 bus. The satellite add-drop separation signal detection device is used for detecting the correctness of the satellite add-drop separation signal.
Description
Technical field
The present invention relates to a kind of pick-up unit, particularly a kind of satellite divides slotting separation signal pick-up unit.
Background technology
Satellite need carry out the surface power supply test to it before integration test and emission.Satellite ground power supply test is must obligato important step in the satellite R﹠D process.Satellite ground is powered test for checking satellite ground power supply, wired monitoring, wired measuring function and path, checks function of supplying power, control function, collection measurement function and the path correctness of a control platform, power battle array and surface power supply cable.
Pull-off plug is used for providing surface power supply to test required contact signal, level signal, pulse signal etc. as the circuit connector of satellite and surface power supply testing apparatus and the electromechanical compo that comes off.After satellite ground power supply detection was finished, needing provide branch slotting separation signal by ground checkout equipment to pull-off plug, and this branch is inserted separation signal makes the satellite pull-off plug realize coming off automatically.
Therefore, satellite divides slotting separation signal to finish the pulse control signal that comes off automatically as pull-off plug, the correctness of this pulse signal is that can the assurance pull-off plug finish the key that comes off automatically, and present pick-up unit can not detect pulsewidth and amplitude and the low problem of measuring accuracy that satellite divides slotting separation signal simultaneously.
Summary of the invention
The objective of the invention is to detect pulsewidth and amplitude and the low problem of measuring accuracy that satellite divides slotting separation signal simultaneously in order to solve present pick-up unit, the invention provides a kind of satellite and divide slotting separation signal pick-up unit.
Satellite of the present invention divides inserts the separation signal pick-up unit, and it comprises FPGA controller, AVR single-chip microcomputer, RS485 bus, five signal processing circuits, five comparers, multiway analog switch and A/D converters;
Host computer carries out exchanges data by RS485 bus and FPGA controller, and the command analysis signal input output end of FPGA controller is connected with the command analysis signal input output end of AVR single-chip microcomputer,
Five signal processing circuits receive five the tunnel respectively and divide slotting separation signal, the processing signals output terminal of described five signal processing circuits is connected with a signal input part of five comparers respectively, simultaneously, the processing signals output terminal of described five signal processing circuits also is connected with five signal input parts of multiway analog switch respectively, a signal output part of multiway analog switch is connected with the input end of analog signal of A/D converter, the digital signal output end of A/D converter is inserted the separation signal input end with the branch of FPGA controller and is connected, and the collection control signal input end of A/D converter is gathered the control signal output terminal with the AD of FPGA controller and is connected;
The pulse width measure signal output part of five comparers is connected with five pulse width measure signal input parts of FPGA controller respectively, and another signal input part of each comparer connects comparative voltage.
Described FPGA controller is embedded in synchronous RS-485 transceiver module, AVR interface microcontroller module, A/D control module and pulse width measure module;
The RS-485 transceiver module is used for the order that control RS485 bus receives the host computer transmission synchronously, and this order sent to AVR interface microcontroller module, also be used for the data that control RS485 bus measures pulse width measure module and A/D control module and send to host computer;
AVR interface microcontroller module, be used for the order that the RS485 bus receives from host computer is sent to the AVR single-chip microcomputer, and the data of returning after resolving according to the AVR single-chip microcomputer are carried out the self check of synchronous RS-485 transceiver module, or carry out described satellite and divide and insert the separation signal pick-up unit and reset, or control pulse width measure module and A/D control module are measured;
The A/D control module is used for the control A/D converter and carries out voltage acquisition, and reads the data of A/D converter output, also is used for the described data of storage;
The pulse width measure module is used for beginning counting when detect the slotting separation signal of branchs for rising edge, when detecting the slotting separation signal of branchs and be negative edge, stop to count, according to the pulsewidth of the slotting separation signal of described counting calculating branch.
The control procedure of FPGA controller adopts state machine to realize, described state machine comprises idle condition, starts time status, storing data state and transmission data mode;
Idle condition is inserted separation signal and is become high level when the pulse width measure module detects any one tunnel branch, then jumps to the startup time status;
Start time status, the pulse width measure module is inserted separation signal to the branch on this road and is carried out timing, and A/D control module control A/D converter carries out voltage acquisition and reads data this road being divided slotting separation signal; Divide and insert separation signal when becoming low level by high level when the pulse width measure module detects this road, jump to storing data state;
Storing data state, the pulse width measure module stops timing, and the A/D control module latchs the data that A/D converter is gathered, and finishes the measurement of pulse width and amplitude; When synchronous RS-485 transceiver module receives the order that host computer uploads, jump to the transmission data mode;
Send data mode, described pulse width and amplitude are sent to host computer by the RS485 bus; When data send end, jump to idle condition.
The invention has the advantages that, the present invention is under the control of FPGA controller, by receiving the order of host computer, use the AVR single-chip microcomputer to carry out command analysis, according to described command execution corresponding operating, signal processing circuit circuit, multiway analog switch and A/D converter instrumented satellite divide the amplitude of inserting separation signal, and signal processing circuit and comparer are finished satellite and divided the pulse width measuring of inserting separation signal, and measurement data is uploaded to host computer.The present invention can detect the slotting separation signal correctness of branch.And can finish simultaneously and divide the amplitude of slotting separation signal and the detection of pulsewidth to satellite, and the data that detection obtains are sent to host computer by the RS-485 bus, have the precision height of measurement, measuring accuracy has improved 5%, also has the advantage of good reliability and real-time simultaneously.
Description of drawings
Fig. 1 is that satellite of the present invention divides the principle schematic of inserting the separation signal pick-up unit.
Fig. 2 is the principle schematic of embodiment three described signal processing circuits.
Fig. 3 is the principle schematic of embodiment four described FPGA controllers.
Fig. 4 is the state transition graph that satellite of the present invention divides the FPGA controller of inserting the separation signal pick-up unit.
Embodiment
Embodiment one: present embodiment is described in conjunction with Fig. 1, the described satellite of present embodiment divides inserts the separation signal pick-up unit, and it comprises FPGA controller 1, AVR single-chip microcomputer 2, RS485 bus 3, five signal processing circuits 4, five comparers 5, multiway analog switch 6 and A/D converters 7;
Host computer carries out exchanges data by RS485 bus 3 and FPGA controller 1, and the command analysis signal input output end of FPGA controller 1 is connected with the command analysis signal input output end of AVR single-chip microcomputer 2,
Five signal processing circuits 4 receive five the tunnel respectively and divide slotting separation signal, the processing signals output terminal of described five signal processing circuits 4 is connected with a signal input part of five comparers 5 respectively, simultaneously, the processing signals output terminal of described five signal processing circuits 4 also is connected with five signal input parts of multiway analog switch 6 respectively, a signal output part of multiway analog switch 6 is connected with the input end of analog signal of A/D converter 7, the digital signal output end of A/D converter 7 is inserted the separation signal input end with the branch of FPGA controller 1 and is connected, and the collection control signal input end of A/D converter 7 is gathered the control signal output terminal with the AD of FPGA controller 1 and is connected;
The pulse width measure signal output part of five comparers 5 is connected with five pulse width measure signal input parts of FPGA controller 1 respectively, and another signal input part of each comparer 5 connects comparative voltage.
It is the control wave that comes off automatically for the satellite pull-off plug that satellite divides slotting separation signal, and come off in order to guarantee that the satellite pull-off plug is safe and reliable, general surface power supply testing apparatus all exportable two-way is divided slotting separation signal, wherein one the tunnel is used for space signal, guarantees the reliability that pull-off plug comes off with this.So satellite divides slotting separation signal pick-up unit should can detect two-way at least and divides slotting separation signal.The satellite of present embodiment divides slotting separation signal pick-up unit can detect 5 the tunnel and divides slotting discrete pulse signal, guarantees that this device has certain versatility.
The satellite of present embodiment divides slotting separation signal pick-up unit and host computer to be articulated in same RS-485 bus 3, described satellite divide insert the separation signal pick-up unit and receive the command request that host computer sends over after, measured data are uploaded to host computer by RS-485 bus 3.Wherein said satellite divides inserts separation signal pick-up unit employing FPGA as master controller, and FPGA controller 1 is mainly finished RS-485 bus 3 communication functions, pulse width measure counting and control A/D converter 7 and finished amplitude measurement.Described satellite divides slotting separation signal pick-up unit also to adopt an AVR single-chip microcomputer 2 to communicate by letter with FPGA controller 1, and this AVR single-chip microcomputer 2 is mainly finished RS-485 command analysis function.
The principle of pulse width measure is: be high level if divide to insert separation signal, through comparer 5 relatively back output high level give FPGA controller 1, FPGA controller 1 begins to count after receiving high level, counts to stop after high level becomes low level.If the number of FPGA controller counting is n, the clock period of FPGA is m, and then dividing the pulse width of inserting separation signal is n*m.
Embodiment two: present embodiment is to divide slotting separation signal pick-up unit further to limit to embodiment one described satellite, and it also comprises standby RS485 bus 8; Host computer also carries out exchanges data by standby RS485 bus 8 with FPGA controller 1.
Embodiment three: in conjunction with Fig. 2 present embodiment is described, present embodiment is to divide slotting separation signal pick-up unit further to limit to embodiment one described satellite, and described signal processing circuit 4 comprises modulate circuit 4-1 and filtering circuit 4-2; Modulate circuit 4-1 receives one the tunnel and divides slotting separation signal, and the conditioned signal output terminal of modulate circuit 4-1 is connected with the conditioned signal input end of filtering circuit 4-2, and the filtering signal output terminal of filtering circuit 4-2 is the processing signals output terminal of signal processing circuit 4.
The amplitude measurement circuit is mainly finished the voltage magnitude of input signal is measured, and it measures block diagram as shown in Figure 3.
Input signal needed through modulate circuit 4-1, filtering circuit 4-2 and multiway analog switch 6 before entering the AD collection.Wherein modulate circuit 4-1 is used for electric resistance partial pressure, and its decay ratio is 5: 1.Because divide slotting separation signal pulsewidth longer, filtering circuit 4-2 adopts low-pass filter circuit.Detect owing to will divide slotting separation signal to carry out amplitude to 5 the tunnel, so select the path of required measurement with multiway analog switch 6.Advantages such as multiway analog switch 6 is selected MAX308 for use, and this multiway analog switch 6 can switch 8 paths, and has the handoff delay weak point, and is low in energy consumption, and conducting resistance is little.AD selects chip AD7865 for use, and measurement range can reach-10V～+ 10V.Input signal inputs to FPGA controller 1 through after the AD converter 7 with the digital quantity after the conversion, finishes the amplitude measurement of pathway selected with this.
Embodiment four: present embodiment is described in conjunction with Fig. 3, present embodiment is to divide slotting separation signal pick-up unit further to limit to embodiment one described satellite, and described FPGA controller 1 is embedded in synchronous RS-485 transceiver module 1-1, AVR interface microcontroller module 1-2, A/D control module 1-3 and pulse width measure module 1-4;
Synchronous RS-485 transceiver module 1-1, be used for control RS4853 bus and receive the order that host computer sends, and this order sent to AVR interface microcontroller module 1-2, also be used for control RS4853 bus the data that pulse width measure module 1-4 and A/D control module 1-3 measure are sent to host computer;
AVR interface microcontroller module 1-2, be used for the order that RS485 bus 3 receives from host computer is sent to AVR single-chip microcomputer 2, and the data of returning after resolving according to AVR single-chip microcomputer 2 are carried out synchronous RS-485 transceiver module 1-1 self check, or carry out described satellite and divide and insert the separation signal pick-up unit and reset, or control pulse width measure module 1-4 and A/D control module 1-3 measure;
A/D control module 1-3 is used for control A/D converter 7 and carries out voltage acquisition, and reads the data of A/D converter 7 outputs, also is used for the described data of storage;
Pulse width measure module 1-4 is used for beginning counting when detect the slotting separation signal of branchs for rising edge, when detecting the slotting separation signal of branchs and be negative edge, stop to count, according to the pulsewidth of the slotting separation signal of described counting calculating branch.
Embodiment five: present embodiment is described in conjunction with Fig. 4, present embodiment is to divide slotting separation signal pick-up unit further to limit to embodiment four described satellites, the control procedure of FPGA controller 1 adopts state machine to realize, described state machine comprises idle condition, starts time status, storing data state and transmission data mode;
Idle condition is inserted separation signal and is become high level when pulse width measure module 1-4 detects any one tunnel branch, then jumps to the startup time status;
Start time status, pulse width measure module 1-4 inserts separation signal to the branch on this road and carries out timing, and 7 pairs of A/D control module 1-3 control A/D converters are inserted separation signal with this road branch and carried out voltage acquisition and read data; Divide and insert separation signal when becoming low level by high level when pulse width measure module 1-4 detects this road, jump to storing data state;
Storing data state, pulse width measure module 1-4 stops timing, and A/D control module 1-3 latchs the data that A/D converter 7 is gathered, and finishes the measurement of pulse width and amplitude; When synchronous RS485 transceiver module 1-1 receives the order that host computer uploads, jump to the transmission data mode;
Send data mode, described pulse width and amplitude are sent to host computer by the RS485 bus; When data send end, jump to idle condition.
Claims (5)
1. satellite divides slotting separation signal pick-up unit, it is characterized in that it comprises FPGA controller (1), AVR single-chip microcomputer (2) AVR single-chip microcomputer (2), RS485 bus (3), five signal processing circuits (4), five comparers (5), multiway analog switch (6) and A/D converter (7);
Host computer carries out exchanges data by RS485 bus (3) and FPGA controller (1), and the command analysis signal input output end of FPGA controller (1) is connected with the command analysis signal input output end of AVR single-chip microcomputer (2),
Five signal processing circuits (4) receive five the tunnel respectively and divide slotting separation signal, the processing signals output terminal of described five signal processing circuits (4) is connected with a signal input part of five comparers (5) respectively, simultaneously, the processing signals output terminal of described five signal processing circuits (4) also is connected with five signal input parts of multiway analog switch (6) respectively, a signal output part of multiway analog switch (6) is connected with the input end of analog signal of A/D converter (7), the digital signal output end of A/D converter (7) is inserted the separation signal input end with the branch of FPGA controller (1) and is connected, and the collection control signal input end of A/D converter (7) is gathered the control signal output terminal with the AD of FPGA controller (1) and is connected;
The pulse width measure signal output part of five comparers (5) is connected with five pulse width measure signal input parts of FPGA controller (1) respectively, and another signal input part of each comparer (5) connects comparative voltage.
2. satellite according to claim 1 divides slotting separation signal pick-up unit, it is characterized in that it also comprises standby RS485 bus (8); Host computer also carries out exchanges data by standby RS485 bus (8) and FPGA controller (1).
3. satellite according to claim 1 divides slotting separation signal pick-up unit, it is characterized in that described signal processing circuit (4) comprises modulate circuit (4-1) and filtering circuit (4-2); Modulate circuit (4-1) receives one the tunnel and divides slotting separation signal, the conditioned signal output terminal of modulate circuit (4-1) is connected with the conditioned signal input end of filtering circuit (4-2), and the filtering signal output terminal of filtering circuit (4-2) is the processing signals output terminal of signal processing circuit (4).
4. satellite according to claim 1 divides slotting separation signal pick-up unit, it is characterized in that described FPGA controller (1) is embedded in synchronous RS-485 transceiver module (1-1), AVR interface microcontroller module (1-2), A/D control module (1-3) and pulse width measure module (1-4);
Synchronous RS-485 transceiver module (1-1), be used for control RS485 bus (3) and receive the order that host computer sends, and this order sent to AVR interface microcontroller module (1-2), also be used for control RS485 bus (3) data of pulse width measure module (1-4) and A/D control module (1-3) measurement are sent to host computer;
AVR interface microcontroller module (1-2), be used for the order that RS485 bus (3) receives from host computer is sent to AVR single-chip microcomputer (2), and the data of returning after resolving according to AVR single-chip microcomputer (2) are carried out synchronous RS-485 transceiver module (1-1) self check, or carry out described satellite and divide and insert the separation signal pick-up unit and reset, or control pulse width measure module (1-4) and A/D control module (1-3) are measured;
A/D control module (1-3) is used for control A/D converter (7) and carries out voltage acquisition, and reads the data of A/D converter (7) output, also is used for the described data of storage;
Pulse width measure module (1-4) is used for beginning counting when detect the slotting separation signal of branchs for rising edge, when detecting the slotting separation signal of branchs and be negative edge, stop to count, according to the pulsewidth of the slotting separation signal of described counting calculating branch.
5. satellite according to claim 4 divides slotting separation signal pick-up unit, it is characterized in that, the control procedure of FPGA controller (1) adopts state machine to realize, described state machine comprises idle condition, starts time status, storing data state and transmission data mode;
Idle condition is inserted separation signal and is become high level when pulse width measure module (1-4) detects any one tunnel branch, then jumps to the startup time status;
Start time status, pulse width measure module (1-4) is inserted separation signal to the branch on this road and is carried out timing, and A/D control module (1-3) control A/D converter (7) carries out voltage acquisition and reads data this road being divided slotting separation signal; Divide and insert separation signal when becoming low level by high level when pulse width measure module (1-4) detects this road, jump to storing data state;
Storing data state, pulse width measure module (1-4) stops timing, and A/D control module (1-3) latchs the data that A/D converter (7) is gathered, and finishes the measurement of pulse width and amplitude; When synchronous RS-485 transceiver module (1-1) receives the order that host computer uploads, jump to the transmission data mode;
Send data mode, described pulse width and amplitude are sent to host computer by RS485 bus (3); When data send end, jump to idle condition.
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| CN112985193A (en) * | 2021-04-30 | 2021-06-18 | 星河动力(北京)空间科技有限公司 | Control method, device and system of carrier rocket and storage medium |
| CN113636111A (en) * | 2021-08-24 | 2021-11-12 | 上海卫星工程研究所 | Spacecraft electromechanical separation signal hybrid use system, method and medium |
| CN114325198A (en) * | 2021-12-29 | 2022-04-12 | 浙江时空道宇科技有限公司 | Test device and test system |
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Application publication date: 20130807 |