CN103227167B - Chip and test mode protection circuit and method of chip - Google Patents
Chip and test mode protection circuit and method of chip Download PDFInfo
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- CN103227167B CN103227167B CN201310118633.8A CN201310118633A CN103227167B CN 103227167 B CN103227167 B CN 103227167B CN 201310118633 A CN201310118633 A CN 201310118633A CN 103227167 B CN103227167 B CN 103227167B
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Abstract
The invention relates to a chip, a test mode protection circuit and a method of the chip. The protection circuit comprises a dynamic signal generator arranged in the chip and used for generating a random first dynamic signal and generating a second dynamic signal according to the first dynamic signal, effective metal wires arranged in a scribing groove of the chip and used for extending the first dynamic signal to the scribing groove from the chip and feeding a third dynamic signal driven by the first dynamic signal back to the chip from the scribing groove, a dynamic signal comparator arranged in the chip and used for receiving and comparing the second dynamic signal and the third dynamic signal and generating a test mode control signal, and a control circuit arranged in the chip and used for generating an internal test mode enabling signal according to the test mode control signal and an external test mode enabling signal. The difficulty of entering into a test mode of the chip can be improved greatly, and therefore, the safety of the chip is improved.
Description
Technical field
The present invention relates to microelectronic, particularly relate to a kind of chip and test pattern protective circuit thereof and method.
Background technology
In order to check that chip does not exist manufacturing defect in the fabrication process, nearly all chip has a test pattern.When chip has still been packaged into module on a wafer or, enters test pattern and close beta has been carried out to chip.In test mode, usually can perform the access to internal memory that some strictly forbids in chip in the future practical application, even can derive the data that chip internal memory or register are preserved.If the assailant obtaining chip successfully enters test pattern, just may obtain the private data in storage on chip or program code, copy living chip even further, such as intelligent card chip, therefore, must be irreversible from test pattern to the conversion of normal mode of operation.
In the prior art, use pin to carry out control chip and enter test pattern.As shown in Figure 1, for the test pattern implementation schematic diagram of prior art chips, this chip is comprising outside functional circuit and function press welding block, the fuse 121 also comprising test press welding block 111 and be connected with test press welding block 111, test press welding block 111 is external test mode enable ports, and external test mode enable signal is directly inputted to chip internal by this port.Such as, load logic 1 level on test press welding block 111, then external test mode enable signal is effective, chip enters test pattern, the level of load logic 0 on test press welding block 111, then external test mode enable signal is invalid, and chip does not enter test pattern.After chip testing terminates, the voltage that loading one is more taller than operating voltage on test press welding block 111, the fuse 121 be connected with test press welding block 111 can blow by the heat of generation.Like this, even if testing load logic 1 level on press welding block 111, chip also cannot be made to enter test pattern.
Along with the development of microelectric technique, fusing schemes is no longer valid.First, because fuse-wires structure area occupied is comparatively large, and fuse does not have other layer of metal cover, therefore under optics or electron microscope, be easy to the position finding fuse.Then, by using focused ion beam, (Focused Ion beam is called for short: technology FIB), is easy to rebuild the fuse-wires structure be blown.Once the fuse blown is rebuilt, just chip can be made to enter test pattern by controlling pin.
Again see Fig. 1, if use multiple fuse, suppose there be n fuse 121,122 ... 12n, in requisition for multiple test press welding block 111,112 ... 11n, n be more than or equal to 2 natural number.Before fuse is not blown, from n test press welding block input n position logical value, and compares with the n position expected value preset, when the two is identical, allow chip to enter test pattern.After test terminates, all fuses or portions of fusing filaments are blown, and the logic voltage be carried on n test press welding block cannot arrive chip internal, and internal control circuit will forbid that chip enters test pattern.Such a process increases group/cording quantity, the fail safe of test pattern can be improved to a certain extent, but very limited.
First, FIB rebuilds the workload just linear increase of fuse.Secondly, fuse area is comparatively large, and chip-area overhead strengthens, and the group/cording quantity brought improves limitation.Suppose there be n fuse, the expected value so preset only has n position, identical with fuse quantity, and the n position expected value preset has 2
nplanting may value.If n is large not, correct Configuration Values can be tried out by exhaustive method so within a certain period of time.
Summary of the invention
The invention provides a kind of chip and test pattern protective circuit thereof and method, in order to realize greatly improving the difficulty entering the test pattern of chip, thus promote the fail safe of chip.
The invention provides a kind of test pattern protective circuit of chip, comprising:
Dynamic Signal Generator, arrange in the chips, for generating the first random Dynamic Signal, according to described first Dynamic Signal, generate the second Dynamic Signal, wherein, the figure place of described first Dynamic Signal is n, the figure place of described second Dynamic Signal to be m, m and n be more than or equal to 2 natural number;
Effective metal line, be arranged in the scribe line of described chip, for described first Dynamic Signal is extended to scribe line from described chip, the 3rd Dynamic Signal driven by described first Dynamic Signal is fed back to described chip from described scribe line, wherein, the figure place of described 3rd Dynamic Signal is m;
Dynamic Signal comparator, arranging in the chips, for receiving described second Dynamic Signal and described 3rd Dynamic Signal, described second Dynamic Signal and described 3rd Dynamic Signal being compared, and generates test pattern control signal;
Control circuit, arrange in the chips, for according to described test pattern control signal and external test mode enable signal, generate internal test mode enable signal, make described chip determine whether to enter test pattern according to described internal test mode enable signal.
The present invention also provides a kind of test pattern guard method of chip, comprising:
In the chips, generate the first random Dynamic Signal, according to described first Dynamic Signal, generate the second Dynamic Signal, wherein, the figure place of described first Dynamic Signal is n, the figure place of described second Dynamic Signal to be m, m and n be more than or equal to 2 natural number;
By arranging effective metal wire in the scribe line of described chip, described first Dynamic Signal is extended to scribe line from described chip, the 3rd Dynamic Signal driven by described first Dynamic Signal is fed back to described chip from described scribe line, wherein, the figure place of described 3rd Dynamic Signal is m;
In the chips, described second Dynamic Signal and described 3rd Dynamic Signal are compared, generate test pattern control signal;
In the chips, according to described test pattern control signal and external test mode enable signal, generate internal test mode enable signal, make described chip determine whether to enter test pattern according to described internal test mode enable signal.
The present invention also provides a kind of chip, comprises functional circuit and function press welding block, also comprises the test pattern protective circuit of aforementioned chip.
Compared with prior art, the present invention has following advantage: the first, more in the quantity of the metal wire of chip edge, and the spacing simultaneously between metal wire can be very little, this considerably increases difficulty and complexity that FIB rebuilds metal wire; Second; the Dynamic Signal that the test pattern protective circuit real time contrast that the present embodiment provides produces; do not rely on certain encoded radio prestored; only have correct annexation of rebuilding between many metal line just may enter test pattern; the quantity of the possibility needing the metal wire attempted to connect is many, much larger than prior art.In sum, the present embodiment substantially increases the difficulty that assailant enters the test pattern of chip, thus greatly improves the fail safe of chip.
In addition; the metal wire be in scribe line in the test pattern protective circuit that the present embodiment provides is passive line completely; therefore Electro-static Driven Comb (Electro-static discharge is not needed; be called for short: ESD) protective circuit; press welding block is not needed to provide input yet; so the scribe line Area comparison shared by circuit is little, cause chip-area overhead smaller.
Accompanying drawing explanation
Fig. 1 is the test pattern implementation schematic diagram of prior art chips;
Fig. 2 is the structural representation of the test pattern protective circuit embodiment of chip of the present invention;
Fig. 3 is the quantity schematic diagram of the possibility that in the test pattern protective circuit embodiment of chip of the present invention, metal wire connects;
Fig. 4 is the schematic flow sheet of the test pattern guard method embodiment of chip of the present invention;
Fig. 5 is the structural representation of chip embodiment of the present invention.
Embodiment
Below in conjunction with specification drawings and specific embodiments, the invention will be further described.
As shown in Figure 2; for the structural representation of the test pattern protective circuit embodiment of chip of the present invention; this test pattern protective circuit can comprise Dynamic Signal Generator 21, effective metal line 22, Dynamic Signal comparator 23 and control circuit 24; Dynamic Signal Generator 21, Dynamic Signal comparator 23 and control circuit 24 arrange in the chips, and effective metal line 22 is arranged in the scribe line of chip.Effective metal line 22 is connected with Dynamic Signal Generator 21, and Dynamic Signal comparator 23 is connected with effective metal line 22 and Dynamic Signal Generator 21, and control circuit 24 is connected with Dynamic Signal comparator 23.
Wherein, Dynamic Signal Generator 21, for generating the first random Dynamic Signal, according to the first Dynamic Signal, generates the second Dynamic Signal, and wherein, the figure place of the first Dynamic Signal is n, the figure place of the second Dynamic Signal to be m, m and n be more than or equal to 2 natural number.Effective metal line 22 for extending to scribe line by the first Dynamic Signal from chip, and feed back to chip by the 3rd Dynamic Signal driven by the first Dynamic Signal from scribe line, wherein, the figure place of the 3rd Dynamic Signal is m; Particularly, effective metal line 22 comprises two parts metal wire: the metal wire the first Dynamic Signal being extended to from chip scribe line and the metal wire fed back to from scribe line by the 3rd Dynamic Signal chip; Alternatively, all or part of first Dynamic Signal can be extended to scribe line by effective metal line 22 from chip.Second Dynamic Signal and the 3rd Dynamic Signal, for receiving the second Dynamic Signal and the 3rd Dynamic Signal, compare by Dynamic Signal comparator 23, generate test pattern control signal; Particularly, when the second Dynamic Signal is identical with the 3rd Dynamic Signal, test pattern control signal is effective, and when the second Dynamic Signal is different from the 3rd Dynamic Signal, test pattern control signal is invalid.Control circuit 24, for according to test pattern control signal and external test mode enable signal, generates internal test mode enable signal, makes chip determine whether to enter test pattern according to internal test mode enable signal; Particularly, when test pattern control signal and external test mode enable signal are all effective, internal test mode enable signal is effective, and chip enters test pattern; When test pattern control signal and the arbitrary invalidating signal of external test mode enable signal, internal test mode enable signal is invalid, and chip cannot enter test pattern.
In the present embodiment, Dynamic Signal Generator 21 continuously produces the first Dynamic Signal that random width is n position, by chip internal and chip exterior two channels, the first Dynamic Signal is sent to Dynamic Signal comparator 23.Wherein, in first channel, k metal line is arranged into scribe line position, thus k position first Dynamic Signal is extended to scribe line from chip, then m metal line is returned chip from the position feedback of scribe line, the 3rd Dynamic Signal of the corresponding m position of this m metal line, 3rd Dynamic Signal sends to Dynamic Signal comparator 23, wherein, k be less than or equal to n and be more than or equal to 1 natural number.In second channel, the second Dynamic Signal generated directly is sent to Dynamic Signal comparator 23 from chip internal by Dynamic Signal Generator 21.Dynamic Signal comparator 23 will be that the second Dynamic Signal of m position and the 3rd Dynamic Signal contrast from the width that Dynamic Signal Generator 21 receives by different channel, if the 3rd Dynamic Signal fed back from chip exterior is identical with the second Dynamic Signal as desired value, then the internal test mode enable signal of Dynamic Signal comparator 23 output is effective, such as: internal test mode enable signal is logic high, otherwise, the internal test mode enable signal that Dynamic Signal comparator 23 exports is invalid, such as: internal test mode enable signal is low level.At chip not from before wafer point cuts off, the 3rd Dynamic Signal fed back from chip exterior is always identical with the second Dynamic Signal as desired value, so internal test mode enable signal continuously effective.By chip from the process that wafer point cuts off, metal wire in scribe line is destroyed, cause Dynamic Signal comparator 23 correctly cannot receive the 3rd Dynamic Signal, now, the 3rd Dynamic Signal fed back from chip exterior is no longer consistent with the second Dynamic Signal as desired value, and so internal test mode enable signal is invalid.
In sum, this test pattern protective circuit achieves the function for monitoring to metal wire in scribe line.At chip not from before wafer point cuts off; this test pattern protective circuit can monitor metal wire and be in connected state; and therefore judge that chip is not also split from wafer; now; internal test mode enable signal is effective; this test pattern protective circuit allows chip to enter test pattern, and when external test mode enable signal is also effective, namely chip enters test pattern.Chip is from after wafer point cuts off; the metal wire that test pattern protective circuit can monitor in scribe line is destroyed; and therefore judge that chip is split from wafer; now; internal test mode enable signal is invalid; external test mode enable signal also can be invalid; test pattern protective circuit forbids that chip enters test pattern; even if adopt FIB technology again to make external test mode enable signal effective; also internal test mode enable signal cannot be driven effective; therefore, chip cannot enter test pattern and tests.
Alternatively, then structural representation shown in Figure 2, the present embodiment can also comprise the enable metal wire 25 of external testing, is arranged in the scribe line of chip.The enable metal wire 25 of external testing for external test mode enable signal is extended to scribe line from chip, then feeds back to chip from scribe line.The external test mode enable signal of control circuit 24 for feeding back according to test pattern control signal and the enable metal wire 25 of external testing, generates internal test mode enable signal.External test mode enable signal is transferred to control circuit 24 by the enable metal wire 25 of external testing after can being loaded by test press welding block 111 again, and wherein, test press welding block 111 is positioned at chip internal.Alternatively, test press welding block 111 and can also be arranged in scribe line.Alternatively, test press welding block 111 can not wanted, directly enable for external testing metal wire 25 is connected to logic high, when chip is not from before wafer point cuts off, external test mode enable signal continuously effective, when test pattern control signal is also effective, chip directly enters test pattern; After chip point to cut off from wafer, the enable metal wire 25 of external testing is cut off, and external test mode enable signal is no longer valid.Alternatively, the figure place of external testing enable signal can be more than two, correspondingly, the quantity of the enable metal wire of external test mode is more than two, the quantity of test press welding block is also two or more, like this, each test press welding block applies 1 external test mode enable signal, and every wires transmits 1 external test mode enable signal.
Alternatively, external test mode enable signal can also adopt the fusing schemes in prior art shown in Fig. 1 to be applied on chip.
Alternatively, if 1 signal in the first Dynamic Signal can drive less than 1 signal in the 3rd Dynamic Signal, and the 3rd Dynamic Signal can be driven by all or part of signal of the first Dynamic Signal, then n is more than or equal to m.If 1 signal in the first Dynamic Signal can drive more than 1 signal in the 3rd Dynamic Signal, and the 3rd Dynamic Signal can be driven by whole signal of the first Dynamic Signal or part signal, then do not have size to limit between m and n, namely m can be greater than, be less than or equal to n.
Alternatively, Dynamic Signal Generator 21 can be arbitrarily signal generating device, such as, but be not limited to, LFSR), the signal generator of real random number generator, pseudorandom number generator or other types (Linear Feedback Shift Register is called for short: for counter, linear feedback shift register.Alternatively, Dynamic Signal Generator 21 can be the combination in any of counter, LFSR, real random number generator, pseudorandom number generator or other types signal generator; Such as, produce the n1 position in the Dynamic Signal of n position first by 1 counter, produce other n-n1 position signals by a LFSR.
Alternatively, then see Fig. 2, the present embodiment can also comprise warning circuit 26, arranges in the chips, for according to test pattern control signal and external test mode enable signal, generates alarm signal.Particularly, when test pattern control signal is invalid and external test mode enable signal is effective, alarm signal is effective, now thinks that chip receives the test pattern attack of assailant.
Alternatively, then see Fig. 2, effective metal line 22 can be arranged on same metal level or different metal levels.Particularly, the metal wire the first Dynamic Signal being extended to scribe line can be positioned at same metal level or different metal layer, and the 3rd Dynamic Signal can be positioned at same metal level or different metal layer from the metal wire that scribe line feeds back to chip.Again see Fig. 2, adopt different pattern to fill the metal wire represented and represent the metal wire being arranged on different metal levels.
Alternatively, again see Fig. 2, except effective metal line 22, the present embodiment can also comprise invalid metal wire 27, be arranged in the scribe line of chip, invalid metal wire does not apply the first Dynamic Signal or the 3rd Dynamic Signal, invalid metal wire 27 interference effects, thus increase attack difficulty further.
For the present embodiment, if want to make the chip cut off from wafer point reenter test pattern, assailant must rebuild the annexation between metal wire destroyed in these scribe line, the main difficulty done like this has: first, these metal wires are very thin, can be the minimum dimension meeting technological requirement, compare fuse much smaller, cause FIB to be difficult to do; The second, these metal wires can be in different metal layer, each other can be adjacent very near, cause FIB difficulty to strengthen; 3rd, the possibility of metal wire interconnection is many, makes the time cost of exhaustive trial method very high, and, for each possibility, when attempting, all to re-start the work that FIB rebuilds, further increase attack difficulty.
For the metal wire that n+m bar is cut-off, the annexation that redefine between n+m metal line is very difficult.Suppose that n and m is known, and m<=n, so will set up m to line relation in n+m metal line, then the individual signals supposing in n source signal only drives the individual signals in m signal, so, total possible number of combinations is:
And in the prior art, needing the logic level of attempting out that n+m fuse applies to be high or low, possible coded system number is 2
n+m.
As shown in table 1, for the quantity of the possibility that the possibility of metal wire connection in the present invention is connected with metal wire in prior art, can find, even if under above-mentioned hypothesis, in the present invention, the quantity of the possibility that metal wire connects is far longer than the quantity of the possibility that metal wire connects in prior art.And along with the increase of the numerical value of n and m, gap is therebetween also increasing.
Table 1
| N size | M size | Possibility of the present invention | The possibility of prior art |
| 6 | 4 | 4725 | 114 |
| 7 | 4 | 17325 | 2048 |
| 8 | 5 | 270270 | 8192 |
| 8 | 6 | 945945 | 16384 |
| 10 | 7 | 91891800 | 131072 |
| 12 | 8 | 9820936125 | 1048576 |
| 12 | 10 | 1.51242E+11 | 4194304 |
| 12 | 12 | 3.16234E 10 | 16777216 |
Further, if do not know n and m, only know the value K of n+m, namely can only see and suppose m<=n, and the individual signals in n source signal only drive the individual signals in m signal by the metal wire that a total how many velamen cuts off, so, total possible number of combinations is:
As shown in Figure 3; for the quantity schematic diagram of the possibility that metal wire in the test pattern protective circuit embodiment of chip of the present invention connects; the value of getting K is 8 to 20; under above-mentioned hypothesis, list the numerical value of the possible situation of possibility situation of the present invention and prior art respectively, can find; in the present invention, the quantity of the possibility that metal wire connects will far away more than the quantity of the possibility of metal wire connection in prior art; and along with the increase of K, gap is therebetween also increasing.
Further, if the individual signals in consideration n source signal can drive the situation of the multiple signals in m signal, the numerical value of total possible situation can increase further.Further, if consider the situation of m>n, the numerical value of total possible combined situation can increase further.
Compared with prior art, the test pattern protective circuit that the present embodiment provides has following advantage: first, more in the quantity of the metal wire of chip edge, spacing simultaneously between metal wire can be very little, and such as: 0.13um, processing line spacing can at 1um or less, this considerably increases difficulty and complexity that FIB rebuilds metal wire, further, metal wire can be distributed on multiple metal level, further increases difficulty and complexity that FIB rebuilds metal wire; Second; the Dynamic Signal that the test pattern protective circuit real time contrast that the present embodiment provides produces; do not rely on certain encoded radio prestored; only have correct annexation of rebuilding between many metal line just may enter test pattern; the quantity of the possibility needing the metal wire attempted to connect is many, much larger than prior art.In sum, the present embodiment substantially increases the difficulty that assailant enters the test pattern of chip, thus greatly improves the fail safe of chip.
In addition; the metal wire be in scribe line in the test pattern protective circuit that the present embodiment provides is passive line completely; therefore Electro-static Driven Comb (Electro-static discharge is not needed; be called for short: ESD) protective circuit; press welding block is not needed to provide input yet, simultaneously because metal wire can be distributed on each metal level, so; scribe line Area comparison shared by circuit is little, causes chip-area overhead smaller.
As shown in Figure 4, be the schematic flow sheet of the test pattern guard method embodiment of chip of the present invention, can comprise the steps:
Step 41, in the chips, Dynamic Signal Generator generates the first random Dynamic Signal, according to the first Dynamic Signal, generates the second Dynamic Signal;
Wherein, the figure place of the first Dynamic Signal is n, the figure place of the second Dynamic Signal to be m, m and n be more than or equal to 2 natural number;
Step 42, by arranging effective metal wire in the scribe line of chip, the first Dynamic Signal is extended to scribe line from chip, the 3rd Dynamic Signal driven by the first Dynamic Signal is fed back to chip from scribe line;
Wherein, the figure place of the 3rd Dynamic Signal is m; Effective metal line 22 comprises two parts metal wire: the metal wire the first Dynamic Signal being extended to from chip scribe line and the metal wire fed back to from scribe line by the 3rd Dynamic Signal chip;
Step 43, in the chips, the second Dynamic Signal and the 3rd Dynamic Signal compare by Dynamic Signal comparator, generate test pattern control signal;
Particularly, when the second Dynamic Signal is identical with the 3rd Dynamic Signal, test pattern control signal is effective, and when the second Dynamic Signal is different from the 3rd Dynamic Signal, test pattern control signal is invalid;
Step 44, in the chips, control circuit, according to test pattern control signal and external test mode enable signal, generates internal test mode enable signal, makes chip determine whether to enter test pattern according to internal test mode enable signal.
Particularly, when test pattern control signal and external test mode enable signal are all effective, internal test mode enable signal is effective, and chip enters test pattern; When test pattern control signal and the arbitrary invalidating signal of external test mode enable signal, internal test mode enable signal is invalid, and chip cannot enter test pattern.
In the present embodiment, Dynamic Signal Generator continuously produces the first Dynamic Signal that random width is n position, by chip internal and chip exterior two channels, the first Dynamic Signal is sent to Dynamic Signal comparator.Wherein, in first channel, k metal line is arranged into scribe line position, thus k position first Dynamic Signal is extended to scribe line from chip, again m metal line is returned chip from the position feedback of scribe line, the 3rd Dynamic Signal of the corresponding m position of m metal line, the 3rd Dynamic Signal sends to Dynamic Signal comparator, wherein, k be less than or equal to n and be more than or equal to 1 natural number.In second channel, the second Dynamic Signal generated directly is sent to Dynamic Signal comparator from chip internal by Dynamic Signal Generator.Dynamic Signal comparator will be that the second Dynamic Signal of m position and the 3rd Dynamic Signal contrast from the width that Dynamic Signal Generator receives by different channel, if the 3rd Dynamic Signal fed back from chip exterior is identical with the second Dynamic Signal as desired value, then the test pattern control signal of control circuit output is effective, otherwise the test pattern control signal that control circuit exports is invalid.At chip not from before wafer point cuts off, the 3rd Dynamic Signal fed back from chip exterior is always identical with the second Dynamic Signal as desired value, so test pattern control signal continuously effective.By chip from the process that wafer point cuts off, metal wire in scribe line is destroyed, cause Dynamic Signal comparator correctly cannot receive the 3rd Dynamic Signal, now, the 3rd Dynamic Signal fed back from chip exterior is no longer consistent with the second Dynamic Signal as desired value, and so test pattern control signal will be in invalid state.
Alternatively, then schematic flow sheet shown in Figure 4, the present embodiment can also comprise the steps:
Step 45, by arranging the enable metal wire of external testing in the scribe line of chip, external test mode enable signal is extended to scribe line from chip, then feeds back to chip from scribe line;
Now, in step 44, the external test mode enable signal that control circuit feeds back according to test pattern control signal and the enable metal wire of external testing, generates internal test mode enable signal.
It should be noted that between step 43 and step 45, there is no strict sequential relationship.
In step 45, external test mode enable signal can be loaded by test press welding block and be transferred to control circuit by metal wire again.Or, test press welding block can not wanted, directly metal wire corresponding for external test mode enable signal is connected to logic high, when chip is not from before wafer point cuts off, external test mode enable signal continuously effective, when test pattern control signal is also effective, chip directly enters test pattern; After chip point to cut off from wafer, the corresponding metal wire of external test mode enable signal is cut off, and external test mode enable signal is no longer valid.
Alternatively, the figure place of external testing enable signal can be more than two, correspondingly, the quantity of the enable metal wire of external test mode is more than two, the quantity of test press welding block is also two or more, like this, each test press welding block applies 1 external test mode enable signal, and every wires transmits 1 external test mode enable signal.
Alternatively, external test mode enable signal can also adopt the fusing schemes shown in Fig. 1 to be applied on chip.
Alternatively, in step 42, if 1 signal in the first Dynamic Signal can drive less than 1 signal in the 3rd Dynamic Signal, and the 3rd Dynamic Signal can be driven by all or part of signal of the first Dynamic Signal, then n is more than or equal to m.If 1 signal in the first Dynamic Signal can drive more than 1 signal in the 3rd Dynamic Signal, and the 3rd Dynamic Signal can be driven by whole signal of the first Dynamic Signal or part signal, then do not have size to limit between m and n, namely m can be greater than, be less than or equal to n.
Alternatively, can also comprise the steps: after step 43
Step 46, in the chips, warning circuit, according to test pattern control signal and external test mode enable signal, generates alarm signal;
Particularly, when test pattern control signal is invalid and external test mode enable signal is effective, alarm signal is effective, now thinks that chip receives the test pattern attack of assailant.
Strict sequential relationship is not had between step 46 and step 44.
Alternatively, in step 42, effective metal line can be arranged on same metal level or different metal levels.Particularly, the metal wire the first Dynamic Signal being extended to scribe line can be positioned at same metal level or different metal layer, and the 3rd Dynamic Signal can be positioned at same metal level or different metal layer from the metal wire that scribe line feeds back to chip.
Alternatively, the present embodiment can also comprise the steps: to add interference by arranging invalid metal wire in the scribe line of chip;
Particularly, invalid metal wire does not apply the first Dynamic Signal or the 3rd Dynamic Signal, invalid metal wire plays interference effect, thus increases attack difficulty further.
Compared with prior art, the test pattern guard method that the present embodiment provides has following advantage: first, more in the quantity of the metal wire of chip edge, spacing simultaneously between metal wire can be very little, this considerably increases difficulty and complexity that FIB rebuilds metal wire, further, metal wire can be distributed on multiple metal level, further increases difficulty and complexity that FIB rebuilds metal wire; Second; the Dynamic Signal that the test pattern guard method real time contrast that the present embodiment provides produces; do not rely on certain encoded radio prestored; only have correct annexation of rebuilding between many metal line just may enter test pattern; the quantity of the possibility needing the metal wire attempted to connect is many, much larger than prior art.In sum, the present embodiment substantially increases the difficulty that assailant enters the test pattern of chip, thus greatly improves the fail safe of chip.
In addition; the metal wire be in scribe line in the test pattern guard method that the present embodiment provides is passive line completely; therefore esd protection circuit is not needed; press welding block is not needed to provide input yet; simultaneously because metal wire can be distributed on each metal level; so the scribe line Area comparison shared by circuit is little, causes chip-area overhead smaller.
As shown in Figure 5, be the structural representation of chip embodiment of the present invention, this chip can comprise functional circuit 51, function press welding block 52 and test pattern protective circuit 53.Wherein, test pattern protective circuit 53 can be the test pattern protective circuit in the test pattern protective circuit embodiment of aforementioned chip, does not repeat them here.
Alternatively, the present embodiment can also comprise test press welding block 111, is connected, for loading external test mode enable signal with test pattern protective circuit 53.
In the present embodiment; the first Dynamic Signal that test pattern protective circuit 53 produces is drawn out in scribe line by metal wire and again the 3rd Dynamic Signal is fed back to test pattern protective circuit 52; by monitoring that the metal wire in scribe line is initial condition or destroyed state; test pattern protective circuit 52 can judge whether chip cuts down from wafer; chip is on wafer to only have test pattern protective circuit 52 to judge, just allows chip to enter test pattern and tests.Once test, chip is from after wafer has cut down, and test pattern protective circuit 52 can judge that chip is cut, so will no longer allow chip to enter test pattern.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (21)
1. a test pattern protective circuit for chip, is characterized in that, comprising:
Dynamic Signal Generator, arrange in the chips, for generating the first random Dynamic Signal, according to described first Dynamic Signal, generate the second Dynamic Signal, wherein, the figure place of described first Dynamic Signal is n, the figure place of described second Dynamic Signal to be m, m and n be more than or equal to 2 natural number;
Effective metal line, be arranged in the scribe line of described chip, for described first Dynamic Signal is extended to scribe line from described chip, the 3rd Dynamic Signal driven by described first Dynamic Signal is fed back to described chip from described scribe line, wherein, the figure place of described 3rd Dynamic Signal is m;
Dynamic Signal comparator, arranging in the chips, for receiving described second Dynamic Signal and described 3rd Dynamic Signal, described second Dynamic Signal and described 3rd Dynamic Signal being compared, and generates test pattern control signal;
Control circuit, arrange in the chips, for according to described test pattern control signal and external test mode enable signal, generate internal test mode enable signal, make described chip determine whether to enter test pattern according to described internal test mode enable signal.
2. the test pattern protective circuit of chip according to claim 1, is characterized in that, also comprise:
The enable metal wire of external testing, is arranged in the scribe line of described chip, for external test mode enable signal is extended to scribe line from described chip, then feeds back to described chip from scribe line;
Described control circuit is used for the external test mode enable signal fed back according to described test pattern control signal and the enable metal wire of described external test mode, generates described internal test mode enable signal.
3. the test pattern protective circuit of chip according to claim 1, is characterized in that, the part signal of described first Dynamic Signal is extended to described scribe line by described effective metal line from described chip.
4. according to the test pattern protective circuit of the arbitrary described chip of claim 1-3, it is characterized in that, 1 signal in described first Dynamic Signal drives less than 1 signal in described 3rd Dynamic Signal, and m is less than or equal to n.
5. according to the test pattern protective circuit of the arbitrary described chip of claim 1-3; it is characterized in that; 1 signal in described first Dynamic Signal drives more than 1 signal in described 3rd Dynamic Signal; and described 3rd Dynamic Signal is driven by all or part of signal in described first Dynamic Signal, and m is less than, be more than or equal to n.
6. the test pattern protective circuit of chip according to claim 2, is characterized in that, the figure place of described external test mode enable signal is more than two, and the quantity of the enable metal wire of described external testing is more than two.
7. the test pattern protective circuit of chip according to claim 1, is characterized in that, also comprise:
Alarm signal circuit for generating, is arranged in the chips, for according to described test pattern control signal and described external test mode enable signal, generates alarm signal.
8. the test pattern protective circuit of chip according to claim 1, is characterized in that, described effective metal line is arranged on different metal levels.
9. the test pattern protective circuit of chip according to claim 1, is characterized in that, also comprise:
Invalid metal wire, is arranged in the scribe line of described chip, described invalid metal wire does not apply described first Dynamic Signal or described 3rd Dynamic Signal.
10. the test pattern protective circuit of chip according to claim 1; it is characterized in that; described dynamic signal generation is counter, linear feedback shift register, real random number generator, pseudorandom number generator, or is the combination in any of counter, linear feedback shift register, real random number generator, pseudorandom number generator.
The test pattern guard method of 11. 1 kinds of chips, is characterized in that, comprising:
In the chips, generate the first random Dynamic Signal, according to described first Dynamic Signal, generate the second Dynamic Signal, wherein, the figure place of described first Dynamic Signal is n, the figure place of described second Dynamic Signal to be m, m and n be more than or equal to 2 natural number;
By arranging effective metal wire in the scribe line of described chip, described first Dynamic Signal is extended to scribe line from described chip, the 3rd Dynamic Signal driven by described first Dynamic Signal is fed back to described chip from described scribe line, wherein, the figure place of described 3rd Dynamic Signal is m;
In the chips, described second Dynamic Signal and described 3rd Dynamic Signal are compared, generate test pattern control signal;
In the chips, according to described test pattern control signal and external test mode enable signal, generate internal test mode enable signal, make described chip determine whether to enter test pattern according to described internal test mode enable signal.
The test pattern guard method of 12. chips according to claim 11, is characterized in that, also comprise:
By arranging the enable metal wire of external testing in the scribe line of described chip, external test mode enable signal is extended to scribe line from described chip, then feed back to described chip from scribe line;
Described according to described test pattern control signal and described external test mode enable signal, generate internal test mode enable signal and be specially:
According to the external test mode enable signal that described test pattern control signal and the enable metal wire of described external test mode feed back, generate internal test mode enable signal.
The test pattern guard method of 13. chips according to claim 11; it is characterized in that, describedly described first Dynamic Signal is extended to scribe line from described chip be specially: the part signal of described first Dynamic Signal is extended to scribe line from described chip.
14. according to the test pattern guard method of the arbitrary described chip of claim 11-13, and it is characterized in that, 1 signal in described first Dynamic Signal drives less than 1 signal in described 3rd Dynamic Signal, and m is less than or equal to n.
15. according to the test pattern guard method of the arbitrary described chip of claim 11-13; it is characterized in that; 1 signal in described first Dynamic Signal drives more than 1 signal in described 3rd Dynamic Signal; and described 3rd Dynamic Signal is driven by all or part of signal in described first Dynamic Signal, and m is less than, be more than or equal to n.
The test pattern guard method of 16. chips according to claim 12, is characterized in that, the figure place of described external test mode enable signal is more than two, and the quantity of the enable metal wire of described external testing is more than two.
The test pattern guard method of 17. chips according to claim 11, is characterized in that, also comprise:
In the chips, according to described test pattern control signal and described external test mode enable signal, generate alarm signal.
The test pattern guard method of 18. chips according to claim 11, is characterized in that, described effective metal line is arranged on different metal levels.
The test pattern guard method of 19. chips according to claim 11, is characterized in that, also comprise:
Adding interference by arranging invalid metal wire in the scribe line of described chip, described invalid metal wire not applying described first Dynamic Signal or described 3rd Dynamic Signal.
20. 1 kinds of chips, comprise functional circuit and function press welding block, it is characterized in that, also comprise the test pattern protective circuit of the arbitrary described chip of claim 1-10.
21. chips according to claim 20, is characterized in that, also comprise:
Test press welding block, is connected with described test pattern protective circuit, for loading external test mode enable signal.
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| CN103559459A (en) * | 2013-11-06 | 2014-02-05 | 北京昆腾微电子有限公司 | Dynamic shielding protection device and method for safety chip |
| CN107861047B (en) * | 2017-11-01 | 2020-04-03 | 北京智芯微电子科技有限公司 | Detection system and detection method for safety test mode |
| US20200350263A1 (en) * | 2019-04-30 | 2020-11-05 | Nxp B.V. | Semiconductor devices with security features |
| US20200350220A1 (en) * | 2019-04-30 | 2020-11-05 | Nxp B.V. | Semiconductor device with security features |
| CN110457172B (en) * | 2019-08-12 | 2023-09-29 | 兆讯恒达科技股份有限公司 | Detection method for film-flowing process |
| CN110648964A (en) * | 2019-10-30 | 2020-01-03 | 华虹半导体(无锡)有限公司 | Method for repairing fuse circuit of chip |
| CN112749419B (en) * | 2020-12-31 | 2023-11-21 | 广州万协通信息技术有限公司 | Protection device and method for safety chip test mode |
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