CN103220002B - A kind of quasi-cyclic LDPC code constructing method eliminating decoder access conflict - Google Patents

Abstract

The present invention relates to the building method of a kind of quasi-cyclic LDPC code, quasi-cyclic LDPC code to be constructed is represented by tree graph model Tanner figure, its quasi-cyclic check matrix parameter is, the size p × p of size m of basic matrix × n, Block matrix, basic matrix variable node dimension distribution (d_v)；Its step includes, 1) it is distributed (d according to described basic matrix variable node dimension_v) determine check-node homogenization dimension distribution (d_c), it is distributed (d according to described dimension_c) in Tanner figure, add all n variable nodes；2) adding m check-node in Tanner figure line by line and selecting to select variable node in advance, being determined the variable node reaching weight preset value by sideline weight, the variable node of described determination is an alternative set；In described alternative set, selection variables node degree of evading (ADeg) is equal to or more than time delay (DLY) point；3) according to step 2) obtained and a little determined sideline weight in Tanner figure, add corresponding edge in Tanner, obtain the quasi-cyclic LDPC of construction, code according to this Tanner figure, complete the construction of quasi-cyclic LDPC code.

Description

A kind of quasi-cyclic LDPC code constructing method eliminating decoder access conflict

Technical field

The present invention relates to the building method of linear error correction code, hierarchical decoder access conflict can be eliminated particularly to a kind of Use the building method of the quasi-cyclic LDPC code setting up check-node mode line by line.

Background technology

Initial LDPC (low-density check low-density parity-check, LDPC) decoding algorithm be by Gallager proposes, and its confidence spread mode is the scheduling that floods (flooding schedule).Mansour et al. proposes The confidence spread mode of a kind of Turbo decoding, the circulation way that the people such as Hocevar is this updates confidence level based on serial is called Hierarchical decoder algorithm (Layered Decoding).Hierarchical decoder algorithm not losing performance and can reduce computational complexity Meanwhile, make the iterations needed for decoding reduce half, therefore suffer from extensive concern.

Block row hierarchical decoder algorithm uses all row concurrent operations in block row, it is adaptable to quasi-cyclic LDPC code (Quasi- CyclicLDPC, QC-LDPC), use layering confidence spread mode, popular in recent years.Prior art is put for this Reliability circulation way proposes different ways of realization.When hardware realizes, the general minimum using correction and (Min-Sum) calculate Method is combined with hierarchical algorithm, to reduce complexity.Pipelining typically to be used improves the throughput of hierarchical decoder, but same When introduce access conflict problem.Bibliography (Sun Y, Karkooti M, Cavallaro J.High throughput, Parallel, scalable LDPC encoder/decoder architecture for OFDM systems.Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on, Oct.2006:39-42) add idle beat in a pipeline and solve access conflict problem, but reduce decoder and handle up Rate；Bibliography (Bhatt T, Sundaramurthy V, Stolpman V, et al.Pipelined Block-Serial Decoder Architecture for Structured LDPC Codes.Speech and Signal Processing, 2006 IEEE International Conference on, 2006:225-228) in add channel information mirror image RAM, by counting Calculate external information knots modification approximation and update channel information, improve pipeline operation efficiency, but performance is lost.Bibliography (Rovini M, Gentile G, Rossi F, et al.A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.IFIP International Conference on Very Large Scale Integration, 2007:236-241) in the scheduling order of operation of each piece of row and check node In reason device, channel information input and output order, make the order of operation of adjacent computing row mate, can only reduce idle waiting as far as possible； Bibliography (Jin Jie, Tsui Chi-ying.An Energy Efficient Layered Decoding Architecture for LDPC Decoder.IEEE Trans.on VLSI, 2010,18 (8): 1185-1195) middle utilization The feature of access conflict, utilizes coupling as much as possible to reduce reading RAM number of channel, reduces power consumption, but be also limited by school Test matrix structure；Bibliography (Marchand C, Dore J B, Conde-Canencia L, et al.Conflict Resolution for pipelined layeredLDPC decoders.Signal Processing Systems, 2009: In 220-225), QC-LDPC basic matrix is divided into the little basic matrix of S*S, then rearranges, by resource contention between streamline Looseization, but it is reduction of decoder degree of parallelism, make throughput reduce.

All solve access conflict problem above with reference to the method in document in varying degrees from design of encoder angle, but All being limited to LDPC check matrix structure, design process complexity does not but ensure that and collision problem is completely eliminated, and needs to pay simultaneously Go out resource or speed or performance cost.In the realization of row hierarchical decoder, the basic reason of access conflict is not account for this in code design One problem.

Content of the invention

For now methodical deficiency, the present invention proposes and a kind of is avoided that row hierarchical decoder algorithmic variable access conflict LDPC code building method, it is to avoid this difficult point in design of encoder, so that the realization simplification of hierarchical decoder, speed carry Height, avoids as reducing the hardware resource that access conflict need to be paid more simultaneously.The present invention is a kind of eliminates decoder access conflict The scheme of quasi-cyclic LDPC code constructing method is as follows, the building method of a kind of quasi-cyclic LDPC code, quasi-cyclic LDPC to be constructed Code is represented by tree graph model Tanner figure, and its quasi-cyclic check matrix parameter is, size m of basic matrix × n, Block matrix Size p × p, basic matrix variable node dimension distribution (d_v)；Its step includes,

1) it is distributed (d according to described basic matrix variable node dimension_v) determine check-node homogenization dimension distribution (d_c), root It is distributed (d according to described dimension_c) in Tanner figure, add all n variable nodes；

2) in Tanner figure, add m check-node line by line, and launch dendrogram with check-node, select to select change in advance Amount node, is determined the variable node reaching weight preset value by sideline weight, and the variable node of described determination is an alternative collection Close；Screening in described alternative set can make degree of evading between adjacent rows (ADeg) be equal to or more than decoding processing delay (DLY) variable node, forms destination node；

3) according to step 2) obtained destination node determines sideline weight in Tanner figure, adds corresponding in Tanner Limit, obtains the quasi-cyclic LDPC code of construction, completes the construction of quasi-cyclic LDPC code according to this Tanner figure.

The method that variable node is selected in selection in advance is, if the current dimension of described check-node is equal to 0, then from variable node In randomly choose a node as purpose variable node connect, directly in Tanner add corresponding edge, the weight in sideline is One fixed value or random value.

When launching dendrogram with check-node, described check-node dimension set is condition:

$k=0:d_c^i-1$

Wherein k is row dimension counter, represents and adds which bar limit, dⁱ _cBeing the dimension of i-th check-node, i is verification Node.

The step selecting variable node in advance is selected also to include, if continuing cycling through the current dimension of the described check-node of value not Equal to 0, then launching dendrogram with i-th check-node for root node, chosen distance root node is farthest and column weight distribution increases slow Variable node alternately node.

Judge that farthest nodal method is, be launched into the tree-shaped subgraph as l for the degree of depth with check-node for root node, until l The current subgraph variable node set number of layer reaches N, or the variable check-node collection of l+1 layer is combined into sky, with current verification The variable node that node does not connect is farthest node；If there is not the variable nodes not connected, then the now change in l layer Amount node is exactly farthest node.

Further, determine that the method that column weight distribution increases slow variable node is, calculate and described pre-select variable node Each row prostatitis weight and its expected row anharmonic ratio value Rcw, select wherein minimum of a value Rcw_min, therefrom select Rcw≤Rcw_min C, Wherein C empirical value is 1.5, variable node as selecting variable node in advance.

Further, sideline Weight Determination is, first traversal root node to all paths selecting variable node in advance, According to

$s={\mathrm{\Σ}}_{w=0}^{l-1}{(-1)}^w{p}_{i,j},$

Wherein, w represents the number of plies in current subgraph；p_{I, j}Represent the limit weight of path process, non-in i.e. corresponding basic matrix The side-play amount of neutral element；S is the weight in whole path, calculates accumulated path weight s and selects sideline power according to randomly assigne Weight p₀, i.e. meet formula: mod (s-p₀, all variable nodes of p) ≠ 0.

Further, decoder processing delay is relevant with concrete hierarchical decoder design, and its degree of evading (ADeg) scope 2～ 10, wherein accepted value is 5 or 8.

Further, the computational methods of the degree of evading between adjacent rows (ADeg) are, two row of the adjacent process when decoding In, the number of the nonzero element of next line common factor of residing row with the neutral element of lastrow.

Use the present invention to propose new code method for designing by the quasi-cyclic LDPC code that the present invention constructs and guarantee a yard structure energy Avoid U_jAccess conflict.CNP first can read in the U of non-recent renewal continuously from CxRAM_jValue U₄, U₂₅, U₂₈, long-time through 3T After, it is necessary to the updated U of input the 1st row operation₂, U₆, U₂₄, but they at least to get to after DLY-3T=2T again CNP entrance, the code construction process conflict evading of the present invention is constrained to ADeg=5, thus eliminates in advance to U₂The visit of equivalent Ask conflict, so this yard can support the row hierarchical decoder streamline of DLY≤5 without the efficiently decoding of idle waiting ground.Decrease Unnecessary delay.Decreasing the waste that often row DLY claps, and being not above row dimension, these postpone to be complicated U_jScheduling Design is also It is difficult to elimination.

It is the PEG algorithm promoted that block progressive edge increases (Block-PEG, BPEG) construction algorithm, can be used to construct this Bright QC-LDPC code.Algorithm (with C-PEG antithesis) on R-PEG line direction is combined with BPEG algorithm, simultaneously at construction algorithm Middle interpolation ADeg constraints, can construct row to evading block PEG algorithm (Row Direction Conflict AvoidanceBlock PEG, RCAB-PEG) flow process.

Structured approach described in this invention obtains quasi-cyclic LDPC code, is suitable for classical layering as depicted in figs. 1 and 2 and translates Code device.The data flow of this decoder is as follows:

1) channel information receiving from channel, is first cached in the middle of memory RAM；All external informations are initialized to 0；

2) from channel information memory, simultaneously serial is taken out in LDPC matrix in a certain layer (p row) corresponding to nonzero element Channel information, form the data stream that width is p；

3) channel information data stream is through selecting module, then determines according to the side-play amount in quasi-cyclic LDPC code basic matrix The circulation deviant of parallel data, is then sent through in corresponding p CNP arithmetic element；

4) from external information memory, simultaneously, read the external information corresponding to LDPC this layer of matrix, be input to CNP computing list In Yuan；

5) CNP arithmetic unit enters row operation according to the channel information receiving and external information, the structure of arithmetic unit such as Fig. 2 institute Showing, concrete operation is corresponding to row hierarchical decoder algorithm:

A) first channel information deducts external information and obtains the information from variable node to check-node, then enters this information Row extraction symbol and absolute value, carry out serial XOR and comparison operation with other information corresponding to this row respectively, obtain The symbol sum of products absolute value minimum of a value of all information of this row and sub-minimum；

B) according to the symbol product obtaining, minimum of a value, sub-minimum and through buffer scheduling information (u_ji) enter row operation, External information value after renewal；

C) external information after updating and the information from variable node to check-node obtaining before carry out summation operation, Channel information after renewal；

6) after completing the confidence spread of p row, continue successively to be iterated computing, until decoding number of times reaches maximum setting Value or decoding convergence.

The principle of the present invention

1 LDPC code row hierarchical decoder algorithm

Quasi-cyclic LDPC code check matrix (H_M×N) corresponding basic matrix is designated as Hb_m×n, the corresponding submatrix of the element of basic matrix It is designated as Block_p×p, wherein m, n represent the number of check-node and variable node in basic matrix respectively, meet M=m × p, N=n ×p。Represent the row dimension of jth row.

Algorithm flow after row hierarchical algorithm is combined with the minimum-sum algorithm of correction is as follows:

(1) Initial Channel Assignment information (U_j) and external information (v_ij):

$U_j^0=\log (p_j^0/p_j^1),1\≤j\≤N---\left(1\right)$

v_ij=0,1≤i≤M, 1≤j≤N (2)

In above formulaWithRepresent the posterior probability of j-th symbol, U_jIt is corresponding log-likelihood ratio,At the beginning of it Beginning value, v_ijIt is the external information that check-node i passes to variable node j.

(2) confidence spread computing is carried out line by line, renewal external information:

u_ji=U_j-v_ij (3)

$v_{\mathrm{ij}}^{\′}=\underset{k\∈N\left(i\right)\backslash j}{\mathrm{\Π}}\mathrm{sign}\left(u_{\mathrm{ki}}\right)\×\underset{k\∈N\left(i\right)\backslash j}{\min }\left|u_{\mathrm{ki}}\right|\×\mathrm{\α}---\left(4\right)$

In above formula, N (i) is the adjacent variable node set of check-node i, N (i) j be N (i) set get rid of node j gained Set；Symbolic operation is sought in sign () expression, and minimum computing is asked in set by min () expression；α is normalization factor, 0 ＜ α ＜ 1。

(3) update channel information and verify

U′_j=u_ji+v′_ij (5)

To all U_jMaking decisions and calculate verification formula, if meeting verification relation, then stopping iteration.Otherwise continue to change In generation, repeat step (2) (3) until meeting verification relation or iterations reaches preset value.

The data access conflict of 2 row hierarchical decoders

The QC-LDPC code of the cramped construction obtaining after being optimized design according to row hierarchical decoder algorithm and traditional design is translated Code device block diagram is as shown in Figure 1.

CxRAM in Fig. 1 represents channel information U_jMemory, ExRAM represents external information v_ijMemory, Rotation module Represent to p U_jCyclic shift according to needed for QC-LDPC code basic matrix side-play amount is carried out for the updated value.CNP is row layering computing Device, correspondence realizes formula (3～5), and it realizes structure as shown in Figure 2 in detail.CNP group represents p CNP of concurrent operation, corresponds to The block row of the p row composition of QC-LDPC code.Select module is used for the U reading from CxRAM_jValue and the firm channel information updating it Between select.After Select module selects, subsequent rows CNP computing U to be used immediately can be_jVariable provide be not required to through Cross the little delay passage of CxRAM.

In the typical CNP design shown in Fig. 2, u in this row can be arranged according to simulated annealing or genetic algorithm_jiValue Input and the order of output scheduling memory (SchRAM), it is achieved channel information U_jUpgrade in time.In Fig. 2, M module represents use u_jiSymbol, minimum do Min computing with time minimum equivalence.Module D represents delay, to U_qiEtc. seeking v_iq' logical delay of computing Mate.There is pipelining delay, when input is v in realizing due to Fig. 2_ij, U_j, the not corresponding formula (4 of the output of CNP simultaneously ～5) v shown in_ij', U_j', therefore it is labeled as v_iq', U_q’.In general, CNP realizes the calculating of formula (3～5), so Fig. 1 In interface macroscopically still label symbol v_ij', U_j', represent CNP to v_ij, U_jRenewal computing.

In fig. 2, all U required for certain row is processed_jAfter numerical value all inputs CNP, after this row operation is updated First U_jThe typical shortest time (being designated as DLY*T, T is the circuit clock cycle) that value reaches CNP entrance again is analyzed as follows. SchRAM input M module and the streamline of adder logic thereafter, the used time is 3T, after output will through Select module with The streamline of Rotation module composition, the used time is 2T, so U_jAt least need to postpone at the complete CNP entrance that again reaches of computing DLY*T=5T.In the design of some other low clock rate, DLY value can reach 2.High in clock rate, or p value is big parallel Spending in high design, DLY value is up to 10.DLY is the key factor in the design of row hierarchical decoder.

Table 1

The decoder streamline U2 value access conflict that the 1st, 2 row operations all update

Table 2

The decoder streamline U2 value that the 5th, 6 row operations all update

Access Lothrus apterus

Row hierarchical decoder algorithm streamline is that (being then that block-by-block row is parallel to QC-LDPC code) enters row operation, often line by line Run into the U that next line computing lastrow to be used just has updated_jThe situation of variable.When the operation result of lastrow can not carry in time Confession, will occur access conflict, and this can be illustrated by Fig. 1, Fig. 2 and Biao 1, it is assumed that DLY=5T.Basic matrix Hb the 2nd row pair of table 1 In formula (3～5) row operation answered, CNP first can read in the U of non-recent renewal continuously from CxRAM_jValue U₄, U₂₅, U₂₈, through 3T After Chang Shijian, it is necessary to the updated U of input the 1st row operation₂, U₆, U₂₄But, they at least will again after DLY-3T=2T CNP entrance can be reached, thus cause to U₂The access conflict of equivalent, so now streamline is forced to insert the 2T free time etc. Treat beat, cause unnecessary delay.The delay that the LDPC code of different structure causes is different, and when most, often row DLY to be caused claps Waste, even more than row dimension, these wastes are very considerable, complicated U_jScheduling Design also is difficult to eliminate these to postpone, thus Need to guarantee that a yard structure is avoided that U by new code method for designing_jAccess conflict.

The situation can being designed to LDPC code in table 2, basic matrix Hb the 6th row has more than or equal to DLY Uj value and the 5th Row is avoided, and i.e. has U1, U4, U6, U24, U28 totally 5 (=DLY) individual U_jValue and the 5th professional etiquette are kept away, it is possible to when to 6 row operation Allow CNP at 5 U of input_jValue U1, after U4, U6, U24, U28, then welcomes the just updated U2 value of the 5th row operation, thus flowing water Line does not needs idle waiting at the 5th row to the 6th row process transition period.In definition back row in nonzero element with previous row non-zero The element number that element is in different lines is " degree of evading " (Avoidence Degree, ADeg).In such as Fig. 1, the 2nd row is to the 1st Row degree of evading be 3, and in Fig. 2 the 5th, 6 in the ranks degree of evading be 5.As long as ADeg >=DLY can be avoided to U_jThe access punching of variable Prominent, in order to be sufficiently accurate it may be desired to ADeg=DLY, the neotectonics method that the present invention proposes will use this constraints.In terms of experience DLY value, ADeg Scope 2 to 10, representative value is 5 or 8.

The R-PEG algorithm that 3 employing line directions are filled

It is a kind of long based on local ring that traditional progressive edge increases (progressive edge-growth, PEG) class algorithm Maximized LDPC code building method, it is construction algorithm (Column Direction PEG, the C-setting up connection by column PEG), construction process can take into account the distribution of row dimension and local ring length maximizes, and institute's structure code performance is excellent.ADeg constraints is base Constraint between basic matrix row, but tradition PEG and popularization thereof are all to carry out check matrix construction according to column direction, are not easy to structure Make the LDPC code with restriction relation in the ranks, therefore use the mode adding limit in PEG algorithm line by line instead, can be convenient Construction meets the LDPC code requiring.Therefore the present invention proposes line direction PEG construction algorithm (Row Direction PEG, R-PEG). R-PEG can be illustrated according to C-PEG algorithm.C-PEG flow process is summarized as follows:

Condition: j=0:N-1 $k=0:d_v^j-1$

If: k=0

Then select the check-node with minimum number of dimensions to set up with current variable node j to be connected, and in TANNER figure Add corresponding limit.Otherwise, on the basis of current Tanner figure, j is cyclic variable, as the carrying out of circulation is added up.With variable Node j, is launched into, for root node, the subgraph that the degree of depth is l, until the current subgraph check-node set number of l layer reaches M, M is Number.

M is the number of check equations in LDPC check matrix, and the line number of check matrix.Or the verification joint of l+1 layer Point set is combined into sky.Then the check-node being not connected in subgraph is preferentially selected,.What was certain was that this parity check nodes with work as The figure that front variable root node j is launched does not connects, i.e. this parity check nodes and current variable node can not pass through any road Footpath connects.Otherwise select the check-node with the minimum number of degrees to set up with root node in the check-node set of l layer to be connected, and Add corresponding limit in Tanner figure, complete algorithm.

Fig. 3 is the contrast of the expanded view of C-PEG and R-PEG, and wherein open squares represents check-node.In conjunction with C-PEG stream Journey and Fig. 3 find that C-PEG, when realizing adding connection, is the interpolation one by one arranging according to variable node one, are row side It to PEG, when doing expansion process, is also to launch according to variable node (arranging).And the present invention by use R-PEG algorithm with Antithesis, add connect press check-node a line a line interpolation, be line direction PEG, figure expansion process during algorithm process Launch according to check-node (OK).The present invention needs row to process constraint, uses R-PEG method comparison convenient.

Brief description

Fig. 1 is typical hierarchical decoder architecture schematic diagram in the present invention.

Fig. 2 is that in Fig. 1 of the present invention, CNP realizes structural representation.

Fig. 3 is the PEG algorithm on line direction of the present invention and the comparison schematic diagram on tradition PEG algorithm column direction.

Quasi-cyclic LDPC code basic matrix schematic diagram when Fig. 4 is degree of evading ADeg=5 in one embodiment of the invention.

Fig. 5 is the bit error rate contrast simulation figure with standard code for the quasi-cyclic LDPC code of code check 0.5 in one embodiment of the invention.

Fig. 6 is quasi-cyclic LDPC code and the mark code bit error rate contrast simulation figure of code check 0.75 in one embodiment of the invention

Detailed description of the invention

According to above analyzing, for avoiding U_jAccess conflict, the ADeg constraints that the basic matrix of quasi-cyclic LDPC code need to meet As follows: in any a line of basic matrix (Hb), ADeg nonzero element at least to be had and all nonzero elements in lastrow are in Different lines, degree of evading ADeg representative value takes 5 or 8.This section proposes relative configurations algorithm.

It is the PEG algorithm promoted that block progressive edge increases (Block-PEG, BPEG) construction algorithm, can construct QC-LDPC code. R-PEG algorithm is combined with BPEG algorithm, in construction algorithm, adds ADeg constraints simultaneously, row can be constructed to evading block The flow process of PEG algorithm (Row Direction Conflict Avoidance Block PEG, RCAB-PEG).In order to simply, Algorithm flow statement does not differentiates between check-node and row, does not differentiates between variable node and row.

1. initialize LDPC check matrix parameter: size p × p, the variable of size m of basic matrix × n, Block matrix save Point dimension distribution (d_v), it is stipulated that the row order that row hierarchical decoder is processed；

2. it is distributed the homogenization dimension distribution (d determining check-node according to variable node dimension_c)；Add to Tanner figure All nn are columns the variable nodes of basic matrix.

3. in Tanner figure, add m check-node one by one, select variable node and set up connection, and determine that sideline is weighed Weight.Concrete steps: local ring a) maximizing PEG algorithm is long, b) carry out line direction PEG side by the row and column dimension distribution of planning Method (R-PEG) code constructs, and c) constructs QC-LDPC code, d) sets the condition of ADeg constraint.

Condition: i (i is check-node, and the line number of this row processing sequence by regulation for step check-node travels through)

(k is the counter of row dimension, represents which the bar limit added),It is i-th parity check nodes Dimension, this step set each check-node be connected with variable node)

If a) the current dimension of this check-node is equal to 0, then from variable node, randomly choose a node as mesh Node, K=K+1, continue cycling through；Otherwise launching bipartite graph with i-th check-node for root node, chosen distance root node is Remote node alternately gathers S₁It is launched into the subgraph as l for the degree of depth with check-node i for root node, until the current son of l layer Figure variable node set number reaches N, or the variable check-node collection of l+1 layer is combined into sky.Do not connect with current parity check nodes i The variable node connecing is farthest node；If there is no not having the variable nodes that connects, then now the variable node in l layer is just It is farthest node, be corresponding with C-PEG algorithm；

B) preferentially choose row and heavily increase slow row as candidate variables node.Calculate S₁Set corresponding each row prostatitis weight and its Expected row weight ratio Rcw, selects wherein minimum of a value Rcw_min.From set S₁Middle selection Rcw≤Rcw_min C_s2(C_s2Experience Value is 1.5) variable node form alternative set S₂；

C) traversal root node is to all paths of alternative variables node, according toCalculate path to tire out Long-pending weight S；And select sideline weight p according to randomly assigne₀, select S₂In all paths can ensure that LDPC code occurs without a length of 4 Ring, i.e. meets formula: mod (s-p₀, all variable nodes of p) ≠ 0, form alternative set S₃(this step can select p repeatedly₀, with Obtain non-NULL S₃).If S₃For empty set, then exit circulation, return to 3；Otherwise continue step d)；

D) annexation according to a upper parity check nodes, from set S₃The middle variable joint selecting to support ADeg constraints Point forms set S₄.I.e. at S₃During middle selection variable node, to preferentially select the element avoiding up nonzero element position.If Choosing, less than avoid, looks into the planning of current check-node dimension, sees that also remaining a how many variable node does not connect, if follow-up also have ADeg may be gathered enough and evade variable node, just allow S₄=S₃., otherwise S₄Empty set.If S₄For empty set, then exit circulation, return to 3；Otherwise continue；

E) from set S₄In randomly choose a node, set up with the root node determining in step a) and be connected, and phase is set Weight p answered₀。

Sum up RCAB-PEG structured approach, 3-a) step embody PEG algorithm local ring length maximization；3-b) step embodiment Line direction PEG method (R-PEG), and support to carry out code construction by the row and column dimension distribution of planning；3-c) embody QC- LDPC code constructs；3-d) embody the requirement of ADeg constraint.The relevant factors of performance such as this algorithm preferential support ring length, take into account ADeg Structural constraint, made code belongs to BPEG subset of codes, with the outstanding bit error rate performance of PEG code.

Description code construction is carried out as a example by useful Fig. 4 side-play amount matrix.This QC-LDPC code length 1344, code check 0.5, corresponding follows Ring displacement submatrix is 84x84.This code is systematic code, the left 8 row correspondence check bit of basic matrix, right 8 row corresponding informance positions.In order to compile Code realizes convenient, and this code uses double diagonal line structure, and this can add at algorithm the 2nd step initial phase, and can arrange to the 8th is inclined Shifting amount be 84 submatrix deduct one 1, obtain coding and start with a little.Set decoding block row order for 1,2,3,4,5,6,7, 8} circulates.Construction process conflict evading is constrained to ADeg=5, such as Fig. 4 the 2nd row nonzero element position { 2,10,11,13,16} Set, has 5 elements and the nonzero element of the 1st row does not arranges altogether, so this yard can support the row hierarchical decoder of DLY≤5 Streamline is without the efficiently decoding of idle waiting ground.

Table 3 provides the common code length of RCAB-PEG construction, the example of code check QC-LDPC code, and table includes that a yard parameter, cloth lead to Mean iterative number of time needed for rate, row hierarchical decoder algorithm.In table, completion rate represents under existing constraints, can success structure The number of codes made and the ratio constructing number of attempt,

The construction result of table 3 shows, RCAB-PEG algorithm is under identical code length code check, and submatrix is bigger, is more difficult to structure Making, ADeg value is more big more is difficult to construction.RCAB-PEG carries out ADeg constraint to constructed code, the Average Iteration of the LDPC code obtaining Number of times is basic and Block PEG algorithm code-phase is worked as.This point is also that RCAB-PEG supports ranks dimension distribution constraint and ring length The benefit that bigization is brought.

Construction end condition be 100 LDPC code of Successful construct or number of attempt reaches 5000；Mean iterative number of time Represent 100 LDPC code of Successful construct, (mean iterative number of time can be made to be taken at 10 using fixing typical signal to noise ratio condition Left and right a signal to noise ratio) needed for mean iterative number of time.Mean iterative number of time can tentatively judge the LDPC code generating quickly Performance, and select Candidate key for follow-up BER Simulation.

The construction result of table 3 shows, RCAB-PEG algorithm is under identical code length code check, and submatrix is bigger, is more difficult to structure Making, ADeg value is more big more is difficult to construction.RCAB-PEG carries out ADeg constraint to constructed code, the Average Iteration of the LDPC code obtaining Number of times is basic and Block PEG algorithm code-phase is worked as.This point is also that RCAB-PEG supports ranks dimension distribution constraint and ring length The benefit that bigization is brought.

Table 3

RCAB-PEG algorithm construction common code result table

Also finding out that from table 3 RCAB-PEG algorithm adds ADeg structuring constraint, algorithm completion rate is relative to BPEG algorithm Decreasing, this is relevant with dimension distribution, code length, code check, p value composite factor.But algorithm existence randomly chooses link, so can Can be hit pay dirk by repeatedly trying structure.Suitably relax constraint and also can improve completion rate, suboptimal solution of also can yet be regarded as.As increased algorithm 3- B) step C_s2Value, expands pre-selected works, weakens dimension and requires, does not deteriorate for a lot of long code performances.

Also can be by decoding circuit little for ADeg value constraint LY value.Even if Adeg value does not reaches the DLY value requiring in Fig. 1, institute The code of the big ADeg value as far as possible obtaining also can eliminate idle beat to greatest extent.In a word, can be according to the actual requirements to RCAB-PEG Algorithm makes reasonably adjustment.

The present invention proposes the bit error rate performance simulation scenarios of RCAB-PEG construction LDPC code, first with RCAB-PEG algorithm Construction obtains ADeg=5, and code length is respectively 8064 (p=252), 2016 (p=84), and 64800 (p=360), code check is respectively 6 LDPC code of 0.5 and 0.75.Then with row its bit error rate performance of hierarchical decoder algorithm simulating of 20 iteration, respectively with BPEG construct obtain 8064 code lengths, 2016 code lengths in WIMAX, the error performance of the LDPC code of 64800 code lengths enters in DVB-SII Row contrast, result can be found in Fig. 5 and Fig. 6.

From the contrast of Fig. 5 and Fig. 6 it can be seen that the LDPC code that obtains with BPEG algorithm of LDPC code that RCAB-PEG algorithm obtains And the LDPC code in WIMAX, DVB-SII standard has suitable performance.But the LDPC compared to the above two present invention construction Code is structurally optimized, it is to avoid row hierarchical decoder because of solve in the ranks to evade bring throughput decline or resource The increase taking.

Fig. 1, Fig. 2 is used to optimize structure realizing the QC-LDPC pipeline decoding device of DLY=5, comparable RCAB-PEG code Decoding rate with general code.Use the code of Fig. 4, ADeg=5, DLY-ADeg=0 idle beat need to be inserted during entering a new line, Row dimension dc=6, therefore often row processes required beat number is dc+DLY-ADeg=6T.And common Q C-with Fig. 4 formed objects LDPC code typical case ADeg=3, needs to insert the idle waiting that DLY-ADeg=2 claps, and the total umber of beats required for a line is processed is dc+ DLY-ADeg=8T.So 8T/6T=1.33 times that the speed of the corresponding decoder of Fig. 4 code is general code, and Fig. 4 code is in design During had contemplated that relation in the ranks, be not required to the Scheduling Design line by line of complexity, and the logical relation of Schedule RAM also may be used Simple realization, make decoder realize simpler effectively.

The present invention is directed to row hierarchical decoder and calculate the intermediate variable access conflict problem of device, it is proposed that a kind of elimination row layering is translated QC-LDPC code construction algorithm (RCAB-PEG) of code device access conflict, this algorithm uses line direction PEG algorithm, and supports in the ranks Evade constraint.This construction algorithm eliminates access conflict problem in advance, thus hierarchical decoder not need Scheduling Design etc. relevant multiple Miscellaneous design, eliminates relevant source rates cost.RCAB-PEG code can give full play to row point in the case of not increasing resource Layer decoder throughput potentiality, under situation typical, use RCAB-PEG code to make decoder speed can bring up to 1.33 times.And emulate Result shows, the LDPC code performance of generation and BPEG code, WIMAX, DVB-SII standard code performance have comparativity.The invention belongs to In the code construction algorithm research realizing for decoder, with reference to the technical method of the present invention, can explore and be suitable to different hardware realization The LDPC code building method of mode.

Claims (9)

1. a building method for quasi-cyclic LDPC code, quasi-cyclic LDPC code to be constructed passes through tree graph model Tanner chart Showing, its quasi-cyclic check matrix parameter is, the size p × p of size m of basic matrix × n, Block matrix, basic matrix variable node Dimension is distributed (d_v)；Its step includes,

1) it is distributed (d according to described basic matrix variable node dimension_v) determine check-node homogenization dimension distribution (d_c), according to institute State dimension distribution (d_c) in Tanner figure, add all n variable nodes；

2) in Tanner figure, add m check-node line by line, and launch dendrogram with check-node, select to select variable joint in advance Point, is determined the variable node reaching weight preset value by sideline weight, and the variable node of described determination is an alternative set；? Screening in described alternative set can make the degree of evading (ADeg) between adjacent rows be equal to or more than decoding processing delay (DLY) Variable node, forms destination node；

3) according to step 2) obtained destination node determines sideline weight in Tanner figure, adds corresponding edge in Tanner figure, Obtain posttectonic quasi-cyclic LDPC code according to this Tanner figure.

2. the building method of quasi-cyclic LDPC code as claimed in claim 1, it is characterised in that launch dendrogram with check-node When, check-node dimension set is condition:

$k=0:d_c^i-1$

Wherein k is row dimension counter, represents and adds which bar limit, dⁱ _cBeing the dimension of i-th check-node, i is check-node.

3. the building method of quasi-cyclic LDPC code as claimed in claim 1, it is characterised in that select to select variable node in advance Method is, if the current dimension of described check-node is equal to 0, then randomly chooses a node from variable node and becomes as purpose Amount node connects, and directly adds corresponding edge in Tanner, and the weight in sideline is a fixed value or random value.

4. the building method of quasi-cyclic LDPC code as claimed in claim 1, it is characterised in that select to select variable node in advance Step also includes, if the current dimension of described check-node is not equal to 0, then launches tree-shaped with i-th check-node for root node Figure, chosen distance root node is farthest and column weight distribution increases slow variable node alternately node.

5. the building method of quasi-cyclic LDPC code as claimed in claim 4, it is characterised in that judge that farthest nodal method is, It is launched into the tree-shaped subgraph as l for the degree of depth with check-node for root node, until the current subgraph variable node set number of l layer reaches To N, or the variable check-node collection of l+1 layer is combined into sky, is farthest with the variable node that current parity check nodes is not connected Node；If there is not the variable nodes not connected, then now the variable node in l layer is exactly farthest node.

6. the building method of quasi-cyclic LDPC code as claimed in claim 4, it is characterised in that determine that column weight distribution increases slow The method of variable node is, calculates described pre-variable node of selecting and respectively arranges prostatitis weight and its expected row anharmonic ratio value Rcw, selects wherein Minimum of a value Rcw_min, therefrom selects Rcw≤Rcw_min C, and wherein C empirical value is 1.5, variable node as selecting change in advance Amount node.

7. the building method of quasi-cyclic LDPC code as claimed in claim 1, it is characterised in that the degree of evading between adjacent rows (ADeg) computational methods are, in two row of the adjacent process when decoding, and the nonzero element of next line and the neutral element of lastrow The number of the common factor of residing row.

8. the building method of quasi-cyclic LDPC code as claimed in claim 1, it is characterised in that sideline Weight Determination is, First traversal root node to all paths selecting variable node in advance, according to

$s={\mathrm{\Σ}}_{w=0}^{l-1}{(-1)}^w{p}_{i,j},$

Wherein, l is the subgraph degree of depth being launched into for root node with check-node i, and w represents the number of plies in current subgraph；p_i,jRepresent The limit weight of path process, the side-play amount of nonzero element in i.e. corresponding basic matrix；S is the weight in whole path, calculates outlet Accumulation weight s in footpath simultaneously selects sideline weight p according to randomly assigne₀, i.e. meet formula: mod (s-p₀, all variablees joint of p) ≠ 0 Point.

9. the interpretation method of quasi-cyclic LDPC code of building method based on the quasi-cyclic LDPC code described in claim 1, The steps include:

1) it from channel receiving channel information, is first cached in the middle of memory RAM；Initializing all external informations is all 0；

2) while from channel information memory, in serial taking-up described LDPC construction code matrix, in any layer, nonzero element institute is right The channel information answered, forms the data stream that width is p；This layer has p row；

3) channel information data stream is through selecting module, then determines parallel according to the side-play amount in quasi-cyclic LDPC code basic matrix The circulation deviant of data, is then sent through in corresponding p CNP arithmetic element；

4) from external information memory, simultaneously, read the external information corresponding to quasi-cyclic LDPC code this layer of matrix, be input to CNP fortune Calculate in unit；

5) CNP arithmetic unit enters row operation according to the channel information receiving and external information；

6) after completing the confidence spread of p row, interative computation is proceeded, until decoding number of times reaches maximum set value or translates Code convergence.