CN103219950B - There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions - Google Patents
There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions Download PDFInfo
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- CN103219950B CN103219950B CN201310081299.3A CN201310081299A CN103219950B CN 103219950 B CN103219950 B CN 103219950B CN 201310081299 A CN201310081299 A CN 201310081299A CN 103219950 B CN103219950 B CN 103219950B
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Abstract
The invention discloses a kind of High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions, comprise three end, tunnel amplifying circuit, reference signal circuit, error signal extraction circuit, the first mixer and the second mixers; Three end, tunnel amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit; The present invention is by extracting through amplifying signal from any road three tunnel final stage amplifying circuits, and carry out subtracting each other obtaining error signal with undistorted main signal, error signal divided two-way to carry out regulating and be input in other two-way final stage amplifying circuit respectively, the output signal of the first mixer to wherein two-way final stage amplifying circuit is carried out first time and is offset; The output signal of the second mixer to the output signal of the first mixer and an other road final stage amplifying circuit carries out second time counteracting.The distorted signal that power amplifier produces after twice counteracting is all eliminated, and obtains good linear effects.
Description
Technical field
The present invention relates to power amplification circuit, particularly relate to a kind of High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions.
Background technology
Contemporary Digital pre-distortion technology is widely used at wireless communication base station system, feed forward power amplifier is still used in some application scenario, but the shortcoming of traditional Feed Forward Power Amplifier based on main amplifier and error amplifier is, because error amplifier itself does not have contribution to the power output of power amplifier, and error amplifier itself has power consumption, therefore cause the efficiency comparison of conventional feed forward power amplifier low, even if having employed Doherty technical efficiency also can only reach about 22%.Therefore, it is possible to work out a kind of high efficiency, simultaneously but also can be when the previous problem being worth further investigation further to realize linearisation without the need to extra circuit of not only having had.
Summary of the invention
The object of the present invention is to provide a kind of high efficiency power amplifier with three conjunction road, tunnel cancellation functions, this amplifier can realize amplifying the high efficiency of the radiofrequency signal of mobile communication frequency range and High Linear.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions is provided, comprises three end, tunnel amplifying circuit, reference signal circuit, error signal extraction circuit, the first mixer and the second mixers; Described three end, tunnel amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Described reference signal circuit carries out amplitude to undistorted main signal and phase adjusted obtains reference signal;
Through amplifying signal in any road final stage amplifying circuit of described error signal extraction circuit extraction, this contains distorted signal and main signal through amplifying signal, this subtracts each other through amplifying signal and described reference signal by described first error signal extraction circuit again, and respectively amplitude and phase adjusted are carried out to the error signal obtained after subtracting each other, obtain the first regulating error signal and the second regulating error signal, and be input in other two-way final stage amplifying circuit respectively;
The output signal of described first mixer to wherein two-way final stage amplifying circuit is carried out first time error signal and is offset;
The output signal of described second mixer to the output signal of described first mixer and an other road final stage amplifying circuit carries out the counteracting of second time error signal.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, wherein:
Described first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the first final amplifier, the first coupler and the first delayer that connect successively; The input access main signal of described first power splitter; The output of described first delayer connects an input of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect the output of described reference signal regulating circuit and a coupled end of the first coupler respectively;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described 3rd power splitter connects the output of subtracter, the input of described first error signal regulating circuit connects an output of described 3rd power splitter, and the output of described first error signal regulating circuit exports the second regulating error signal; The input of described second error signal regulating circuit connects another output of described 3rd power splitter, and the output of described second error signal regulating circuit exports the first regulating error signal;
Described second final stage amplifying circuit comprises the 4th power splitter and the first final stage time delay and amplifying circuit, the input of described 4th power splitter connects an output of described second power splitter, described first final stage time delay is connected an output of described 4th power splitter with an input of amplifying circuit, another input of described first final stage time delay and amplifying circuit accesses described first regulating error signal, and described first final stage time delay is connected another input of described first mixer with the output of amplifying circuit;
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit, described second final stage time delay is connected another output of described 4th power splitter with an input of amplifying circuit, and another input of described second final stage time delay and amplifying circuit accesses the second regulating error signal; Described second final stage time delay is connected an input of the second mixer with the output of amplifying circuit; Another input of described second mixer connects the output of described first mixer.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, wherein:
Described first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the 4th power splitter, the first final amplifier, the first coupler and the first delayer that connect successively; The input access main signal of described first power splitter; The output of described first delayer connects an input of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect the output of described reference signal regulating circuit and a coupled end of the first coupler respectively;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described 3rd power splitter connects the output of subtracter, the input of described first error signal regulating circuit connects an output of described 3rd power splitter, and the output of described first error signal regulating circuit exports the second regulating error signal; The input of described second error signal regulating circuit connects another output of described 3rd power splitter, and the output of described second error signal regulating circuit exports the first regulating error signal;
Described second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit, described first final stage time delay is connected an output of described second power splitter with an input of amplifying circuit, another input of described first final stage time delay and amplifying circuit accesses described first regulating error signal, and described first final stage time delay is connected another input of described first mixer with the output of amplifying circuit;
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit, described second final stage time delay is connected an output of described 4th power splitter with an input of amplifying circuit, and another input of described second final stage time delay and amplifying circuit accesses the second regulating error signal; Described second final stage time delay is connected an input of the second mixer with the output of amplifying circuit; Another input of described second mixer connects the output of described first mixer.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, wherein:
Described first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the 4th power splitter, the first final amplifier, the first coupler and the first delayer that connect successively; The input access main signal of described first power splitter; The output of described first delayer connects an input of described second mixer; Another input of described second mixer connects the output of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect the output of described reference signal regulating circuit and a coupled end of the first coupler respectively;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described 3rd power splitter connects the output of subtracter, the input of described first error signal regulating circuit connects an output of described 3rd power splitter, and the output of described first error signal regulating circuit exports the second regulating error signal; The input of described second error signal regulating circuit connects another output of described 3rd power splitter, and the output of described second error signal regulating circuit exports the first regulating error signal;
Described second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit, described first final stage time delay is connected an output of described 4th power splitter with an input of amplifying circuit, and another input of described first final stage time delay and amplifying circuit accesses the second regulating error signal; Described first final stage time delay is connected an input of the first mixer with the output of amplifying circuit;
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit, described second final stage time delay is connected an output of described second power splitter with an input of amplifying circuit, another input of described second final stage time delay and amplifying circuit accesses described first regulating error signal, and described second final stage time delay is connected another input of described first mixer with the output of amplifying circuit.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and the input signal time delay of described subtracter two inputs is equal, and error signal phase place in input signal is contrary, and amplitude is equal.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and described first final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit, and phase place is identical.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and described second final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit, and phase place is identical.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and the input signal time delay of two inputs of described first mixer is equal, and error signal phase place in input signal is contrary, and amplitude is not etc.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and the input signal time delay of two inputs of described second mixer is equal, and error signal phase place in input signal is contrary, and amplitude is equal.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and described first final stage time delay comprises with amplifying circuit the second delayer, the second coupler and the second final amplifier that are connected successively with amplifying circuit or described second final stage time delay.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and described first final stage time delay comprises with amplifying circuit the 3rd delayer, the 3rd final amplifier and the 3rd coupler that are connected successively with amplifying circuit or described second final stage time delay.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and described driving amplifier comprises N number of amplifier tube, and wherein N is natural number.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and the 3rd delayer is any one in delay line, integrated delayer or filtering wave by prolonging time device.
Of the present invention have in the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, and the first final amplifier, the second final amplifier or the 3rd final amplifier comprise the amplifier tube of N number of series connection or parallel connection, and wherein N is natural number.
The beneficial effect that the present invention produces is: the present invention is by extracting through amplifying signal from any road three tunnel final stage amplifying circuits, and carry out subtracting each other obtaining error signal with undistorted main signal, error signal divided two-way to carry out regulating and be input in other two-way final stage amplifying circuit respectively, the output signal of the first mixer to wherein two-way final stage amplifying circuit is carried out first time and is offset; The output signal of the second mixer to the output signal of described first mixer and an other road final stage amplifying circuit carries out second time counteracting.Due to the counteracting of twice error signal can be carried out, can be more relatively low to the required precision of circuit.The distorted signal that power amplifier produces after twice counteracting is all eliminated, and obtains good linear effects.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the schematic block circuit diagram of first embodiment of the invention;
Fig. 2 is the schematic block circuit diagram of second embodiment of the invention;
Fig. 3 is the schematic block circuit diagram of third embodiment of the invention;
Fig. 4 is the schematic block circuit diagram one of the of the present invention first or second final stage time delay and amplifying circuit;
Fig. 5 is the schematic block circuit diagram two of the of the present invention first or second final stage time delay and amplifying circuit;
Fig. 6 is the theory diagram of reference signal regulating circuit of the present invention;
Fig. 7 is the first error signal regulating circuit of the present invention or the second error signal regulating circuit theory diagram;
Fig. 8 is the structural representation one of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier;
Fig. 9 is the structural representation two of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier;
Figure 10 is the structural representation three of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In order to realize amplifying the high efficiency of the radiofrequency signal of mobile communication frequency range and High Linear, the embodiment of the present invention has the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions, comprises three end, tunnel amplifying circuit, reference signal circuit, error signal extraction circuit, the first mixer and the second mixers; Three end, tunnel amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Reference signal circuit carries out amplitude to undistorted main signal and phase adjusted obtains reference signal;
Through amplifying signal in any road final stage amplifying circuit of error signal extraction circuit extraction, this contains distorted signal and main signal through amplifying signal, this subtracts each other through amplifying signal and reference signal by the first error signal extraction circuit again, and respectively amplitude and phase adjusted are carried out to the error signal obtained after subtracting each other, obtain the first regulating error signal and the second regulating error signal, and be input in other two-way final stage amplifying circuit respectively;
The output signal of the first mixer to wherein two-way final stage amplifying circuit is carried out first time error signal and is offset;
The output signal of the second mixer to the output signal of the first mixer and an other road final stage amplifying circuit carries out the counteracting of second time error signal.
As shown in Figure 1, the first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, second power splitter 4, first final amplifier 5, first coupler 6 and the first delayer 7 that connect successively to the first embodiment of the present invention; The input access main signal of the first power splitter 1; The output of the first delayer 7 connects an input of the first mixer 15.Be specially: main signal inputs from the first power splitter 1 input A1, the input A3 of driving amplifier 2 is outputted to from the first output terminals A 2 of the first power splitter 1, the signal of driving amplifier 2 to input amplifies, the input A5 of the second power splitter 4 is then outputted to from the output terminals A 4 of driving amplifier 2, the input B2 of the first final amplifier 5 is outputted to from the second output B1 of the second power splitter 4, first final amplifier 5 pairs signal amplifies, distorted signal can be produced simultaneously, the signal be exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then the second input D2 of subtracter 8 is outputted to from the coupled end D1 of the first coupler 6.The output B5 of the first coupler 6 outputs signal the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects the second output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects the coupled end D1 of the first coupler 6;
Error signal extraction circuit comprises the 3rd power splitter 9, first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, and the output E5 of the first error signal regulating circuit 10 exports the second regulating error signal; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, and the output F3 of the second error signal regulating circuit 11 exports the first regulating error signal;
Second final stage amplifying circuit comprises the 4th power splitter 12 and the first final stage time delay and amplifying circuit 13, the input A7 of the 4th power splitter 12 connects an output terminals A 6 of the second power splitter 4, first final stage time delay is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, another input of first final stage time delay and amplifying circuit 13 accesses the first regulating error signal, namely connects the output F3 of the second error signal regulating circuit 11.First final stage time delay is connected another input G4 of the first mixer 15 with the output G3 of amplifying circuit 13; First final stage time delay and amplifying circuit 13 pairs of signals carry out the injection of time delay, amplification and error signal, can produce distorted signal simultaneously.
3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit 14, second final stage time delay is connected another output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, another input of second final stage time delay and amplifying circuit 14 accesses the second regulating error signal, namely connects the output E5 of the first error signal regulating circuit 10; Second final stage time delay is connected an input H4 of the second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of the second mixer 16 connects the output G5 of the first mixer 15.Second final stage time delay and amplifying circuit 14 pairs of signals carry out the injection of time delay, amplification and error signal, can produce distorted signal simultaneously.
The second embodiment of the present invention, as shown in Figure 2, the first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and the first delayer 7 that connect successively, the input access main signal of the first power splitter 1, the output of the first delayer 7 connects an input of the first mixer 15, be specially: main signal inputs from the first power splitter 1 input A1, the input A3 of driving amplifier 2 is outputted to from the first output terminals A 2 of the first power splitter 1, the signal of driving amplifier 2 to input amplifies, the input A5 of the second power splitter 4 is then outputted to from the output terminals A 4 of driving amplifier 2, the input A7 of the 4th power splitter 12 is outputted to from the second output G1 of the second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of the first final amplifier 5, first final amplifier 5 pairs signal amplifies, distorted signal can be produced simultaneously, the signal be exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then the second input D2 of subtracter 8 is outputted to from the coupled end D1 of the first coupler 6.The output B5 of the first coupler 6 outputs signal the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of the first coupler 6;
Error signal extraction circuit comprises the 3rd power splitter 9, first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 of the first error signal regulating circuit 10 exports the second regulating error signal, and output E5 is connected with the input E6 of amplifying circuit 14 with the second final stage time delay; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 of the second error signal regulating circuit 11 exports the first regulating error signal, and output F3 is connected with the input F4 of amplifying circuit 13 with the first final stage time delay;
Second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit 13, first final stage time delay is connected an output G1 of the second power splitter 4 with an input G2 of amplifying circuit 13, another input F4 of the first final stage time delay and amplifying circuit 13 accesses the first regulating error signal, and the first final stage time delay is connected another input G4 of the first mixer 15 with the output G3 of amplifying circuit 13;
3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit 14, second final stage time delay is connected an output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, and another input E6 of the second final stage time delay and amplifying circuit 14 accesses the second regulating error signal; Second final stage time delay is connected an input H4 of the second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of the second mixer 16 connects the output G5 of the first mixer 15.
As shown in Figure 3, the first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and the first delayer 7 that connect successively to third embodiment of the invention, the input access main signal of the first power splitter 1, the output of the first delayer 7 connects an input of the second mixer 16, another input of second mixer 16 connects the output of the first mixer 15, first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and the first delayer 7 that connect successively, the input access main signal of the first power splitter 1, be specially: main signal inputs from the first power splitter 1 input A1, the input A3 of driving amplifier 2 is outputted to from the first output terminals A 2 of the first power splitter 1, the signal of driving amplifier 2 to input amplifies, the input A5 of the second power splitter 4 is then outputted to from the output terminals A 4 of driving amplifier 2, the input A7 of the 4th power splitter 12 is outputted to from the output terminals A 6 of the second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of the first final amplifier 5, first final amplifier 5 pairs signal amplifies, distorted signal can be produced simultaneously, the signal be exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then the second input D2 of subtracter 8 is outputted to from the coupled end D1 of the first coupler 6.The output B5 of the first coupler 6 outputs signal the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the second mixer 16.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of the first coupler 6;
Error signal extraction circuit comprises the 3rd power splitter 9, first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 of the first error signal regulating circuit 10 exports the second regulating error signal, is connected with an input E6 of amplifying circuit 13 with the first final stage time delay; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 of the second error signal regulating circuit 11 exports the first regulating error signal, is connected with an input F4 of amplifying circuit 14 with the second final stage time delay;
Second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit 13, first final stage time delay is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, and another input E6 of the first final stage time delay and amplifying circuit 13 accesses the second regulating error signal; First final stage time delay is connected an input G4 of the first mixer 15 with the output G3 of amplifying circuit 13;
3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit 14, second final stage time delay is connected an output H1 of the second power splitter 4 with an input H2 of amplifying circuit 14, another input F4 of the second final stage time delay and amplifying circuit 14 accesses the first regulating error signal, and the second final stage time delay is connected another input H4 of the first mixer 15 with the output H3 of amplifying circuit 14.
The input signal time delay of subtracter 8 two inputs is equal, and error signal phase place in input signal is contrary, and amplitude is equal.
Further, in the above-described embodiments, the first final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit 13, and phase place is identical.
Further, in the above-described embodiments, the second final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit 14, and phase place is identical.
Further, in the above-described embodiments, the input signal time delay of two inputs of the first mixer 15 is equal, and error signal phase place in input signal is contrary, amplitude is not etc., the amplitude of the error signal that the first final amplifier 5 exports is bigger, realizes offseting in the first time of the first mixer 15 place error signal.
Further, in the above-described embodiments, the input signal time delay of two inputs of the second mixer 16 is equal, and error signal phase place in input signal is contrary, and amplitude is equal, and the second time finally realizing error signal offsets.
Further, in the above-described embodiments, as shown in Figure 4, the first final stage time delay comprises with amplifying circuit 14 the second delayer 17, second coupler 19 and the second final amplifier 18 be connected successively with amplifying circuit 13 or the second final stage time delay.Namely the output of the second delayer 17 connects the input of the second coupler 19, and the output of the second coupler 19 connects the input of the second final amplifier 18.
Further, in the above-described embodiments, as shown in Figure 5, first final stage time delay comprises with amplifying circuit 14 the 3rd delayer 20, the 3rd final amplifier 21 and the 3rd coupler 22 that are connected successively with amplifying circuit 13 or the second final stage time delay, namely the output of the 3rd delayer 20 connects the input of the 3rd final amplifier 21, the input of output the 3rd coupler 22 of the 3rd final amplifier 21.
Further, what above-described embodiment medial error signal extracting circuit extracted also can extract through amplifying signal from the second final amplifier 18 or the 3rd final amplifier 21.
Further, in above-described embodiment, driving amplifier 2 comprises N number of amplifier tube, and wherein N is natural number.
Further, in above-described embodiment, the first delayer 7, second delayer 17 and the 3rd delayer 20 are any one in delay line, integrated delayer or filtering wave by prolonging time device.
Further, in above-described embodiment, the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise the amplifier tube of N number of series connection or parallel connection, and wherein N is natural number.
Be illustrated in figure 6 the theory diagram of the reference signal regulating circuit 3 in the present invention, reference signal regulating circuit comprises the first amplitude modulator 23, first phase modulator 24, the 4th delay line 25 and the first prime amplifier 26.
The input that the main signal exported from the output C1 of the first power splitter 1 is input to the first amplitude modulator 23 carries out amplitude modulation, the output of the first amplitude modulator 23 is connected to the input of the first phase modulator 24, the signal of the first phase modulator 24 to input carries out phase modulation, the output of the first phase modulator 24 is connected to the input of the 4th delay line 25, the signal of 3rd delay line 25 to input carries out time delay, the output of the 3rd delay line 25 is connected to the input of the first prime amplifier 26, the signal of the first prime amplifier 26 to input amplifies, and the signal be exaggerated is exported by output.
Be illustrated in figure 7 the theory diagram of the first error signal regulating circuit 10 in the present invention and the second error signal regulating circuit 11, comprise the second amplitude modulator 27, second phase modulator 28 and the second prime amplifier 29.
Error signal through the 3rd power splitter 9 output is input to the input of the second amplitude modulator 27, second amplitude modulator 27 pairs error signal carries out amplitude modulation, the output of the second amplitude modulator 27 is connected to the input of the second phase modulator 28, the signal of the second phase modulator 28 to input carries out phase modulation, the output of the second phase modulator 28 is connected to the input of the second prime amplifier 29, the signal of the second prime amplifier 29 to input amplifies, the output output error conditioning signal of the second prime amplifier 29.
As shown in Figure 8,9, 10, be the structural representation of three kinds of embodiments of the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21.In Fig. 8, the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 23 in parallel and amplifier 24, and one end of its parallel connection connects power splitter 28, and the other end connects mixer 31; In Fig. 9, the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 33 in parallel, amplifier 34 and amplifier 35, and one end of its parallel connection connects power splitter 32, and the other end connects mixer 36; In Figure 10, the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 38 in parallel, amplifier 39, amplifier 40 and amplifier 41, and one end of its parallel connection connects power splitter 37, and the other end connects mixer 42.
In implementation process of the present invention, driving amplifier 2 can need selection to be in series by single or multiple amplifier tube according to the gain of the power amplifier complete machine of reality, in like manner the first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 can be that independently single amplifier tube is formed, also can be close road by N number of amplifier tube to form, wherein N is more than or equal to 2, concrete enforcement will according to the demanded power output of Feed Forward Power Amplifier, and the type selecting of final stage amplifier tube and determining.Itself there are enough rollbacks due to driving amplifier 2 and are all operated in category-A, therefore linear distortion is substantially negligible, other first final amplifier 5, amplifier in first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 is also be operated in category-A or AB class when designing, therefore the linear distortion of amplifier generation itself is also relatively little, first final stage amplifying circuit can be operated in different states as required, can be AB class also can be C class, amplifier when the first final amplifier is operated in C class and in the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 forms a Doherty amplifying circuit.First final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 are used as error amplifier in the implementation process of this programme to use, owing to there is no special error amplifier, therefore relative to traditional Feed Forward Power Amplifier, both hardware cost was saved, again reduce power consumption simultaneously, the efficiency of power amplifier product is effectively improved.Under the first final amplifier 5 works in the condition of C class A amplifier A, the efficiency of complete machine power amplifier can reach between 40-50% according to the difference of signal peak-to-average ratio.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improve and convert the protection range that all should belong to claims of the present invention.
Claims (14)
1. there is a High-efficiency power amplification circuit for three conjunction road, tunnel cancellation functions, it is characterized in that, comprise three end, tunnel amplifying circuit, reference signal circuit, error signal extraction circuit, the first mixer (15) and the second mixers (16); Described three end, tunnel amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Described reference signal circuit carries out amplitude to undistorted main signal and phase adjusted obtains reference signal;
Through amplifying signal in any road final stage amplifying circuit of described error signal extraction circuit extraction, this contains distorted signal and main signal through amplifying signal, this subtracts each other through amplifying signal and described reference signal by described error signal extraction circuit again, and respectively amplitude and phase adjusted are carried out to the error signal obtained after subtracting each other, obtain the first regulating error signal and the second regulating error signal, and be input in other two-way final stage amplifying circuit respectively;
The output signal of described first mixer to wherein two-way final stage amplifying circuit is carried out first time error signal and is offset;
The output signal of described second mixer to the output signal of described first mixer and an other road final stage amplifying circuit carries out the counteracting of second time error signal.
2. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to claim 1, is characterized in that, wherein:
Described first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connect successively; The input access main signal of described first power splitter (1); The output of described first delayer (7) connects an input of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect the output of described reference signal regulating circuit (3) and a coupled end of the first coupler (6) respectively;
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described 3rd power splitter (9) connects the output of subtracter (8), the input of described first error signal regulating circuit (10) connects an output of described 3rd power splitter (9), and the output of described first error signal regulating circuit (10) exports the second regulating error signal; The input of described second error signal regulating circuit (11) connects another output of described 3rd power splitter (9), and the output of described second error signal regulating circuit (11) exports the first regulating error signal;
Described second final stage amplifying circuit comprises the 4th power splitter (12) and the first final stage time delay and amplifying circuit (13), the input of described 4th power splitter (12) connects an output of described second power splitter (4), described first final stage time delay is connected an output of described 4th power splitter (12) with an input of amplifying circuit (13), another input of described first final stage time delay and amplifying circuit (13) accesses described first regulating error signal, described first final stage time delay is connected another input of described first mixer (15) with the output of amplifying circuit (13),
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit (14), described second final stage time delay is connected another output of described 4th power splitter (12) with an input of amplifying circuit (14), another input of described second final stage time delay and amplifying circuit (14) accesses the second regulating error signal; Described second final stage time delay is connected an input of the second mixer (16) with the output of amplifying circuit (14); Another input of described second mixer (16) connects the output of described first mixer (15).
3. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to claim 1, is characterized in that, wherein:
Described first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the 4th power splitter (12), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connect successively; The input access main signal of described first power splitter (1); The output of described first delayer (7) connects an input of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect the output of described reference signal regulating circuit (3) and a coupled end of the first coupler (6) respectively;
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described 3rd power splitter (9) connects the output of subtracter (8), the input of described first error signal regulating circuit (10) connects an output of described 3rd power splitter (9), and the output of described first error signal regulating circuit (10) exports the second regulating error signal; The input of described second error signal regulating circuit (11) connects another output of described 3rd power splitter (9), and the output of described second error signal regulating circuit (11) exports the first regulating error signal;
Described second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit (13), described first final stage time delay is connected an output of described second power splitter (4) with an input of amplifying circuit (13), another input of described first final stage time delay and amplifying circuit (13) accesses described first regulating error signal, and described first final stage time delay is connected another input of described first mixer (15) with the output of amplifying circuit (13);
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit (14), described second final stage time delay is connected an output of described 4th power splitter (12) with an input of amplifying circuit (14), another input of described second final stage time delay and amplifying circuit (14) accesses the second regulating error signal; Described second final stage time delay is connected an input of the second mixer (16) with the output of amplifying circuit (14); Another input of described second mixer (16) connects the output of described first mixer (15).
4. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to claim 1, is characterized in that, wherein:
Described first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the 4th power splitter (12), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connect successively; The input access main signal of described first power splitter (1); The output of described first delayer (7) connects an input of described second mixer (16); Another input of described second mixer (16) connects the output of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect the output of described reference signal regulating circuit (3) and a coupled end of the first coupler (6) respectively;
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described 3rd power splitter (9) connects the output of subtracter (8), the input of described first error signal regulating circuit (10) connects an output of described 3rd power splitter (9), and the output of described first error signal regulating circuit (10) exports the second regulating error signal; The input of described second error signal regulating circuit (11) connects another output of described 3rd power splitter (9), and the output of described second error signal regulating circuit (11) exports the first regulating error signal;
Described second final stage amplifying circuit comprises the first final stage time delay and amplifying circuit (13), described first final stage time delay is connected an output of described 4th power splitter (12) with an input of amplifying circuit (13), another input of described first final stage time delay and amplifying circuit (13) accesses the second regulating error signal; Described first final stage time delay is connected an input of the first mixer (15) with the output of amplifying circuit (13);
Described 3rd final stage amplifying circuit comprises the second final stage time delay and amplifying circuit (14), described second final stage time delay is connected an output of described second power splitter (4) with an input of amplifying circuit (14), another input of described second final stage time delay and amplifying circuit (14) accesses described first regulating error signal, and described second final stage time delay is connected another input of described first mixer (15) with the output of amplifying circuit (14).
5. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, the input signal time delay of described subtracter (8) two inputs is equal, and error signal phase place in input signal is contrary, and amplitude is equal.
6. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, described first final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit (13), and phase place is identical.
7. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, described second final stage time delay is equal with the input signal time delay of two inputs of amplifying circuit (14), and phase place is identical.
8. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, the input signal time delay of two inputs of described first mixer (15) is equal, and error signal phase place in input signal is contrary, and amplitude is not etc.
9. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, the input signal time delay of two inputs of described second mixer (16) is equal, and error signal phase place in input signal is contrary, and amplitude is equal.
10. the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, described first final stage time delay comprises with amplifying circuit (14) the second delayer (17), the second coupler (19) and the second final amplifier (18) that are connected successively with amplifying circuit (13) or described second final stage time delay.
11. High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, described first final stage time delay comprises with amplifying circuit (14) the 3rd delayer (20), the 3rd final amplifier (21) and the 3rd coupler (22) that are connected successively with amplifying circuit (13) or described second final stage time delay.
12. High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions according to any one of claim 2-4, it is characterized in that, described drive amplification circuit (2) comprises N number of amplifier tube, and wherein N is natural number.
13. according to the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions described in claim 11, it is characterized in that, the 3rd delayer (20) is delay line, any one in integrated delayer or filtering wave by prolonging time device.
14. according to the High-efficiency power amplification circuit with three conjunction road, tunnel cancellation functions described in claim 12, it is characterized in that, first final amplifier (5) or the 3rd final amplifier (21) comprise the amplifier tube of N number of series connection or parallel connection, and wherein N is natural number.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310081299.3A CN103219950B (en) | 2013-03-14 | 2013-03-14 | There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310081299.3A CN103219950B (en) | 2013-03-14 | 2013-03-14 | There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions |
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| CN103219950A CN103219950A (en) | 2013-07-24 |
| CN103219950B true CN103219950B (en) | 2016-04-27 |
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| CN1098572A (en) * | 1993-04-19 | 1995-02-08 | 美国电话电报公司 | Low-distortion feed-forward amplifier |
| US5877653A (en) * | 1995-11-16 | 1999-03-02 | Samsung Electronics Co., Ltd. | Linear power amplifier and method for removing intermodulation distortion with predistortion system and feed forward system |
| CN1321356A (en) * | 1999-09-01 | 2001-11-07 | 三菱电机株式会社 | Feedforward amplifier |
| CN203278753U (en) * | 2013-03-14 | 2013-11-06 | 武汉正维电子技术有限公司 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1098572A (en) * | 1993-04-19 | 1995-02-08 | 美国电话电报公司 | Low-distortion feed-forward amplifier |
| US5877653A (en) * | 1995-11-16 | 1999-03-02 | Samsung Electronics Co., Ltd. | Linear power amplifier and method for removing intermodulation distortion with predistortion system and feed forward system |
| CN1321356A (en) * | 1999-09-01 | 2001-11-07 | 三菱电机株式会社 | Feedforward amplifier |
| CN203278753U (en) * | 2013-03-14 | 2013-11-06 | 武汉正维电子技术有限公司 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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