CN103219241B - A kind of method preparing groove discrete semiconductor device - Google Patents
A kind of method preparing groove discrete semiconductor device Download PDFInfo
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- CN103219241B CN103219241B CN201210019197.4A CN201210019197A CN103219241B CN 103219241 B CN103219241 B CN 103219241B CN 201210019197 A CN201210019197 A CN 201210019197A CN 103219241 B CN103219241 B CN 103219241B
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Abstract
The invention discloses a kind of method preparing groove discrete semiconductor device, comprise the following steps: first with trench mask, the epitaxial layer implanting p-type adulterant on substrate is formed P type 1 district, and erode on epitaxial layer and form multiple gate trench；Then, medium between epitaxial layer surface deposits, recycling contact hole mask, inter-level dielectric is eroded, inter-level dielectric is formed perforate, is then injected into P type and n-type doping agent, form P type 2 district and N-type source region respectively, P type 1 district and P type 2 district synthesize P type base, epi-layer surface erodes formation contact hole groove afterwards, and contact hole groove is carried out metal plug filling；Finally, deposit metal level on the surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line, adopt this preparation method, eliminate the preparation section of base mask and active region mask, make the manufacturing cost of device obtain bigger reduction。
Description
Technical field
The present invention relates to semiconductor power discrete device technical field, specifically, the preparation method relating to a kind of trench semiconductor power discrete device。
Background technology
At present, power MOSFET (MetalOxideSemiconductorFieldEffectTransistor, mos field effect transistor) is widely used to each electron-like, communication product, computer, consumer appliances, automobile etc., meanwhile, it industrially also has multiple application。
Power semiconductor representated by power MOSFET, due to conducting resistance is low and can speed-sensitive switch, so it can efficiently control the big electric current of high frequency。Meanwhile, power MOSFET as mini power conversion element be just widely utilized the power pack at such as power amplifier, power converter, low noise amplifier and some personal computers switch, power circuit, be characterized in that low-power consumption, speed are fast。
Groove type power MOS FET, because of its have in structure efficiently and the low advantage of on-resistance characteristics, it is widely used as power supply control electronic device, the flourish of industry requires that power circuit has higher efficiency and less power consumption, require low price simultaneously, force manufacturer that cost of manufacture is reduced。
In the design and manufacture field of existing groove type power MOS FET, the base of MOSFET and source region are each to need base mask and active region mask step to introduce, in order to reduce manufacturing cost, propose before some, such as the american documentation literature US20110233667 disclosed, US20090085074, US20110233666, US077996427 etc., attempt the manufacture method omitting base or active region mask step, its step is complex, not easily generate, and the terminal of the semiconductor device produced (termination) structure is bad, so that the breakdown voltage of device and reliability are also relatively poor。
Summary of the invention
Instant invention overcomes shortcoming of the prior art, provide a kind of method preparing groove discrete semiconductor device, its compared with before groove type power discrete device manufacture method step few, eliminate base and active region mask step or only eliminate base masks, reduce the manufacturing cost of groove type power discrete device, and do not affect the electric property of groove type power discrete device, q&r, and then improve the ratio of performance to price of semiconductor device。
The present invention can be used for preparing the trench semiconductor power discrete device of 12V to 1200V。
In order to solve above-mentioned technical problem, the present invention is achieved by the following technical solutions:
A kind of method preparing groove discrete semiconductor device, comprises the following steps:
(1) utilize trench mask that the epitaxial layer 200 implanting p-type adulterant on substrate 10 is formed P type 1 district 201, and erode on epitaxial layer and form multiple gate trench；
(2) medium 401 between epitaxial layer surface deposits, recycling contact hole mask, inter-level dielectric is eroded, inter-level dielectric is formed perforate, it is then injected into P type and n-type doping agent, form P type 2 district 202 and N-type source region 204 respectively, afterwards epi-layer surface is eroded formation contact hole groove, and contact hole groove is carried out metal plug 502 fill；
(3) deposit metal level 404 at the upper surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line。
Further, described step (1) comprises the following steps:
A, on epitaxial layer formation oxide layer, accumulation lithography coating 1000 in oxide layer, portion of oxide layer is exposed again through trench mask, the portion of oxide layer exposed is carried out dry corrosion, until exposing epitaxial layer, form the multiple trench mask perforates in oxide layer, then dispose lithography coating；
B, at surface implanting p-type adulterant, have the part that former oxide layer covers not to be injected into, it does not have the part that former oxide layer covers can be injected into, and by a High temperature diffusion operation P-type dopant advanced and be diffused in epitaxial layer formation P type 1 district 201；
C, forming groove 300 by etching, this groove extends to epitaxial layer through P type 1 district, groove carries out the oxidation of sacrifice property, then disposes all oxide layers；
D, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon 301, then the polysilicon 302 of deposited n-type high dopant in the trench, to fill groove and to cover end face；
E, the polysilicon layer in epi-layer surface is carried out plane corrosion treatmentCorrosion Science or chemically mechanical polishing。
Further, it is characterised in that in step a, described multiple trench mask aperture widths are different, and width range therein is 0.2 μm to 2.0 μm。
Further, it is characterised in that in step a, after disposing lithography coating, form one layer of new oxide layer in the epi-layer surface exposed。
Further, it is characterised in that in step d, by thermally grown mode, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon。
Further, described step (1) comprises the following steps in a kind of modification (embodiment) of the present invention: in stepb, after the implanting p-type adulterant of surface, just precipitate layer of oxide layer and at least one the trench mask perforate in oxide layer is sealed up, the aperture widths sealed up can be 0.2 μm, or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, then oxide layer is carried out dry corrosion, remove the oxide layer in perforate, expose the epitaxial layer in perforate, subsequently enter step c, a High temperature diffusion operation need not be passed through。
Further, described step (1) comprises the following steps in a kind of modification (embodiment) of the present invention: in step c, before etching groove, first precipitate layer of oxide layer and at least one the trench mask perforate in oxide layer is sealed up, the aperture widths sealed up can be 0.2 μm, or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, the benefit of this step is to make the perforate of some trench mask have to be injected formation P type 1 district by P-type dopant but do not outputed groove, then oxide layer is carried out dry corrosion, remove the oxide layer in perforate, expose the epitaxial layer in perforate；Etching groove afterwards。
Further, it is characterised in that in stepb, a described High temperature diffusion processing temperature is 950
To 1200 DEG C, the time is 10 minutes to 1000 minutes。
Further, described step (2) comprises the following steps:
A, between top surface deposits medium；
B, at inter-level dielectric surface accumulation lithography coating, utilizing contact hole mask to expose part inter-level dielectric, then the part inter-level dielectric exposed being carried out dry corrosion, until exposing epitaxial layer, inter-level dielectric is formed multiple contact hole mask perforate, then disposes lithography coating；
C, at surface implanting p-type adulterant, the part that inter-level dielectric covers is had not to be injected into, there is no the part that inter-level dielectric covers, P-type dopant can be injected in epi-layer surface, and by secondary high-temperature diffusion operation, P-type dopant propelling is diffused in epitaxial layer and forms P type 2 district, P type 1 district and P type 2 district synthesize P type base 203；
D, surface inject n-type doping agent, the part that inter-level dielectric covers is had not to be injected into, not having the part that inter-level dielectric covers, n-type doping agent can be injected in epi-layer surface, and n-type doping agent propelling be diffused in P type base by three high temperature diffusion operation and form N-type source region 204；
E, by inter-level dielectric perforate, epi-layer surface is eroded, forms contact hole groove, contact hole groove enters in P type base through N-type source region, afterwards to contact hole groove implanting p-type high dopant；
F, on contact hole trenched side-wall, bottom and inter-level dielectric surface, it is sequentially depositing one layer of titanium layer and one layer of titanium nitride layer, then contact hole groove is carried out tungsten fills to form contact hole trench metal connector。
Further, described step (2) is characterised by, in step a, is sequentially depositing undoped silicon on top surface and boro-phosphorus glass forms inter-level dielectric。
Further, described step (2) is characterised by, in stepb, the aperture widths of described multiple contact hole masks is all the same size。
Further, described step (2) is characterised by, in stepb, described contact hole mask aperture widths is not all the same size, and width range is 0.2 μm to 1.6 μm。
Further, described step (2) is characterised by, described secondary high-temperature diffusion operation temperature is 950 to 1200 DEG C, and the time is 10 minutes to 1000 minutes, and described three high temperature diffusion operation temperature are 950 to 1200 DEG C, and the time is 10 minutes to 100 minutes。
Further, described step (2) comprises the following steps in a kind of modification (embodiment) of the present invention:
In step e, before etching contact hole groove, first precipitate layer of oxide layer, then oxide layer is carried out dry corrosion, dispose the oxide layer in perforate, expose the epitaxial layer in perforate；Etching contact hole groove afterwards, other steps are identical with described step (2), and the benefit of this step is to make from the P type high dopant of contact hole groove injection relatively not close to trenched side-wall (raceway groove of device)。
Further, described step (2) comprises the following steps in a kind of modification (embodiment) of the present invention: in step e, the width of contact hole mask perforate is not all the same size, before etching contact hole groove, first precipitate layer of oxide layer and at least one the contact hole mask perforate in inter-level dielectric is sealed up, the aperture widths sealed up can be 0.2 μm or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, the benefit of this step is that the contact hole perforate making those be sealed up does not have metal plug wherein, also without forming contact hole groove；Then oxide layer is carried out dry corrosion, dispose the oxide layer in the contact hole perforate do not sealed up, expose the epitaxial layer in perforate；Etching contact hole groove afterwards, other steps are identical with described step (2)。
Further, described step (2) comprises the following steps in a kind of modification (embodiment) of the present invention:
In step d, the width of contact hole mask perforate is not all the same size, before n-type doping agent is injected on surface, first precipitate layer of oxide layer and at least one the contact hole mask perforate in inter-level dielectric is sealed up, the aperture widths sealed up can be 0.2 μm or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, the benefit of this step is that the contact hole perforate making those be sealed up is not injected by n-type doping agent and do not have metal plug wherein, also without forming contact hole groove；Then surface being injected n-type doping agent, at this moment n-type doping agent can only inject those perforates do not sealed up, and other steps are identical with described (2)。
The preparation method of the present invention also can be used for only eliminating base mask and source region needs active region mask step to introduce, and its preparation method comprises the following steps:
(1) utilize trench mask that the epitaxial layer 200 implanting p-type adulterant on substrate 10 is formed P type base, and erode on epitaxial layer and form multiple gate trench；
(2) active region mask step is utilized to form source region；
(3) medium between epitaxial layer surface deposits, recycling contact hole mask forms contact hole groove, and contact hole groove is carried out metal plug filling；
(4) deposit metal level at the upper surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line。
Further, described step (1) comprises the following steps:
A, on epitaxial layer formation oxide layer, accumulation lithography coating in oxide layer, portion of oxide layer is exposed again through trench mask, the portion of oxide layer exposed is carried out dry corrosion, until exposing epitaxial layer, forming multiple trench mask perforates in oxide layer, trench mask aperture widths is different, width range therein is 0.2 μm to 2.0 μm, then disposes lithography coating；
B, to surface implanting p-type adulterant, the part that former oxide layer covers is had not to be injected into, not having the part that former oxide layer covers, P-type dopant can be injected in epi-layer surface, and P-type dopant propelling be diffused in epitaxial layer by a High temperature diffusion operation and form P type base；
C, forming groove by being etched in tapping, this groove extends in epitaxial layer through P type base, groove carries out the oxidation of sacrifice property, then disposes all oxide layers；
D, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon, then the polysilicon of deposited n-type high dopant in the trench, to fill groove and to cover end face；
E, the polysilicon layer in epi-layer surface is carried out plane corrosion treatmentCorrosion Science or chemically mechanical polishing。
Further, described step (1), in stepb, after the implanting p-type adulterant of surface, just precipitation layer of oxide layer at least one the trench mask perforate in oxide layer is sealed up, the aperture widths sealed up can be 0.2 μm, or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, then oxide layer is carried out dry corrosion, removes the oxide layer in perforate, expose the epitaxial layer in perforate, subsequently enter step c, a High temperature diffusion operation need not be passed through。
Compared with prior art, the invention has the beneficial effects as follows:
The preparation method adopting the present invention, eliminates the preparation section of base mask and active region mask or only eliminates the preparation section of base mask, make the manufacturing cost of device obtain bigger reduction；Simultaneously without influence on the original electrical characteristic of device, thus adding the ratio of performance to price of device, and do not affect the q&r of groove type power discrete device。
Accompanying drawing explanation
Accompanying drawing is used for providing a further understanding of the present invention, is used for together with embodiments of the present invention explaining the present invention, is not intended that limitation of the present invention, in the accompanying drawings:
Fig. 1 is exposure oxide layer 400 schematic diagram of the embodiment of the present invention 1；
Fig. 2 is the exposure epitaxial layer schematic diagram of the embodiment of the present invention 1；
Fig. 3 is the implanting p-type adulterant schematic diagram of the embodiment of the present invention 1；
Fig. 4 is P type 1 district 201 schematic diagram of the embodiment of the present invention 1；
Fig. 5 is groove 300 schematic diagram of the embodiment of the present invention 1；
Fig. 6 be the embodiment of the present invention 1 dispose all sacrifice oxide layer schematic diagrams；
Fig. 7 is grid oxic horizon 301 schematic diagram of the embodiment of the present invention 1；
Fig. 8 is highly doped polysilicon 302 schematic diagram of deposition of the embodiment of the present invention 1；
Fig. 9 be the embodiment of the present invention 1 carry out plane treatment schematic diagram；
Figure 10 is inter-level dielectric 401 schematic diagram of the embodiment of the present invention 1；
Figure 11 be the embodiment of the present invention 1 to contact hole to implanting p-type adulterant schematic diagram；
Figure 12 is P type base 203 schematic diagram of the embodiment of the present invention 1；
Figure 13 be the embodiment of the present invention 1 to contact hole to inject n-type doping agent schematic diagram；
Figure 14 is N-type source region 204 schematic diagram of the embodiment of the present invention 1；
The contact hole groove that Figure 15 is the embodiment of the present invention 1 shows 501 intentions；
Figure 16 is metal plug 502 schematic diagram of the embodiment of the present invention 1；
Figure 17 is albronze layer 404 schematic diagram of the embodiment of the present invention 1；
Figure 18 is the cross sectional representation of the device of the embodiment of the present invention 2 (a kind of modification of the present invention)；
Figure 19 is the cross sectional representation of the device of the embodiment of the present invention 3 (a kind of modification of the present invention)；
Figure 20 is the cross sectional representation of the device of the embodiment of the present invention 4 (a kind of modification of the present invention)；
Figure 21 is the cross sectional representation of the device of the embodiment of the present invention 5 (a kind of modification of the present invention)；
Figure 22 is the cross sectional representation of the device of the embodiment of the present invention 6 (a kind of modification of embodiment)。
Detailed description of the invention
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are illustrated, it will be appreciated that preferred embodiment described herein is merely to illustrate and explains the present invention, is not intended to limit the present invention。
A kind of method preparing groove discrete semiconductor device of the present invention, comprises the following steps: first with trench mask, the epitaxial layer implanting p-type adulterant on substrate is formed P type 1 district, and erodes on epitaxial layer and form multiple gate trench；Then, medium between epitaxial layer surface deposits, recycling contact hole mask, inter-level dielectric is eroded, inter-level dielectric is formed perforate, is then injected into P type and n-type doping agent, form P type 2 district and N-type source region respectively, afterwards epi-layer surface is eroded formation contact hole groove, and contact hole groove is carried out metal plug filling；Finally, deposit metal level on the surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line。
Embodiment 1:
As shown in Figure 1, epitaxial layer 200 is placed in the top of substrate 10, first epitaxial layer accumulation is used above or thermally grown mode forms oxide layer 400 (thickness is 0.3 μm to 1.5 μm oxide hard light shield), accumulation one layer photoetching coating 1000 again in oxide layer, then passes through trench mask and forms pattern and expose the some parts of oxide layer。
As in figure 2 it is shown, trench mask is formed after the oxide layer that exposes of pattern carries out dry corrosion, expose epitaxial layer, then dispose lithography coating。
As it is shown on figure 3, to silicon chip surface implanting p-type adulterant, (dosage is 2e12/cm3To 2e14/cm3), there is the part that former oxide layer 400 covers not to be injected into, it does not have the part that former oxide layer covers, P-type dopant can be injected in epi-layer surface and form p type island region, and P-type dopant can adopt B11 (boron boron)。
As shown in Figure 4, the P-type dopant of injection is pushed into by a High temperature diffusion operation (time is 10 minutes to 1000 minutes, and temperature is 950 DEG C to 1200 DEG C) and is diffused in epitaxial layer and forms P type 1 district 201。The P type 1 district degree of depth (degree of depth is 0.3 μm to 4.0 μm) that this step is formed not is ultimate depth, because also having other work in hot environment after this step, so, the P type 1 district degree of depth that this step is formed suitably to adjust。
As it is shown in figure 5, form groove 300 by etching, this groove (degree of depth is 1.0 μm to 7.0 μm, and width is 0.2 μm to 2.0 μm) extends to N-type epitaxy layer through P type 1 district。
As shown in Figure 6, after formation of the groove, groove carries out the oxidation of sacrifice property, and (time is 10 minutes to 100 minutes, temperature is 1000 DEG C to 1200 DEG C), with the silicon layer (P type alloy can be pushed further into being diffused into epitaxial layer by the oxidation operation of sacrifice property) that elimination is destroyed by plasma in grooving process, then dispose all oxide layers。
As it is shown in fig. 7, and by thermally grown mode, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon 301 (thickness is 0.02 μm to 0.12 μm) a layer thin。
As shown in Figure 8, the polysilicon 302 of deposited n-type high dopant in the trench, polysilicon doping concentration is RS=5 Ω/ to 100 Ω/ (sheet resistance), to fill groove and to cover end face。
As it is shown in figure 9, then the polysilicon layer in epi-layer surface to be carried out plane corrosion treatmentCorrosion Science or chemically mechanical polishing。
As shown in Figure 10, epitaxial layer most surface first deposits undoped silicon dioxide layer (thickness is 0.1 μm to 0.5 μm), then deposit boro-phosphorus glass (thickness is 0.1 μm to 0.8 μm) and form inter-level dielectric 401。
As shown in figure 11, at inter-level dielectric surface accumulation lithography coating, contact hole mask is utilized to expose part inter-level dielectric, then the part inter-level dielectric exposed is carried out dry corrosion, until exposing epitaxial layer, inter-level dielectric being formed multiple contact hole mask perforate 500, then disposes lithography coating；Then (boron, dosage is 2e12/cm to epitaxial layers implanting p-type adulterant3To 2e14/cm3)。
As shown in figure 12, by secondary high-temperature DIFFUSION TREATMENT, work in hot environment temperature is 950 to 1200 DEG C, and the time is 10 minutes to 1000 minutes, makes P-type dopant push away and is diffused on epitaxial layer and forms P type 2 district, and P type 1 district and P type 2 district synthesize P type base 203。
As shown in figure 13, then epitaxial layers inject n-type doping agent (phosphorus or arsenic, dosage is 1e15/cm3To 2e16/cm3), epitaxial layer is formed N-type region。
As shown in figure 14, by three high temperature DIFFUSION TREATMENT, temperature is 950 to 1200 DEG C, and the time is 10 minutes to 100 minutes, make N-type region push away and be diffused into P type base formation N-type source region 204 (N-type active area depth is 0.2 μm to 0.8 μm, and the P type base degree of depth is 0.5 μm to 4.5 μm)。
As shown in figure 15, pass through contact hole mask, epitaxial layer containing adulterant is carried out etch, (degree of depth is 0.4 μm to 1.0 μm to make contact hole groove 501, width is 0.2 μm to 1.6 μm) enter into P type base through N-type source region, afterwards to contact hole groove implanting p-type high dopant 205, assorted agent concentration is 1014To 5 × 1015/cm3, to reduce the contact resistance between P type base and metal plug, this increases the safe handling district of device effectively。
As shown in figure 16, deposit one layer of titanium/titanium nitride layer 402 at contact hole trenched side-wall, bottom and epitaxial layer upper surface, then contact hole groove is carried out tungsten 403 and fills to form metal plug 502。
As shown in figure 17, at one layer of aluminium copper deposited above 404 (thickness is 0.8 μm to 10 μm) of this device, then pass through metal mask and carry out metal etch, form metal pedestal layer and line。
Embodiment 2:
The technical scheme of the present embodiment is roughly the same with embodiment 1, and it differs only in:
In above-described embodiment 1 before Fig. 5 etching groove, first precipitate layer of oxide layer and the trench mask aperture widths scope in oxide layer is sealed up by the perforate of 0.2 μm to 0.6 μm, the aperture widths sealed up can be 0.2 μm or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, the benefit of this step is to make the perforate of some trench mask have to be injected (P type 1 district) by P-type dopant but do not outputed groove, the terminal structure of device is better, thus the breakdown voltage of device is higher and more stable, then oxide layer is carried out dry corrosion, remove the oxide layer in perforate, expose the epitaxial layer in perforate；Etching groove afterwards, at this moment the perforate that those not precipitated oxide layers are sealed up is only had just to be outputed groove, (degree of depth is 1.0 μm to 7.0 μm to this groove, width is 0.2 μm to 2.0 μm) extend to epitaxial layer through P type 1 district, other steps are identical with embodiment 1, and the cross section of device is as shown in figure 18。
Embodiment 3:
The technical scheme of the present embodiment is roughly the same with embodiment 1, and it differs only in:
In above-described embodiment 1, Figure 15 is before etching contact hole groove, first one layer of (LPCVD) oxide layer of precipitation, and then oxide layer carries out dry corrosion, removes the oxide layer in contact hole trenches openings, exposes the epitaxial layer in perforate；Etching contact hole groove afterwards。Other steps are basic identical with embodiment 1, and the cross section of device is as shown in figure 19。
Embodiment 4:
The technical scheme of the present embodiment is roughly the same with embodiment 2, and it differs only in:
In above-described embodiment 2, before etching contact hole groove, first one layer of (LPCVD) oxide layer of precipitation, then oxide layer is carried out dry corrosion, removes the oxide layer in contact hole trenches openings, expose the epitaxial layer in perforate；Etching contact hole groove afterwards。Other steps are basic identical with embodiment 2, and the cross section of device is as shown in figure 20。
Embodiment 5:
A kind of modification for the present invention。
Step is identical with embodiment 1, simply:
Before the adulterant in N-type source region is injected on surface, first precipitate layer of oxide layer and contact hole mask aperture widths scope in inter-level dielectric is sealed up by the perforate of 0.2 μm to 0.6 μm, the aperture widths sealed up can be 0.2 μm or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, then surface is injected the adulterant in N-type source region, other steps are identical with step described in embodiment 1, and the cross section of device is as shown in figure 21。
The benefit of embodiment 5 is that the contact hole perforate making those be sealed up is not injected by n-type doping agent and do not have metal plug wherein, also without forming contact hole groove。
Embodiment 6:
A kind of modification for the present invention。
Step is identical with embodiment 2, simply:
Before the adulterant in N-type source region is injected on surface, first precipitate layer of oxide layer and contact hole mask aperture widths scope in inter-level dielectric is sealed up by the perforate of 0.2 μm to 0.6 μm, the aperture widths sealed up can be 0.2 μm or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm not etc., depending on preparation method, then surface is injected the adulterant in N-type source region, other steps are identical with step described in embodiment 2, and the cross section of device is as shown in figure 22。
The benefit of embodiment 6 is to make the perforate of some trench mask have to be injected (P type 1 district) by P-type dopant but do not outputed groove, some contact hole perforate has by P-type dopant injection (P type 2 district) but is not injected by n-type doping agent and do not have metal plug wherein, also without forming contact hole groove, the benefit of this embodiment is to make the terminal structure of device better, thus the breakdown voltage of device is higher and more stable。
Last it is noted that these are only the preferred embodiments of the present invention, it is not limited to the present invention, the present invention can be used for relating to manufacturing trench semiconductor power discrete device (such as, insulated trench gate bipolar transistor (TrenchIGBT) or trench diode, groove has special based diode), the present invention can be used for preparing the trench semiconductor power discrete device of 12V to 1200V, embodiments of the invention are to make an explanation with N-type passage device, the present invention also can be used for P type passage device, although the present invention being described in detail with reference to embodiment, for a person skilled in the art, technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent replacement, but all within the spirit and principles in the present invention, the any amendment made, equivalent replacement, improve, should be included in protection scope of the present invention it。
Reference marks table:
10 substrates
200 epitaxial layers
201P type 1 district
202P type 2 district
203P type base
204N type source region
The P type high-doped zone of 205 contact hole channel bottoms
300 grooves
301 grid oxic horizons
302 highly doped polysilicons
400 oxide layers
401 inter-level dielectrics
402 titaniums/titanium nitride
403 tungsten
404 aluminium coppers
405LPCVD oxide layer
The 500 contact hole mask perforates formed in inter-level dielectric
501 contact hole grooves
502 metal plugs
1000 lithography coatings
Claims (12)
1. the method preparing groove discrete semiconductor device, it is characterised in that comprise the following steps, and as follows successively:
(1) utilize trench mask that the epitaxial layer implanting p-type adulterant on substrate is formed P type 1 district, and erode on epitaxial layer and form multiple gate trench；
(2) medium between epitaxial layer surface deposits, recycling contact hole mask, inter-level dielectric is eroded, inter-level dielectric is formed perforate, it is then injected into P type and n-type doping agent, form P type 2 district and N-type source region respectively, afterwards epi-layer surface is eroded formation contact hole groove, and contact hole groove is carried out metal plug filling；
(3) deposit metal level on the surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line。
2. a kind of method preparing groove discrete semiconductor device according to claim 1, it is characterised in that described step (1) comprises the following steps:
A, on epitaxial layer formation oxide layer, accumulation lithography coating in oxide layer, portion of oxide layer is exposed again through trench mask, the portion of oxide layer exposed is carried out dry corrosion, until exposing epitaxial layer, forming multiple trench mask perforates in oxide layer, trench mask aperture widths is different, width range therein is 0.2 μm to 2.0 μm, then disposes lithography coating；
B, to surface implanting p-type adulterant, the part that former oxide layer covers is had not to be injected into, not having the part that former oxide layer covers, P-type dopant can be injected in epi-layer surface, and P-type dopant propelling be diffused in epitaxial layer by a High temperature diffusion operation and form P type 1 district；
C, forming groove by being etched in tapping, this groove extends in epitaxial layer through P type 1 district, groove carries out the oxidation of sacrifice property, then disposes all oxide layers；
D, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon, then the polysilicon of deposited n-type high dopant in the trench, to fill groove and to cover end face；
E, the polysilicon layer in epi-layer surface is carried out plane corrosion treatmentCorrosion Science or chemically mechanical polishing。
3. a kind of method preparing groove discrete semiconductor device according to claim 2, it is characterised in that in step a, after disposing lithography coating, forms one layer of new oxide layer in the epi-layer surface exposed。
4. a kind of method preparing groove discrete semiconductor device according to claim 2, it is characterized in that, in stepb, after the implanting p-type adulterant of surface, just precipitate layer of oxide layer and at least one the trench mask perforate in oxide layer is sealed up, the aperture widths sealed up is 0.2 μm, or 0.3 μm or 0.4 μm or 0.5 μm or 0.6 μm, then oxide layer is carried out dry corrosion, remove the oxide layer in perforate, expose the epitaxial layer in perforate, subsequently enter step c, a High temperature diffusion operation need not be passed through。
5. a kind of method preparing groove discrete semiconductor device according to claim 2, it is characterized in that, in step c, before etching groove, first precipitate layer of oxide layer and at least one the trench mask perforate in oxide layer is sealed up, then oxide layer is carried out dry corrosion, removing the oxide layer in perforate, expose the epitaxial layer in perforate, afterwards etching groove。
6. a kind of method preparing groove discrete semiconductor device according to claim 1, it is characterised in that described step (2) comprises the following steps:
A, between top surface deposits medium；
B, at inter-level dielectric surface accumulation lithography coating, contact hole mask is utilized to expose part inter-level dielectric, then the part inter-level dielectric exposed is carried out dry corrosion, until exposing epitaxial layer, inter-level dielectric is formed multiple contact hole mask perforate, multiple contact hole mask aperture widths are without all the same sizes, and width range is 0.2 μm to 1.6 μm, then disposes lithography coating；
C, at surface implanting p-type adulterant, the part that inter-level dielectric covers is had not to be injected into, there is no the part that inter-level dielectric covers, P-type dopant can be injected in epi-layer surface, and by secondary high-temperature diffusion operation, P-type dopant propelling is diffused in epitaxial layer and forms P type 2 district, P type 1 district and P type 2 district synthesize P type base；
D, surface inject n-type doping agent, the part that inter-level dielectric covers is had not to be injected into, not having the part that inter-level dielectric covers, n-type doping agent can be injected in epi-layer surface, and n-type doping agent propelling be diffused in P type base by three high temperature diffusion operation and form N-type source region；
E, by inter-level dielectric perforate, epi-layer surface is eroded, forms contact hole groove, contact hole groove enters into P type base through N-type source region, afterwards to contact hole groove implanting p-type high dopant；
F, on contact hole trenched side-wall, bottom and inter-level dielectric surface, it is sequentially depositing one layer of titanium layer and one layer of titanium nitride layer, then contact hole groove is carried out tungsten fills to form trench metal connector。
7. a kind of method preparing groove discrete semiconductor device according to claim 6, it is characterized in that, in step d, the width of contact hole mask perforate is not all the same size, before n-type doping agent is injected on surface, first precipitate layer of oxide layer and at least one the contact hole mask perforate in inter-level dielectric is sealed up, then n-type doping agent being injected on surface。
8. a kind of method preparing groove discrete semiconductor device according to claim 6, it is characterized in that, in step e, before epi-layer surface is carried out contact hole trench erosion, first precipitate layer of oxide layer, then oxide layer is carried out dry corrosion, removes the oxide layer in interlayer dielectric openings, expose the epitaxial layer in perforate；Etching contact hole groove afterwards。
9. a kind of method preparing groove discrete semiconductor device according to claim 6, it is characterized in that, in step e, the width of contact hole mask perforate is not all the same size, before etching contact hole groove, first precipitate layer of oxide layer and at least one the contact hole mask perforate in inter-level dielectric is sealed up, then oxide layer being carried out dry corrosion, dispose the oxide layer in the contact hole perforate do not sealed up, expose the epitaxial layer in perforate；Then etching contact hole groove, afterwards to contact hole groove implanting p-type high dopant。
10. the method preparing groove discrete semiconductor device, it is characterised in that comprise the following steps, and as follows successively:
(1) utilize trench mask that the epitaxial layer implanting p-type adulterant on substrate is formed P type base, and erode on epitaxial layer and form multiple gate trench；
(2) active region mask is utilized to form source region；
(3) medium between epitaxial layer surface deposits, recycling contact hole mask forms contact hole groove, and contact hole groove is carried out metal plug filling；
(4) deposit metal level at the upper surface of device, utilize metal mask to carry out metal attack, form metal pedestal layer and line。
11. a kind of method preparing groove discrete semiconductor device according to claim 10, it is characterised in that described step (1) comprises the following steps:
A, on epitaxial layer formation oxide layer, accumulation lithography coating in oxide layer, portion of oxide layer is exposed again through trench mask, the portion of oxide layer exposed is carried out dry corrosion, until exposing epitaxial layer, forming multiple trench mask perforates in oxide layer, trench mask aperture widths is different, width range therein is 0.2 μm to 2.0 μm, then disposes lithography coating；
B, to surface implanting p-type adulterant, the part that former oxide layer covers is had not to be injected into, not having the part that former oxide layer covers, P-type dopant can be injected in epi-layer surface, and P-type dopant propelling be diffused in epitaxial layer by a High temperature diffusion operation and form P type base；
C, forming groove by being etched in tapping, this groove extends in epitaxial layer through P type base, groove carries out the oxidation of sacrifice property, then disposes all oxide layers；
D, the sidewall that expose at groove and bottom, and the upper surface of epitaxial layer forms grid oxic horizon, then the polysilicon of deposited n-type high dopant in the trench, to fill groove and to cover end face；
E, the polysilicon layer in epi-layer surface is carried out plane corrosion treatmentCorrosion Science or chemically mechanical polishing。
12. the preparation method of groove discrete semiconductor device according to claim 11, it is characterized in that, in step c, before etching groove, first precipitate layer of oxide layer and at least one the trench mask perforate in oxide layer is sealed up, then oxide layer is carried out dry corrosion, removing the oxide layer in perforate, expose the epitaxial layer in perforate, afterwards etching groove。
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| CN101777514A (en) * | 2010-02-03 | 2010-07-14 | 香港商莫斯飞特半导体有限公司 | A kind of trench semiconductor power device and preparation method thereof |
| CN101901765A (en) * | 2009-03-17 | 2010-12-01 | 三菱电机株式会社 | Method of manufacturing power semiconductor device |
| CN101997030A (en) * | 2009-08-17 | 2011-03-30 | 力士科技股份有限公司 | Trench metal-oxide-semiconductor field effect transistor (MOSFET) with shallow trench structure and manufacturing method thereof |
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| US6281547B1 (en) * | 1997-05-08 | 2001-08-28 | Megamos Corporation | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask |
| KR100385859B1 (en) * | 2000-12-27 | 2003-06-02 | 한국전자통신연구원 | Trench gate MOSFET fabricated by using hydrogen annealing and self-align technique |
| CN101834142B (en) * | 2010-05-21 | 2012-11-14 | 香港商莫斯飞特半导体有限公司 | Method for manufacturing flute with thick insulating bottom and semiconductor device thereof |
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| CN101997030A (en) * | 2009-08-17 | 2011-03-30 | 力士科技股份有限公司 | Trench metal-oxide-semiconductor field effect transistor (MOSFET) with shallow trench structure and manufacturing method thereof |
| CN101777514A (en) * | 2010-02-03 | 2010-07-14 | 香港商莫斯飞特半导体有限公司 | A kind of trench semiconductor power device and preparation method thereof |
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