CN103219037A

CN103219037A - In-chip memory with multi-port read-write

Info

Publication number: CN103219037A
Application number: CN201310140319XA
Authority: CN
Inventors: 龙希田; 杨杰; 石匆; 吴南健
Original assignee: Institute of Semiconductors of CAS
Current assignee: Institute of Semiconductors of CAS
Priority date: 2013-04-22
Filing date: 2013-04-22
Publication date: 2013-07-24
Anticipated expiration: 2033-04-22
Also published as: CN103219037B

Abstract

The invention discloses an in-chip memory with multi-port read-write. The in-chip memory comprises three stages of circuit structures connected in order, wherein the first-stage circuit structure is used for locking and storing input data and gating a storage unit, the second-stage circuit structure is used for writing and storing the data in the storage unit, and the third-stage circuit structure is used for reading out the stored data, the first-stage circuit structure comprises a write address decoder, a clock gating logic circuit and a data input latch, and the input end of the first-stage circuit structure is connected with the output end of the clock gating logic circuit; the second-stage circuit structure comprises a plurality of static random storage units, and the input end of the second-stage circuit structure is respectively connected with the output ends of the write address decoder and the data input latch; and the third-stage circuit structure comprises a multiplexer, the input end of the third-stage circuit structure is connected with the output ends of the plurality of static random storage units, the output end of a read address decoder is respectively connected with the input end of the multiplexer, and the input end of the data output latch is connected with the output end of the multiplexer.

Description

The on-chip memory of multiport read-write

Technical field

The invention belongs to integrated circuit fields, particularly the on-chip memory of a kind of multiport read-write in the digital circuit.

Background technology

For demands such as the quick access of satisfying data and metadata caches, nearly all chip internal is all integrated on-chip memory.These on-chip memories (such as the cache in the processor) are participated in its main operational usually directly in data path, have the multiport read-write, and access speed requires high, and single memory capacity is less, but characteristics such as One's name is legion.Huge day by day along with the circuit design scale, and the developing rapidly of single-chip multi-core parallel concurrent processor, digit chip is increasing to the demand of data path buffer memory in the sheet, and its area summation has occupied appreciable ratio in the entire chip area.

At present, in the on-chip memory design, mainly with static RAM (SRAM), register file, these 3 kinds of structures of latch arrays are the most common.For the SRAM structure, 6 pipe unit type SRAM are example with standard, though the area that storage unit takies is little, access speed is also very fast, because the use of sense amplifier makes SRAM when being used for the low capacity storage, have expended a lot of extra areas.Register file and latch display relatively is fit to the data of storage low capacity by contrast, and the two respectively has relative merits.Register file has good temporal characteristics, be suitable for use in very much in the synchronizing sequential circuit, and be supported in and same unit carried out read-write operation in the same cycle, latch arrays sequential expense is big, can not support to read while write, but under the same memory cell number, can take than register file and lack the area that is close to half.

In sum, existing stored structure all can not be well under the situation of guaranteed performance, and save area reduces manufacturing cost, takes into account area and performance so press for a kind of new memory circuitry.Read and write particularly (low-power consumption) clock synchronization storer of write once read many and the present invention has designed a kind of novel support multiport, utilize the less SRAM storage unit of area to realize the temporal characteristics of register.

Summary of the invention

The objective of the invention is to, a kind of on-chip memory of multiport read-write is provided, described on-chip memory can support multiport to read and write particularly write once read many, has low in power consumption.

The invention provides a kind of on-chip memory of multiport read-write, comprising:

Three grades of circuit structures of Lian Jieing successively, first order circuit structure are used to import the gating with storage unit of latching of data, and second level circuit structure is used for the data write storage unit and stores, and the tertiary circuit structure is used to store reading of data, wherein,

This first order circuit structure comprises the write address code translator, clock gated logic circuit, and data input latch device, and its input end is connected with the output terminal of clock gated logic circuit;

This second level circuit structure comprises a plurality of static ram cells, and its input end is connected with the output terminal of write address code translator with the data input latch device respectively;

This tertiary circuit structure comprises MUX, and its input end links to each other with each output terminal of a plurality of static ram cells; Read address decoder, its output terminal is connected with the input end of MUX respectively; The data output latch, its input end is connected with the output terminal of MUX.

The present invention possesses following advantage: 1. because generally speaking, data output latch number n is far smaller than memory depth k, so in this storer, except address decoding circuitry and static storage cell, the area of other peripheral circuits almost can be ignored, so this storer has greater advantage on area.2. circuit structure is fairly simple, only is suitable for the clock control that a clock gated logic has just been finished whole storer, and not only power consumption is lower than latch arrays that does not adopt low power dissipation design and register file, and clock load very down.A clock can easily drive a huge memory circuit.3. this storer can be expanded very easily, such as when storer is expanded on bit wide, read/write address code translator and clock gated logic can carry out multiplexing, therefore saved area to a greater extent, secondly the small-capacity memory of this write once read many can constitute the multiport memory of writing mutiread very easily, be used in some specific occasions, this storer can also well adapt to the address decoding mode (embodiment 2 that specifically can see below) of half decode in addition, to reduce the logical block that decoding scheme expends.4. this storer is similar with register file on sequential, allows same storage unit to be read while write, this also be simple latch display and SRAM storer can not accomplish.

Description of drawings

For further illustrating content of the present invention and advantage, below in conjunction with accompanying drawing and example in detail as after, wherein:

Fig. 1 is a structural representation of the present invention.

Fig. 2 is the structural representation of first embodiment of the invention.

Fig. 3 is the circuit diagram of static ram cell 21 among Fig. 1.

Fig. 4 is the read-write sequence figure of Fig. 2 embodiment.

Fig. 5 is the structural representation of second embodiment of the invention.

Fig. 6 is the structured flowchart that the present invention acts on the chip multi-core system.

Embodiment

See also shown in Figure 1ly, the on-chip memory of a kind of multiport read-write comprises:

Three grades of circuit structures of Lian Jieing successively, first order circuit structure 1 is used to import the gating with storage unit of latching of data, and second level circuit structure 2 is used for the data write storage unit and stores, and tertiary circuit structure 3 is used to store reading of data, wherein

This first order circuit structure 1 comprises write address code translator 11, clock gated logic circuit 12; And data input latch device 13, its input end is connected with the output terminal of clock gated logic circuit 12; Described data input latch device 13 has data input pin, and it is input as 1 bit write data, and outputs to each input end of a plurality of static ram cells 21.Described clock gated logic circuit 12 has the input clock end and writes Enable Pin, and described write address code translator 11 is according to write address and write enable signal and decode.

The function of first order circuit structure 1 is to finish the gating with storage unit of latching of input data in the described storer, and its detailed process is as follows:

1. the clock gated logic circuit 12, by writing the control of enable signal and clock signal, when writing enable signal and be logic low " 0 ", clock gated logic circuit 12 is output as logic low " 0 ", gated clock is closed, when writing enable signal and be logic high " 1 ", gated clock is reopened, and the door controling clock signal of output is opposite with the input clock signal phase place.

2. working as described storer input clock is logic low, when gated clock is logic high, 13 pairs of data input latch devices want the data of data input pin to sample, when described storer input clock rising edge, data in the data input latch device 13 are latched, this moment, the data of external data input end were isolated (the latch is here thought positive latch, if the negative latch principle of use is similar in this).

3. write address code translator 11 is according to the write address of input with write enable signal and decode, if write enable signal is logic high " 1 ", write address code translator 11 is with the OPADD decoded signal, this signal has only and the output terminal of write address correspondence effective (for logic high " 1 "), effectively output terminal will control correspondence in the second level circuit structure 2 static ram cell 21 write new data, if write enable signal is logic low " 0 ", and all output all is logic low " 0 ".

Sequential power consumption characteristics in the described storer in the first order circuit structure 1 is as follows:

1. writing enable signal should change during for low level at input clock, is logic low " 0 " in case write enable signal, and the first order circuit structure 1 of described storer and second level circuit structure 2 be no longer occurrence logic upset all, enters low power consumpting state.

2. the input of write address and data all should be set up during input clock is logic high and be finished, and keeping a clock period at least changes again, that is to say that the input of write address and data can not change when the input clock low level, the variation of write address and data input should be synchronous with the rising edge of input clock generally speaking.

This second level circuit structure 2 comprises a plurality of static ram cells 21, its input end is connected with the output terminal of write address code translator 11 with data input latch device 13 respectively, the quantity of described static ram cell 21 is more than or equal to 2, each static ram cell 21 in described this second level circuit structure 2 is to have added a transmission gate switch 213 between two phase inverters that latch mutually 211 and 212, when write control signal is effective, switch disconnects, the data input is transparent with respect to output, when write control signal is invalid, switch conduction, storer is stored signal, what export can only be the data of current storage, irrelevant with input signal, the grid of this transmission gate switch 213 is connected with the grid of transistor 214, and the source electrode of this transistor 214 or drain electrode are connected (consulting Fig. 3) with the input end of phase inverter 211;

The concrete storing process of static ram cell 21 is as follows:

1. working as input clock is logic low, when gated clock is logic high, write address and write data can not change, therefore the write control signal of selected static ram cell 21 is continuously logic high, and the data that sampled by data input latch device 13 are written in this static ram cell 21 at this moment.

2. working as the storer input clock is logic high, when gated clock is logic low, write address and data input may change during this period, but because 13 pairs of data before of data input latch device latch, so the data in the static ram cell 21 of old write address correspondence can not be modified, and the invalid data of the static ram cell 21 of the new write address correspondence that changes during this period can not be stored, so when write address changes, corresponding static ram cell 21 in the old write address, just successful storage the data that write of last one-period.

This tertiary circuit structure 3 comprises MUX 31, and its input end links to each other with each output terminal of a plurality of static ram cells 21; Read address decoder 32, its output terminal is connected with the input end of MUX 31 respectively; Data output latch 33, its input end is connected with the output terminal of MUX 31, and be subjected to the control of clock gate logic 12, described several number all links to each other with described clock gated logic circuit 12 according to output latch 33, the input clock of each data output latch is the input clock of described on-chip memory, and the output of each data output latch is the final sense data of described on-chip memory.

Described MUX 31 is identical with the quantity of data output latch 33, and its quantity is less than the quantity of static ram cell 21.

Tertiary circuit structure 3 functions in the described storer are to finish reading of storage data, and its detailed process is as follows:

Read the address and be input to and read address decoder 32 when n (n＞=1) is individual, produce n gating control signal, the static ram cell 21 of reading the place, address is given the input end of data output latch 33 by MUX 31 output datas of gating control signal control, after the input clock rising edge, active data is read from data output latch 33.

The temporal characteristics of tertiary circuit structure 3 is as follows: reading the gating control signal that address decoding obtains can set up during the logic low of a last clock period, also can be after the current period rising edge clock, foundation also keeps stable, as long as satisfy the maintenance Time Created of data output latch, if but the gating control signal between the input clock low period, sets up and may cause valid reading bigger than normal according to the delay of exporting.

Described on-chip memory comprises following input/output port: an input clock, one or more write addresses, the data input of one 1 bit, write enable signal for 1, read the address for n, and n 1 bit read data, wherein n is the quantity of data output latch 33.

See also shown in Figure 2ly, be first embodiment of the present invention:

Be that a data port is 1 bit, memory capacity is that one of 4 bits are read one and write dual-ported memory, it is identical with structural representation shown in Figure 1 that it forms structure, wherein clock gated logic circuit 12 is logical AND gates, data input latch device 13 is all positive latch with data output latch 33, MUX 31 is by four NMOS transmission gate transistor 311,312,313,314 and level recover logical circuit 315 and constitute 4 NMOS transmission gate transistors 311,312,313,314 grid is subjected to gating control signal RD0 respectively, RD1, RD2, RD3 controls.

The port information of storer such as following table one:

The port title	Port direction	The port bit wide	The port explanation
				clk	Input
	1	The storer input clock signal
			wren	Input
	1	The memory write enable signal
			wraddr	Input	2	The memory write address
rdaddr	Input	2					The memory read address
			Din	Input	1	The memory write data
Dout	Output
			1	The memory read data

WL0, WL1, WL2, WL3, RDO, RD1, RD2, RD3 among Fig. 2,-GCLK, DQ are M signal, wherein WL0, WL1, WL2, WL3 are the signal after the write address decoding, DQ is the latching of data input latch device 13 and the output of sampling,-GCLK is a gated clock,-GCLK signal makes data input latch device 13 to sample when the clk low level, physical relationship sees Table two, and the relation between WL0, WL1, WL2, WL3 and wren, the wraddr sees Table three, and the relation between RD0, RD1, RD2, RD3 and the rdaddr sees Table four.

In the following table and literal in data 0 correspond to logic low " 0 ", data 1 are corresponding to logic high " 1 ".

Table two is as follows:

clk	wren	-GCLK
			0	0	0
0	1	1
			1	0	0
1	1	0

Table three is as follows:

wren	wraddr	WL0	WL1	WL2	WL3
						0	0	0	0	0	0

0	1	0	0	0	0
						0	2	0	0	0	0
0	3	0	0	0	0
						1	0	1	0	0	0
1	1	0	1	0	0
						1	2	0	0	1	0
1	3	0	0	0	1

Table four is as follows:

rdaddr	RD0	RD1	RD2	RD3
						0	1	0	0	0
1	0	1	0	0
					2	0	0	1	0
3	0	0	0	1

The concrete read-write sequence of the described storer of first example following (consulting Fig. 4): clock period 0:wren=0, wraddr=1, raddr=2, WL0=0, WL1=0, WL2=0, the first order of WL3=0 reservoir and the second level is no longer occurrence logic change all, and what the 3rd bit memory cell was deposited is 1.Clock period 1:wren=1, wraddr=0, rdaddr=0, Dout was output as 1 (storing value of the 3rd bit memory cell) after this moment, WLO became 1. rising edges, between later half cycle low period, Dout keeps initial value, and input end DQ=Din=0, and Din is write in first storage unit of WL0 correspondence.

Clock period 2:wren=1, wraddr=2, this moment, WL0 became 0, WL2 becomes 1, rdaddr=2, and Dout is output as 0 (storing value of the 1st bit memory cell) behind the rising edge clock, between later half cycle low period, Dout keeps initial value, and input end DQ=Din=1, and Din is write in the 3rd bit memory cell of WL2 correspondence.Clock period 3:wren=0, wraddr is constant, and rdaddr is constant, and the first order of reservoir and the second level is no longer occurrence logic change all, and output data is Dout=1 (storing value of the 3rd bit memory cell).

See also shown in Figure 5ly, be second embodiment of the present invention:

This embodiment is bit wide 1 bit, and memory capacity is that 2 of 16 bits are read 1 and write the multiport memory (see figure 5), compares with first embodiment, and what this embodiment was different is:

1. the decoded mode of write address is the half decode mode, high two bit address wraddrH[1:0] and low two bit address wraddrL[1:0] respectively decoding produce 4 address decode signal wrh[0], wrh[1], wrh[2], wrh[3], wrl[0], wrl[1], wrl[2], wrl[3] each signal all controls 4 storage unit, these 8 signals combination in twos each other come the required storage unit of independent gating, (the half decode mode is compared the fully decoded mode can save a large amount of transistors).

In second example because two read ports are arranged, so need two groups of MUX 31, these two groups of MUX 31, the common data-out port that connects 16 static ram cells 21, read address rdaddr1[3:0 but receive respectively] and rdaddr2[3:0] the gating control signal, OPADD rdaddr1[3:0 respectively at last] and rdaddr2[3:0] institute's deposit data.For write port in second example, or any one read port, its temporal aspect and first embodiment are identical.

Seeing also shown in Figure 6ly, is the structured flowchart that the present invention acts on the chip multi-core system:

It comprises 61,62,63,64 and communicating between multi-kernel controllers 65 of 4 processor cores, each processor core 61,62,63,64 all interconnects with communicating between multi-kernel controller 65, and exist input and output mutual, comprise an arithmetic logic unit (1bitALU) 611,621,631,641 and storer of the present invention 612,622,632,642 in the processor core 61,62,63,64.

This system is owing to added multiport memory of the present invention, and arithmetic logic unit 611,621,631,641 in each processor core 61,62,63,64 and communicating between multi-kernel controller 65 can carry out read-write operation to corresponding memory 612,622,632,642 simultaneously.Those skilled in the art's generic representation represented to belong in the English of part functional part among Fig. 6.

The above; only be the embodiment among the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the conversion that can expect easily or replacement all should be encompassed in of the present invention comprising within the scope.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.

Claims

1. the on-chip memory of multiport read-write comprises:

2. the on-chip memory of multiport read-write as claimed in claim 1, the quantity of wherein said static ram cell is more than or equal to 2.

3. the on-chip memory of multiport as claimed in claim 1 read-write, wherein said MUX is identical with the quantity of data output latch, and its quantity is more than or equal to 1 and less than the quantity of static ram cell.

4. the on-chip memory of multiport read-write as claimed in claim 1, each static ram cell in wherein said this second level circuit structure is to have added a transmission gate switch between two phase inverters that latch mutually, when write control signal is effective, switch disconnects, the data input is transparent with respect to output, when write control signal is invalid, switch conduction, storer is stored signal, what export can only be the data of current storage, irrelevant with input signal, the grid of this transmission gate switch is connected with transistorized grid, and this transistorized source electrode or drain electrode are connected with the input end of phase inverter.

5. the on-chip memory of multiport read-write as claimed in claim 1, wherein said data input latch utensil has data input pin, and it is input as 1 bit write data, and outputs to each input end of a plurality of static ram cells.

6. by the on-chip memory of the described multiport of claim 1 read-write, wherein said on-chip memory comprises following input/output port: an input clock, one or more write addresses, the data input of one 1 bit, write enable signal for 1, read the address for n, and n 1 bit read data, wherein n is the quantity of data output latch.

7. by the on-chip memory of the described multiport of claim 1 read-write, wherein said a plurality of data output latch all links to each other with described clock gated logic circuit, the input clock of each data output latch is the input clock of the on-chip memory of described multiport read-write, and the output of each data output latch is the final sense data of the on-chip memory of described multiport read-write.