CN103218311A - Virtual FIFO (First In, First Out) device realized by adopting SRAM (static random-access memory) - Google Patents
Virtual FIFO (First In, First Out) device realized by adopting SRAM (static random-access memory) Download PDFInfo
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Abstract
The invention discloses a virtual FIFO (First In, First Out) device realized by adopting an SRAM (static random-access memory). The virtual FIFO device mainly comprises a data uplink/downlink second-level FIFO module, a state machine module and an external first-level FIFO module. The data uplink/downlink second-level FIFO module comprises a data uplink second-level FIFO module and a data downlink second-level FIFO module, each of which is formed by memory blocks in an FPGA (Field Programmable Gate Array) and is used for primary transmission of data. The state machine module is used for controlling the transmission state of a data stream by using the FPGA. The external first-level FIFO module is realized by the SRAM and is used for realizing large-capacity FIFO data caching. Since virtual FIFO is realized by adopting the SRAM, compared with special off-chip FIFO devices and FIFO devices in the FPGA, the virtual FIFO device realized by adopting the SRAM has the advantages that the hardware cost is greatly reduced and the system reliability is improved on the premise that the high-speed and large-capacity data caching is guaranteed.
Description
Technical field
The present invention relates to the development and Design field of pci bus technology and FPGA, particularly utilize SRAM to make up the method and system of external cache for fpga chip.
Background technology
In the transmission data, often to use FIFO, this is a kind of metadata cache mode of first-in first-out.Its feature is that order writes data, calls over data then, and data address adds 1 automatically by inner read/write address pointer and finishes.This metadata cache mode is the AD data acquisition through being usually used in the data transmission between two kinds of clock zones or the two kinds of hardware systems such as an end, and the other end is the situation of pci bus.
The outer FIFO of sheet is the early stage a kind of FIFO form that occurs, this FIFO can finish the function of the buffer memory of first-in first-out preferably, but costs an arm and a leg, on the other hand, carry out data transmission between two chips and can make system complexity improve, thereby also reduced reliability.Enter SOC after the epoch in electronic technology, FIFO has also just arisen at the historic moment in the sheet, such as the block storer of FPGA inside.This FIFO can overcome the above-mentioned shortcoming of the outer FIFO of sheet, but its shortcoming is also arranged, and is exactly that capacity is less, and the FIFO degree of depth generally can only reach several K to tens K, can not satisfy the demand of data volume when big.So will seek a kind of new FIFO mode, can guarantee the metadata cache of high-speed high capacity, it is too high to be unlikely to cost again, and can guarantee reliability.
Generally speaking, carry out data transmission by pci bus between equipment and the computing machine.Host computer (main frame) sends to data on the subcard by pci bus, perhaps by pci bus reading of data from the subcard.The general dma mode that adopts transmits block data.For the DMA transmission mode, when each data block transmitted size was big, data transmission rate was higher.And,,, then need the frequent starting dma controller if each data quantity transmitted is less for the bus transfer pattern that requires very high data transmission rate.Increased the burden of CPU like this, on real-time, cannot say for sure to demonstrate,prove.For example requiring bus transfer rate is 60MB/S, and the bigger data block size of each transmission is 2MB, and then per second need start dma controller 30 times.If the bigger data block of each transmission just need have bigger buffer memory on subcard.Use FPGA to realize interface with pci bus on the general pci bus subcard.The block memory span of FPGA inside is less, is not suitable for making up bigger buffer memory.Therefore need be at FPGA build up outside buffer memory, thus the notion of virtual fifo has been proposed.
The FIFO of existing scheme or the outer FIFO of employing sheet or employing FPGA internal build, the shortcoming that faces is numerous, and major defect is as follows:
(1) the outer FIFO device of high capacity sheet costs an arm and a leg less in actual applications appearance
(2) the outer FIFO reliability of sheet is relatively poor
(3) the FIFO capacity of FPGA internal build is less, can't satisfy the requirement of pci bus transmission
(4) set pattern is old, is easy to imitation.The implementation method of scheme is easily understood, and is very easily caused the disorderly competition in market by people's imitation.
(5) the present invention is exactly in order to overcome these limitation of old scheme, to utilize SRAM to make up virtual fifo innovatively outside FPGA; So both satisfy the requirement of high-capacity and high-speed rate FIFO, improved the reliability of system again, reduced cost of developing simultaneously.
Summary of the invention
The present invention is exactly in order to overcome these limitation of old scheme, to utilize SRAM to make up virtual fifo innovatively outside FPGA; So both satisfy the requirement of high-capacity and high-speed rate FIFO, improved the reliability of system again, reduced cost of developing simultaneously.
Particularly, the present invention proposes a kind of device that adopts static store to realize virtual fifo, mainly comprise: on the data/descending secondary fifo module, state machine module and outer departmental level fifo module, wherein
On the described data/and descending secondary fifo module, data uplink secondary fifo module and data downstream secondary fifo module, it constitutes by the memory block by FPGA inside, is used for data are carried out elementary transmission;
Described state machine module is used to the transmission state that utilizes the FPGA control data to flow;
Described outer departmental level fifo module is realized by static store, is used to realize jumbo data fifo buffer memory.
According to a further aspect of the present invention, wherein data uplink secondary fifo module and data downstream secondary fifo module are the FIFO of two 32 1K degree of depth, are made of the memory block of FPGA inside.
According to a further aspect of the present invention, wherein utilize the transmission state of FPGA control data stream to comprise that further receiving the outside transmits the data of coming in, pass to outer departmental level FIFO, receive the data that outer departmental level FIFO passes into again, then data are sent out.
According to a further aspect of the present invention, in the wherein whole virtual fifo process data stream on data/descending secondary fifo module and outside transmission between the departmental level fifo module control by described state machine module.
According to a further aspect of the present invention, the mode of operation of wherein said state machine module comprises following three kinds: idle condition, write state is read state.
According to a further aspect of the present invention, two address registers are set in the wherein said state machine module: writing address register and read address register, initial value is 0, is used to describe the read/write address of current virtual fifo.
The present invention adopts SRAM to realize virtual fifo, and the inner FIFO of FIFO device and FPGA when guaranteeing the high-speed high capacity metadata cache, has greatly reduced hardware cost, and improved the reliability of system outside special sheet.
Description of drawings
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments:
Accompanying drawing 1 is depicted as employing SRAM(static store proposed by the invention) the device synoptic diagram of the virtual fifo realized;
Accompanying drawing 2 is depicted as on the data proposed by the invention/descending secondary fifo module structural representation;
Accompanying drawing 3 is depicted as the state machine diagram of virtual fifo proposed by the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The present invention uses jumbo high-speed asynchronous SRAM, and the sequential of Asynchronous SRAM is simple, and capacity generally can reach 1MB or more, and bus frequency also can reach 100MHz, and synchronous relatively SRAM of price and high capacity FIFO device are also relatively more cheap.The design has just adopted 2 jumbo high-speed asynchronous sram chips.Every chip capacity is 2MB, adds up to 4MB.
For the buffer memory of data transmission, be configured to the FIFO(first in first out) structure, use comparatively simple.The design utilizes FPGA to realize the controller of SRAM, thereby has made up 32 of bit wides, and the degree of depth is the virtual fifo of 1M to the maximum.The frequency of operation of virtual fifo is 50MHz, and bandwidth is 200MB/s.The SRAM that considers virtual fifo will handle input and output, so effective transmission bandwidth of virtual fifo is that 100MB/s(is that the input and output bandwidth is 100MB/S).Such transmission bandwidth can satisfy the transmission demand of pci bus.
(1) formation of virtual fifo device
The construction system block diagram of virtual fifo as shown in Figure 1, chief component is on the data/descending secondary fifo module 101, state machine module 102 and outer departmental level fifo module 103, wherein:
On the data/descending secondary fifo module 101, the FIFO that comprises two 32 1K degree of depth, they are made of the memory block of FPGA inside for our called after data uplink secondary fifo module and data downstream secondary fifo module (abbreviating FIFO_A and FIFO_B in the explanation of back respectively as).As shown in Figure 2.Their effect is that data are carried out elementary transmission, promptly receives the outside data of coming in that transmit, and passes to outer departmental level FIFO, receives the data that outer departmental level FIFO passes into again, then data is sent out.
Outer departmental level fifo module 103 is realized by SRAM, is used to realize jumbo data fifo buffer memory, be to the expansion of FPGA inside FIFO on hardware, also be the major part on hardware of whole virtual fifo, utilize it, we have been extended to 1M to the FIFO degree of depth from several K.
Wherein, the mode of operation of described state machine module 102 has 3 kinds: idle condition 301, write state 302 is read state 303, as shown in Figure 3.
(2) implementation procedure of virtual fifo and state machine are described
The idle condition 301 of state machine module 102, write state 302 is read three kinds of mode of operations of state 303 and is controlled automatically by the bus arbitration module.The length that at every turn reads the bursty data piece is designated as burst_length=10 (16 system).If when writing data number VFIFO_COUNT_REG among the SRAM and be 512K, just think full.Two address registers are set in state machine module 102: writing address register writeAddrReg, read address register readAddrReg, initial value is 0.These two address registers are used to describe the read/write address of current virtual fifo.
In order to further specify the device of the virtual fifo that the present invention proposes, the workflow of described virtual fifo device is as follows:
1) power on and serve after, state machine module enters idle condition.VFIFO_COUNT_REG is 0.
2) in idle condition, the state of state machine module monitoring FIFO_A and FIFO_B.If the data number among the FIFO_A is not less than burst_length, and VFIFO less than, just enter the VFIFO data and write state; Otherwise the judgment data output enable, and the data among the FIFO_B just enter the VFIFO read states less than half-full.
3) the VFIFO data are write state: read burst_length data continuously from FIFO_A, be written among the SRAM.Judge then whether FIFO_B needs supplementary data (basis for estimation: data output enable OUTPUT_EN, and the data among the FIFO_B are less than half-full).If desired, just enter the VFIFO read states.After writing data, the data of VFIFO_COUNT_REG increase burst_length.
4) VFIFO read states: from SRAM, read 8 data continuously, be written among the FIFO_B.Get back to idle condition then.
5) after the sense data, the data of VFIFO_COUNT_REG reduce burst_length.
5.4 the device mode of operation of virtual fifo:
Write the data of 1M byte earlier;
1) enable data output;
2) the data length VFIFO_COUNT_REG among the inquiry VFIFO.If less than 1M, just write the 1M data once more.Repeat 3 process.
The present invention adopts SRAM to realize virtual fifo, and the inner FIFO of FIFO device and FPGA when guaranteeing the high-speed high capacity metadata cache, has greatly reduced hardware cost, and improved the reliability of system outside special sheet.The structure that the present invention has creatively adopted data to enter structure data downstream secondary FIFO in the FPGA by the data uplink secondary FIFO of structure in the FPGA again through the virtual fifo that is made of SRAM, this structure is the expansion to the success of FIFO in the sheet.By FPGA the mode of bursty data piece has been adopted in the control of data stream, guaranteed that data can intactly not carry out high-speed transfer with losing.Through actual verification, the virtual fifo that adopts this mode to realize can accurately not have at a high speed in the data communication of pci bus and hardware really finishes the work with losing.
This employing SRAM realizes with high content of technology, the strong security of virtual fifo, is not easy imitated and applies mechanically; For the communication data collection of high density, big data quantity and the technic relization scheme of handling in comparing the 3rd have bigger advantage now.
In sum, though the present invention with the preferred embodiment disclosure as above, yet it is not in order to limit the present invention.The general technical staff of the technical field of the invention without departing from the spirit and scope of the present invention, can do various changes and modification.Therefore, protection scope of the present invention is as the criterion when looking appended the scope that claim defined.
Claims (6)
1. device that adopts static store to realize virtual fifo mainly comprises: on the data/and descending secondary fifo module, state machine module and outer departmental level fifo module, wherein
On the described data/and descending secondary fifo module, data uplink secondary fifo module and data downstream secondary fifo module, it constitutes by the memory block by FPGA inside, is used for data are carried out elementary transmission;
Described state machine module is used to the transmission state that utilizes the FPGA control data to flow;
Described outer departmental level fifo module is realized by static store, is used to realize jumbo data fifo buffer memory.
2. the system as claimed in claim 1, wherein data uplink secondary fifo module and data downstream secondary fifo module are the FIFO of two 32 1K degree of depth, are made of the memory block of FPGA inside.
3. the system as claimed in claim 1 wherein utilizes the transmission state of FPGA control data stream to comprise that further receiving the outside transmits the data of coming in, and passes to outer departmental level FIFO, receives the data that outer departmental level FIFO passes into again, then data is sent out.
4. the system as claimed in claim 1, in the wherein whole virtual fifo process data stream on data/descending secondary fifo module and outside transmission between the departmental level fifo module control by described state machine module.
5. the system as claimed in claim 1, the mode of operation of wherein said state machine module comprises following three kinds: idle condition, write state is read state.
6. the system as claimed in claim 1 is provided with two address registers in the wherein said state machine module: writing address register and read address register, initial value is 0, is used to describe the read/write address of current virtual fifo.
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Application publication date: 20130724 |