CN103208487B - Method and apparatus for relatively thin stack package structure - Google Patents

Method and apparatus for relatively thin stack package structure Download PDF

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Publication number
CN103208487B
CN103208487B CN201210546170.0A CN201210546170A CN103208487B CN 103208487 B CN103208487 B CN 103208487B CN 201210546170 A CN201210546170 A CN 201210546170A CN 103208487 B CN103208487 B CN 103208487B
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substrate
package
pop
packaging part
connector
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CN201210546170.0A
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CN103208487A (en
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吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

Method and apparatus for relatively thin stack package (" PoP ") structure.A kind of structure includes: the first ic package, and this first ic package includes at least one IC-components installed on the first substrate and the multiple stacked package connectors extended from bottom surface；And second ic package, this second ic package includes at least another IC-components being arranged on second substrate and is positioned on upper surface the multiple joint dishes being connected to multiple stacked package connector, and the multiple joint outer parts extended from bottom surface；Wherein, at least second substrate is formed by laminated multi-layer dielectric and conductor.In another embodiment, the bottom surface of first substrate forms chamber, and a part for another integrated circuit is extended partially in chamber.Disclose the method for manufacturing PoP structure.

Description

Method and apparatus for relatively thin stack package structure
Technical field
The present invention relates to semiconductor manufacturing, more specifically, relate to the side of stack package structure Method and device.
Background technology
Along with the device using IC manufacturing constantly reduces, less to for IC-components The demand of packaging part is continuously increased.A kind of being being increasingly used to saves the space on system circuit board And the method for the plate area used by Jian little ing is for being referred to as " stack package (Package on Package) provide " or in the combination of " PoP " device, vertically arranged package structure two or More integrated circuits.PoP structure reduces integrated electricity by being combined into single package structure System circuit board area needed for road, and also eliminate be pointed on circuit board may additionally make device The needs of some the connector traces being connected to each other.Through hole can be used to be connected to vertically arranged encapsulation Electrical connection is provided between device.
Such as, the device on upper packaging part during memory module can be mounted in PoP structure.Make For limiting examples, memory module can include one, two or more commodity memory device Part, such as, DDR DRAM or FLASH device.Upper base plate for packaging can be multilayer circuit board, And can by resin (such as, the weaving glass-reinforced epoxy resin of such as FR4 or BT resin), Pottery, plastics, film or other baseplate materials are formed.
The bottom surface of upper substrate can have a line or the multirow that the plane perpendicular away from head substrate extends PoP connector.These PoP connectors provide the collection in the bottom package being arranged on PoP device Become the connection of circuit, or provide when PoP device is finally arranged on system circuit board mapped (map) to the connection of system board.
Bottom package is to have the substrate of integrated circuit mounted thereto.Integrated circuit can be " should With processor " or " AP ".The upper surface of bottom package has for receiving and being electrically connected to PoP The joint dish (land) of connector or pad.Such as, if PoP connector is from upper packaging part The multirow solder ball that bottom surface extends, joint dish or pad on the upper surface of bottom package would correspond to These connectors and receive these connectors.
The bottom package of PoP structure also has position external connection thereon (generally on bottom surface) Part, this joint outer part is for forming last connection between PoP structure and system circuit board.Bottom Packaging part can be BGA (" BGA ") type packaging part, and has and be arranged on bottom surface The solder ball of array.Therefore, PoP device has the PoP between head substrate and bottom substrate Connector, and the external connection that the bottom substrate on the pad being arranged on system circuit board extends Part terminal.
But, along with to higher performance and the increase of the demand of higher frequency operated device, tie at PoP The wiring used in structure becomes the factor of significantly limiting.For the device from PoP structure to system board with And the signal path of the device acquisition signal from system board to POP structure is the longest, this signal path Board trace, solder ball, solder projection or C4 connector and closing line can be included.These paths Produce IR pressure drop and cause system slack-off.And, PoP device use in portable use increases Add the demand to thinner packaging part.
Summary of the invention
On the one hand, the invention provides a kind of semiconductor device structure, including: the first integrated circuit envelope Piece installing, including at least one IC-components installed on the first substrate, and has from described Multiple stacked package connectors that the bottom surface of first substrate extends；And second ic package, Including at least another IC-components being arranged on second substrate, including being positioned at described second base Be connected to multiple joint dishes of the plurality of stacked package connector on the upper surface of plate, and include from Multiple joint outer parts that second bottom surface of described second ic package extends；Wherein, at least Described second substrate includes multiple dielectric layers and the conductor being stacked and being not inserted into core.
In described semiconductor device structure, the plurality of stacked package connector is solder.
In described semiconductor device structure, the plurality of joint outer part is solder.
In described semiconductor device structure, described first substrate includes being stacked and not inserting Enter multiple dielectric layers and the conductor of core.
In described semiconductor device structure, described first substrate includes the first table being positioned at core material More than first dielectric layer on face, and more than second dielectric on the second surface of described core material Layer.
In described semiconductor device structure, described first substrate further includes at described first base The chamber formed in the core of the described bottom surface of plate.
In described semiconductor device structure, another is integrated for described second packaging part described at least Circuit devcie is extended partially in the described core of the described bottom surface of described first surface formation Described chamber in.
In described semiconductor device structure, described at least another IC-components is embedded in institute State in second substrate.
In described semiconductor device structure, described at least another IC-components uses trace Upper plate connector is installed to described second substrate.
In described semiconductor device structure, at least one IC-components described is memory.
In described semiconductor device structure, described at least another IC-components is micro-process Device.
On the other hand, the invention provides a kind of semiconductor device structure, including: the first integrated circuit Packaging part, including at least one IC-components installed on the first substrate, and has from institute State multiple stacked package connectors that the bottom surface of first substrate extends, and formation on described bottom surface And extend to the chamber in described first substrate, described stacked package connector cloth spaced apart with described chamber Put；And second ic package, including be arranged on second substrate at least another is integrated Circuit devcie, including being connected to the plurality of stacked package on the upper surface being positioned at described second substrate Multiple joint dishes of connector, and farther include the bottom surface from described second ic package The multiple joint outer parts extended；Wherein, at least in described at least another IC-components Extend partially in the chamber on the described bottom surface of described first substrate.
In described semiconductor device structure, described second substrate includes being stacked and not inserting Enter multiple dielectric layers and the conductor of core.
In described semiconductor device structure, described first substrate includes the first table being positioned at core material More than first dielectric layer on face, and it is positioned at more than second on the second surface of described core material Jie Electric layer.
In described semiconductor device structure, described second substrate includes be positioned at the second core material The 3rd many dielectric layers on one surface, and be positioned on the second surface of described second core material More than four dielectric layer.
Another aspect, the invention provides a kind of method, including: the first ic package is provided, Described first ic package includes the one or more collection on the upper surface that is positioned on first substrate Become circuit, and the multiple stacked package connectors extended from the lower surface of described first substrate are provided； Second ic package is provided, including: provide second substrate, at the upper table of described second substrate Having other integrated circuits one or more on face, described second substrate includes being arranged in described second base For receiving multiple joint dishes of the plurality of stacked package connector on the upper surface of plate, and enter one Step includes: provide the multiple joint outer parts extended from the bottom surface of described second substrate；And by inciting somebody to action The described stacked package connector of described first ic package is bonded on described second substrate The plurality of joint dish, is installed to described first ic package described in described second substrate Upper surface；Wherein, it is provided that described second substrate includes: provide and be stacked with and to be not inserted into core many Individual dielectric layer and conductor.
In the described method, it is provided that described second substrate farther includes: provide and there is covering one First dielectric layer of the conductor on surface；Ground floor through hole is formed in described first dielectric layer；Described Ground floor through hole is formed ground floor conductive material；Described conductive material in described ground floor through hole Top forms ground floor conductive trace；And it is provided above the second dielectric layer at described conductive trace.
Described method farther includes: form second layer through hole in described second dielectric layer；Institute State formation conductive material in the described second layer through hole in the second dielectric layer；In described second layer through hole Described conductive material above formed second layer conductive trace；And patterning covers one surface Described conductor, for accommodate joint outer part.
Described method farther includes: be installed to by the one or more integrated circuit flip chip The described second layer conductive trace of described second substrate.
Described method farther includes: the one or more integrated circuit is embedded into described second In substrate.
Accompanying drawing explanation
In order to be more fully understood from the present invention and advantage thereof, the following description carried out presently in connection with accompanying drawing As reference, wherein:
Fig. 1 shows a part for the printed circuit board (PCB) being provided with PoP device on it with 3-D view；
Fig. 2 shows embodiment PoP structure with viewgraph of cross-section；
Fig. 3 shows another embodiment PoP structure with viewgraph of cross-section；
Fig. 4 shows alternative embodiment PoP structure with viewgraph of cross-section；
Fig. 5 shows another alternative embodiment PoP structure with viewgraph of cross-section；
Fig. 6 shows another alternative embodiment PoP structure with viewgraph of cross-section；
Fig. 7 shows the viewgraph of cross-section of the embodiment of Fig. 2 and shows the signal road of this embodiment Footpath；
Fig. 8 shows another embodiment PoP structure with viewgraph of cross-section；
Fig. 9 shows the intervening process steps for forming embodiment substrate with viewgraph of cross-section；
Figure 10 shows the embodiment substrate of Fig. 9 after other processing with viewgraph of cross-section；
Figure 11 shows the embodiment of Figure 10 after other processing with viewgraph of cross-section；
Figure 12 shows the embodiment of Figure 11 after other processing with viewgraph of cross-section；
Figure 13 shows the embodiment of Figure 12 after other processing with another viewgraph of cross-section；
Figure 14 shows embodiment PoP structure with another viewgraph of cross-section；
Figure 15 shows embodiment of the method with flow chart；And
Figure 16 shows alternative embodiment with flow chart.
Accompanying drawing, schematic diagram and chart are all illustrative and not restrictive, but the reality of the present invention Execute the example of example, simplified for illustration purposes, and be not drawn to scale.
Detailed description of the invention
Example discussed in detail below and the manufacture of illustrative embodiment and use.It should be appreciated, however, that this Invention provides the applicable inventive concept that many can realize in various specific environments.The tool discussed Body embodiment only manufactures and uses the illustrative concrete mode of design disclosed in the present application, rather than Limit the scope of the present invention, and without in limiting scope of the following claims.
Embodiments herein (will be described in detail now the example) provides the thickness for having reduction The new method of the PoP structure of degree and shorter signal path length and device.Embodiment PoP structure Shorter wiring distance is advantageous particularly in forming the packaging part being used for high frequency or high performance device, but, Advantageous embodiment uses and is not limited to these application.Use embodiment obtain thinner PoP structure for The total form factor providing thinner is favourable, for such as smart mobile phone, tablet PC, electronics Reader, PDA, portable video and music player, camera, hand-held web browser or regard Frequently receiver etc. are hand-held and for portable set, day by day increase the demand of thinner total form factor.
Fig. 1 shows four/part of conventional PoP structure 13, conventional PoP with 3-D view Structure 13 includes: as BGA (" the BGA ") packaging part 15 of bottom package；And The upper packaging part 17 above BGA package part being arranged in PoP structure.Upper encapsulation from Fig. 1 The joint outer part that the bottom surface of part 17 extends and the joint dish on the upper surface of BGA package part 15 or weldering Dish is connected.
Embodiment described in this application has the bottom extending to PoP structure from the bottom of upper packaging part The connector of the joint dish on the upper surface of packaging part.In certain embodiments, these connectors are permissible Formed as solder ball.But, embodiment and the various application to embodiment are not limited to this.Copper connects Part such as copper post, pillar or stud, controlled collapse chip connection part (" C4 "), copper or solder are convex Block and other conductive material posts all can substitute in accompanying drawing as the solder shown in example connector Ball, or be used together as the solder ball shown in example connector in accompanying drawing.And, make herein Term " solder " include leaded and lead-free solder.Solder containing pb (such as Pb/Sn composition) with And lead-free solder (including but not limited to such as embodiment SnAgCu (" SAC ") composition) is at term In the range of " solder ", it also includes other solder compositions, such as eutectic.Can use various Plating and coating improve solderability, reduce oxidation, improve cohesive, improve reflux technique or change Enter other characteristics of connector.All these changes are considered as the optional reality of embodiments discussed herein Execute example, and these alternative embodiments are the most all within the purview of the appended claims.
In FIG, system board 21 is installed PoP structure 13.System board 21 can be such as to print Printed circuit board.Ball connector can be used PoP structure to be installed, to be connected to be in thermal reflux Joint dish on system plate 21.In reflux technique, first with the system formed corresponding to BGA ball The form of the joint dish alignment on plate 21 places BGA ball, mobile PoP structure so that BGA ball with On system board 21 joint dish contact, and use heat treatment so that BGA ball fusing and backflow and Mechanically engage with circuit board, complete PoP structure with circuit board electrically and mechanically.Can make With sticker to increase mechanical strength further, and underfill can be used to provide right The Stress Release of the connector between PoP structure 13 and system board 21.
When the input of device and the quantity of output connector increase, these devices in conventional PoP structure Using of part forms thicker structure.When PoP structure becomes thicker, the device on upper packaging part The distance in path to system board adds.Signal path can include bond pad, closing line, on Trace, the through hole through upper packaging part, the solder ball to lower packaging part or copper post on packaging part connect Part, lead to the solder projection of the integrated circuit on lower packaging part and pad, to another of system circuit board Hole and another solder ball.This path can have and caused by the current-resistance (" IR ") in path Substantially voltage drop.And, packaging part height wherein needs the thinnest hand of relatively thin packaging part in design Hold and become a problem in portable set.Thickness such as the typical PoP structure in Fig. 1 can be big In 1.2 millimeters.This thickness may be the biggest for the application of some thin device.
Fig. 2 shows the first embodiment of the PoP structure 30 of improvement with viewgraph of cross-section.At Fig. 2 In, it is provided that there is the upper packaging part 27 of substrate 29.This substrate can be weaving glass-reinforced oxygen tree Fat " core ".Other baseplate materials can be used, include but not limited to such as BT resin.In printing The material (such as FR4) used in board structure of circuit may be used for substrate 29.This core has separation leads The dielectric materials layer of electric trace, to form multilayer circuit board.Such as, on the dielectric layer side illustrate for Receive the pad 36 of closing line 35.Through hole and contact may be used for vertically connecting trace, to carry Connect for wiring and mapping.For providing vertical-path can use through hole by the signal of substrate, such as, Through hole 37, its as extend through substrate 29 hole formed, then with conductive material fill this hole or Form the liner in this hole, to complete vertical connection paths.Then, the mark on the bottom surface of upper packaging part 27 Line provides for signal is connected to through hole 37 and until the above road of upper packaging part 27 further Footpath.Upper packaging part 27 all has solder mask layer 33 in upper and lower surface.In fig. 2 also Show passivation layer 39, its can for example be by duroplastic moulding materials compression molding formed for Protection through hole 37, closing line 35 and pad 36 are from the overmolded layer of moisture and thermal stress (overmolded layer).Other overmolding material, such as, resin and asphalt mixtures modified by epoxy resin can be used Fat.
As illustrative and not restrictive example, upper packaging part 27 can carry (carry) and such as deposit The commercial integrated circuits device 31 of memory device.In this embodiment, device 31 can be FLASH, SRAM or DRAM device.These illustrate as two stack chip stackings.More multitube can be installed Core, to increase the size of the memory provided, or can only use a tube core alternatively.Also Other kinds of device can be installed on substrate 29.In fig. 2 it is shown that device 31 is connected The closing line (such as 35) of the pad (such as 36) to substrate 29.But, in optional layout In, bottom memory dice can be " flip-chip ", and can use solder projection or copper Connector is bonded to the joint dish on the core of substrate 29.In certain embodiments, can conduct Element forms the memory module of some vertical stacking tube cores, uses such as though-hole connections to connect stacking Storage component part can be flip-chip peace to form the bottom die in memory module, and module Install to substrate 29.All these layouts are all regarded as the alternative embodiment of a part for embodiment, and And fall within the scope of the appended claims.
Connector 38 forms the PoP connector of the structure for Fig. 2.These connectors 38 can be Solder or other conductive materials.As shown in Figure 2, they can be solder ball, but embodiment is not Being limited to the use of solder ball, connector can be copper post, copper stud, controlled collapse chip connection part (" C4 ") or for element being connected to other connectors of following plate or device.And, The term " solder " used in this manual is not limited to any particular type, and can use and contain Lead or lead-free solder.Lead and tin (Pb/Sn) or the solder ball of Pb and other materials can be used.? In alternative embodiment, it is possible to use include the tin as limiting examples, silver and copper (" SAC ") Without lead composition.Eutectic composition may be used for forming connector.The shape of connector 38 is also not necessarily limited to " ball " shape, and can use cylinder, cylindricality, avette, turriform, square, rectangle and Other shapes.
In the embodiment of fig. 2, PoP connector 38 is embarked on journey in the peripheral disposition of substrate 29.This The core of the bottom surface being arranged in packaging part 27 leaves interval, for installing in its lower section Chip is placed in the perpendicular separation provided by connector 38, and the bottom surface of neighbouring upper packaging part 27. In this way, the thickness T2 of PoP structure 30 is reduced.As described further below, at other In embodiment, it is also possible to reduce this perpendicular separation further by other amendments multiple.
In fig. 2, it should be noted that envelope can be used in the application in addition to PoP structure 30 Piece installing.For example, it is possible to be installed on circuit board by connector 38, and storage component part 31 is permissible Apply for other.Therefore, upper packaging part 27 has in addition to for embodiments discussed herein Effectiveness.
In fig. 2, " centreless " bottom package 25 is illustrated below at upper packaging part 27.This encapsulation Part forms " BGA " part of PoP structure and carries application processor or " AP " 42.AP 42 Microprocessor can be but not limited to.Alternative embodiment for AP 42 includes special IC (" ASIC "), digital signal processor (" DSP "), radio transceiver IC or execution The use of other function elements of selected desired function.If AP 42 is processor or microprocessor, Then it can be seen that storage component part 31 can be the program storage relevant to AP 42 or the most slow Rush memory；Therefore, using of PoP structure 30 provides " system " used in the devices.Then, The system of PoP structure 30 includes some integrated circuits, but only needs the system circuit board of a part.
Coreless substrate 41 is set up bottom package 25.This packaging part has the one of upper packaging part 27 A little parts；Such as, it is shown that there is through hole and the conductive trace of contact and dielectric layer, and use weldering Connect the mask upper and lower surface with protective substrate 41.But, eliminate now at upper packaging part The substrate 29 used in 27 or " core ".As will be described further below, PoP disclosed herein Some embodiments of structure use a kind of coreless substrate for manufacturing the thickness with reduction (such as Fig. 2 In 41) new method.
The thickness reached relative to conventional PoP device, the thickness T2 of PoP structure 30 reduces.Logical Cross omission " core " reduction thickness and there is several advantage.Shorten from such as 31 and 42 device to being The path of system plate connector.Owing to each path is to be multiplied by path by by the electric current in this path The voltage drop that causes of the product (" IR ") of resistance, shorter path has " IR " fall of reduction. And, the time delay in the shorter signal stroke of shorter path implement, and it is achieved that relatively High operating frequency.And, as the result of use coreless substrate, packaging part becomes more physically Thin, this achieves thinner system packaging part.
In fig. 2 it is shown that " flip-chip " method of use is installed to the AP 42 of coreless substrate 41； That is, the bond pad on the surface of AP 42 is " flipped ", so it is " ventricumbent ", and And bond pad is connected to the trace on substrate 41 by conductive material.In this specific embodiment, its It not restrictive but the embodiment of a washability, use " trace upper plate " or " BOT " even Fitting.The bond pad of AP 42 is formed copper connector.These are connected directly to substrate 41 Copper tracing wire on upper surface, forms electrical connection.With more conventional " SOP " or " solder on pad " Method is compared, and uses BOT method to achieve more thin space (interval smaller between bond pad) Connect.SOP method needs have more interval between the pad formed on trace, to allow weldering Solder on dish refluxes together with the solder projection used on AP 42 subsequently.But, SOP implements Example may be used for being installed to AP 42 substrate 41, and applies for some, and the method is likely to be of Advantage.In all these alternative embodiments are within the scope of the appended claims.
Show the underfill 44 between the BOT connector below AP 42.Generally Capillary type underfill (" CUF ") method is used to distribute bottom filler as liquid.Resin Or the space that epoxy resin liquid flows below AP 42 and fills between connector.Can use Room temperature, UV or heat cure are to solidify this material.Bottom filler provides mechanical strength and Stress Release.
The joint dish or the pad 51 that are positioned on the upper surface of coreless substrate 41 receive PoP connector 38, It is solder ball in this embodiment.These connectors can be connected to such as be connected to device 31 The trace of AP 42 or externally connected connector 48 (being shown as solder ball in this embodiment) is used In being connected to system.Through hole can be formed in substrate 41, or can be by through hole and substrate Interior trace, form vertical company by another through hole with the trace on another surface of substrate 41 Connect.
Joint outer part 48 can be the solder connections of such as solder ball.These solder balls can be arranged Become the comb mesh pattern of row and column, and most of bottom surface of substrate 41 can be covered.Joint outer part from And form " BGA " or " BGA ", and bottom package 25 can be referred to as BGA envelope Piece installing.Bottom package 25 can also have the effectiveness in addition to PoP structure 30；That is, bottom Packaging part 25 provides the packaging part for AP 42, and such as, it may be used for tool on PoP packaging part Have in the PoP structure of storage component part, or bottom package 25 can be mounted to do not have PoP The circuit board of packaging part.
Fig. 3 illustrates alternative embodiment PoP structure 60 with cross sectional view.Multiple elements of Fig. 2 are at figure Again illustrate in 3, and for these elements, use identical reference numeral.
In figure 3, on coreless substrate 79, packaging part 67 is the most also formed.This substrate is by multiple Dielectric layer is formed, and the plurality of dielectric layer can such as use method as described below embodiment to be formed.This A little layers carry conductive traces and comprise through hole so that use through hole and the contact of conductive trace, Multilayer circuit board can be formed by coreless substrate 79.Be shown in substrate 79 upper and lower surface it Between the through hole 77 of electrical connection is provided.Coreless substrate 79 is thinner than the substrate 29 in Fig. 2；Therefore, PoP Structure 60 has the thickness T3 of the T2 less than Fig. 2, and in fig. 2, only descending packaging part is centreless. Herein, upper packaging part 67 and lower packaging part 25 are all centreless.Remaining element of Fig. 3 and Fig. 2 phase With.The interval 49 above AP 42 and below upper packaging part 67 of Fig. 3 is optional；This sky Between can be less or same as the most do not provided interval.The thickness T3 realized in this embodiment Again smaller than the thickness using conventional PoP structure to realize.
In the diagram, with another viewgraph of cross-section, further alternative PoP structure 80 is shown.Multiple Element is identical with Fig. 2, and uses identical reference numeral for identical element.
Packaging part 27 is identical with Fig. 2 in fig. 4, the upper, has device having on core substrate 29 31, closing line 35, pad 36, solder mask 33 and through hole 37.
Now lower packaging part is labeled as 85, to distinguish the difference in embodiment compared with Fig. 2.Lower envelope Piece installing 85 has coreless substrate 91, and it has the chip 42 being embedded.This AP 42 can be with The device of same type in Fig. 2, but in this embodiment, AP 42 is embedded in substrate 91； That is, the main body of AP 42 is positioned at the thickness of coreless substrate 91 rather than arranges on top of this.From And, compared with the conventional method of PoP structure, the PoP connector 38 produced can be thinner, and PoP structure 80 can have much smaller thickness T4.Illustrate that AP 42 pacifies as BOT interface unit It is contained in coreless substrate 91 in the chamber formed so that the upper surface of AP 42 and being positioned on substrate 91 The upper surface of the solder mask 93 of side can be substantially coplanar, but these parts are optional.Alternatively, AP 42 can also extending vertically above on solder mask surface.
Upper packaging part 27 in Fig. 4 is identical with the upper packaging part 27 in Fig. 2, uses identical reference Numeral and need not at this be described further.
Fig. 5 illustrates PoP constructive embodiment 100 with viewgraph of cross-section.In this embodiment, such as, Being renumberd by upper packaging part is 107, to distinguish the upper packaging part 27 of this embodiment and Fig. 2.At figure In 5, upper packaging part 107 is formed by core substrate 109, and this core substrate 109 can be glass of such as weaving Glass reinforced epoxy substrate.The bottom of substrate 109 is formed chamber 105.Should " chamber is downward " type Arrange allow to be arranged on the AP 42 on lower packaging part 25 main part extend to packaging part 107 Main body in chamber in, so thickness T5 can be the biggest relative to the thickness that conventional PoP structure has The earth reduces.Vertical area needed for AP 42 reduces the thickness also allowing for reducing PoP connector 38.
Remaining element of Fig. 5 includes for such as the lower packaging part 25 of the coreless substrate packaging part in Fig. 2, position Device 31 on upper packaging part, AP 42, joint outer part 48 are all identical with Fig. 2, and Use identical numeral.The remaining part of embodiment 100 is identical with PoP structure 30.
Fig. 6 shows another embodiment 110 with viewgraph of cross-section.In figure 6, PoP structure 110 There is packaging part in " chamber is downward " type that upper packaging part 107 is identical with Fig. 5.Lower packaging part 125 It is to have core substrate now, such as, there is the FR4 substrate of weaving glass-reinforced epoxy resin 111.Figure Therefore the remaining part of 6 and identical in Fig. 5 also use identical reference numeral.The thickness of structure 110 Degree T6 reduces such as the chamber 105 in Fig. 5 by using；But, under PoP, packaging part 125 is now Conventional " having core " substrate 111.Chamber use of packaging part 107 on mo(u)ld bottom half allows structure 110 again Thickness T6 less than the thickness that can realize in conventional PoP structure.
Fig. 7 illustrates the embodiment 60 of Fig. 2 and illustrates the example signal of device in embodiment further Path 20.Signal path 20 illustrate from device 31 by closing line 35 to upper substrate, to copper tracing wire, Path by the lower surface of through hole 77 to substrate.This signal path continues through solder ball connector 38 to the trace in the coreless substrate of lower packaging part 25, to AP 42, then by lower packaging part Through hole is to solder ball 48 and on printed circuit board (PCB).The vertical component of signal path is owing to passing through centreless The use of substrate and the BOT of embodiment install the thickness realized and reduce and shorten, and this greatly reduces letter The IR fall in number path, improves device performance.
Fig. 8 shows the embodiment PoP knot of the warping characteristic with minimizing with another viewgraph of cross-section Structure 130.Again, use the weaving glass-reinforced epoxy resin such as FR4 has core substrate 29 Packaging part 27 in formation, the lower packaging part 135 in this embodiment is also to have core substrate simultaneously, herein Numbered 136.This substrate 136 has asymmetric circuit layer system；In this example, upper surface There is two-layer dielectric and the copper tracing wire 137,139 of vertical stacking, have core substrate 136 at this simultaneously On bottom surface, it is shown that single dielectric layer 141.In testing, shown that this layout is " right relative to having Claiming " similar structures that is layered reduces packaging part warpage.Embodiment substrate 136 upper surface or under Can have other layers on surface, but in all embodiments, the upper surface of substrate 136 is all than base The lower surface of plate 136 has greater number of dielectric layer.During thermal cycle and assembling PoP structure, This asymmetric layer is arranged and is reduced other contingent substrate warps.
Remaining part shown in Fig. 8 is identical with those in preceding embodiment, and for identical Element reuses identical numeral.Such as, including device 31, closing line 35, pad 36, weldering Connect mask 33, through hole 37 and have the upper packaging part 27 of core substrate 29 identical with Fig. 2.Under Substrate 135 to Fig. 7 has core substrate 125 similar, except dielectric materials layer 137,139 and 141 Outside the most asymmetric mode is arranged.Connector 48, AP 42 and PoP connector 38 According to arranging before.
Further aspect is that of Fig. 8 illustrates from AP as solder on pad or " SOP " connector now 42 connections arriving lower packaging part 135.By these numbered 143, to distinguish them and above-mentioned other are real Execute the BOT connector 43 in example.But, in an alternative embodiment, this asymmetric laminar substrate cloth Putting can also be with the BOT connector one for AP 42 in the such as preceding embodiment in accompanying drawing above Rise and use.SOP connector 143 has the pad of band solder on substrate 135, and AP 42 has There is solder projection, make by using thermal reflux formation solder connections to be possibly realized.By AP 42 It is again to provide bottom filler 44 after flip-chip is installed to substrate 136.SOP connects to be needed even Bigger distance (bigger spacing) between fitting, and it is permissible therefore can not to realize using BOT to connect The thin space resolution ratio of the terminal on AP 42 realized.BOT connects can support e.g., less than 30 The minimum spacing distance of micron.
Presently describe the embodiment of the method for manufacturing the coreless substrate for embodiment.In fig .9, With viewgraph of cross-section, the intermediate structure 150 for forming coreless substrate is shown.Interstage in technique Shown in there is on any surface the carrier 158 of two identical assemblies, it can be glass or gold Belong to carrier.Pre impregnated material (" pre-preg ") layer 153 is Tetefol or cloth, one The conductive material layer 155 of such as layers of copper it is provided with on individual surface.Temporarily adhere to conductive layer 155 carry It is used for processing on tool 158.Laser drill or other borehole drill constructions can be used to form opening 156, with In selected location, following conductive layer 155 is exposed.These openings will become through hole.
In fig. 10, it is illustrated that the structure 150 after other procedure of processing.In order to from Fig. 9 transition To Figure 10, apply electroless copper, use photoetching to pattern electroless plating, implement plating, and real Execute other patterning to limit through hole 156 and trace 159 on the surface of pre-preg layers 153. These traces 159 are forming internal connection in the sandwich construction of coreless substrate.
Figure 11 structure 150 after processing other shown in viewgraph of cross-section.In order to be transitioned into figure In stage shown in 11, another pre-preg layers 162 is laminated to pre-preg layers 153.Implement other Smithcraft.Again, using laser to form opening in region 164, it is through hole.Implement without electricity Plating, carries out lithographic patterning and copper electroplating layer afterwards, then patterns this layers of copper with at pre-preg layers 162 Outer surface on formed trace 165.Formation joint dish is used for being connected to AP 42 by these traces 165 Integrated circuit, and this coreless substrate is used in embodiment PoP structure a kind of time be used for will The PoP connector formed on an upper.
Figure 12 illustrates in two coreless substrates of the Figure 10 after other processing with viewgraph of cross-section One.Substrate is cut or singulation forms separate unit and removes from carrier 158, no longer illustrates This carrier.Then, pattern bottom conductive layer 155, to be formed on the bottom surface of pre-preg layers 153 For the joint dish of BGA ball, such as dipping layer 162, through hole 164 and trace 165,159 Remaining element is according to previously arranging like that.
Figure 13 illustrates the coreless substrate of the Figure 12 after some other procedure of processings.At coreless substrate Upper and lower surface on all form solder mask layer 167.Then, patterning solder mask with Form opening above trace, and on ball bond dish, electroplate underbump metallization layer 169.Trace 165 It is ready for the integrated circuit AP 42 as BOT device is installed.
Figure 14 is shown with coreless substrate with viewgraph of cross-section and forms the bottom envelope as shown in Fig. 2 above The assembly completed of piece installing 25.The core of coreless substrate 41 is installed integrated circuit AP 42. Installing joint outer part 48 on bottom surface, it can be solder ball.Therefore, bottom package 25 is BGA package part, and be ready for being assembled in PoP structure 30 as shown in Figure 2.
Figure 15 illustrates the embodiment of the method for forming coreless substrate as implied above with flow chart.In step In rapid 62, it is provided that upper packaging part, on this packaging part have the IC on the upper surface being arranged on first substrate, And the PoP connector from the extension of the bottom surface of first substrate.In step 64, it is provided that lower packaging part, This lower packaging part has at least one IC being positioned on second substrate and is positioned on upper surface for connecing Receive the joint dish of PoP connector.In the step 66, on the bottom of second substrate, offer is used for connecting Joint outer part array to circuit board.In the step 68, upper packaging part and lower packaging part are stacked also It is bonded together, and second substrate is dielectric and conductor laminate layers and the centreless base being not inserted into core Plate.
Figure 16 illustrates alternative embodiment with flow chart.In step 72., it is provided that have and be positioned at IC on one substrate and the upper packaging part of the PoP connector from bottom surface extension, and at first substrate Core in provide chamber.In step 74, it is provided that lower packaging part, this lower packaging part has and is positioned at At least one IC on second substrate, has for receiving PoP connection on the upper surface of second substrate The joint dish of part.In a step 76, the bottom surface of second substrate provides joint outer part array.? In step 78, it is stacked to form PoP structure, by PoP by upper packaging part and lower packaging part The joint dish that connector is joined on the upper surface of second substrate, and the IC on second substrate extends to In chamber on the bottom surface of first substrate.When compared with conventional method, every kind of method all provides to have and subtracts Little signal length and the embodiment of thinner PoP structure.In test media, at conventional PoP Having the packaging part of thickness more than 1.2 millimeters in structure, the use of embodiment makes thickness reduce 30% And the PoP structure being reduced to less than 1 millimeter is possibly realized.
In one embodiment, semiconductor device structure includes: the first ic package, has At least one IC-components on the first substrate is installed, and there is the bottom surface from first substrate The multiple stacked package connectors extended；And second ic package, including being arranged on second At least another IC-components on substrate, has to be positioned on the upper surface of second substrate and is connected to Multiple joint dishes of multiple stacked package connectors, and there is from the second ic package Multiple joint outer parts that two bottom surfaces extend；Wherein, at least second substrate includes being stacked and not having There is multiple dielectric layers and the conductor inserting core.
In another embodiment, including above structure, plurality of stacked package connector is solder. In another embodiment, multiple joint outer parts are solders.In yet another embodiment, first substrate Including being stacked and being not inserted into multiple dielectric layers and the conductor of core.In yet another embodiment, Above semiconductor device structure includes: have more than first dielectric layer on the first surface of core material First substrate, and more than second dielectric layer being positioned on the second surface of core material.Real at another Execute in example, the chamber formed in the core of the bottom surface that first substrate further includes at first substrate. In another alternative embodiment, in above structure, at least another integrated electricity of the second packaging part Extend to road device portions in the chamber formed in the core of the bottom surface of first substrate.Another In individual embodiment, at least another IC-components is embedded in second substrate.Implement at another In example, at least another IC-components uses trace upper plate connector to be installed on second substrate.
In another embodiment, in above semiconductor device structure, at least one integrated circuit device Part is memory.In yet another embodiment, at least another IC-components is microprocessor.
In another alternative embodiment, semiconductor device structure includes: the first ic package, There is at least one IC-components installed on the first substrate, and have from first substrate Bottom surface extend multiple stacked package connectors, and on bottom surface formed and extend to the first base Chamber in plate, stacked package connector is arranged spaced apart with chamber；And second ic package, There is at least another IC-components being arranged on second substrate, including being positioned at second substrate It is connected to multiple joint dishes of multiple stacked package connector on upper surface, and farther includes from Multiple joint outer parts that the bottom surface of two ic packages extends；Wherein, at least another is integrated In the chamber on the bottom surface extending to first substrate at least partially in circuit devcie.
In another embodiment, a kind of method includes: provide the first ic package, and this is the years old One ic package includes the one or more integrated circuits being positioned on the upper surface of first substrate, And the multiple stacked package connectors extended from the lower surface of first substrate are provided；By providing the There is on the upper surface of two substrates the second substrate of other integrated circuits one or more and provide second integrated Circuit package, this second substrate includes being arranged on the upper surface of second substrate for receiving multiple heap Multiple joint dishes of folded encapsulation connector, and further provide for from the extension of the bottom surface of second substrate many Individual joint outer part；And by the stacked package connector of the first ic package is bonded to Multiple joint dishes on second substrate, are installed to the upper table of second substrate by the first ic package Face；Wherein, it is provided that second substrate includes: the multiple dielectric layers being stacked with and being not inserted into core are provided And conductor.
In another embodiment, above method is implemented, wherein, it is provided that second substrate includes: provide There is the first dielectric layer of the conductor covering a surface；Ground floor through hole is formed in the first dielectric layer； Ground floor conductive material is formed in ground floor through hole；On conductive material in ground floor through hole square Become ground floor conductive trace；And it is provided above the second dielectric layer at conductive trace.Implement at another In example, the method proceeds: by forming second layer through hole in the second dielectric layer；It is situated between second Second layer through hole in electric layer is formed conductive material；On conductive material in second layer through hole square Become second layer conductive trace；And patterning covers the conductor on a surface for receiving external connection Part.
In yet another embodiment, in above method, the method includes: by one or more integrated Circuit flip-chip is installed on the second layer conductive trace of second substrate.In yet another embodiment, The method includes being embedded in second substrate one or more integrated circuits.
Scope of the present application expection is not limited to the structure described in specification, specifically the showing of method and steps Example embodiment.Can be very according to the disclosure of example embodiment as those of ordinary skill in the art Readily appreciate that, can apply existing or Future Development for performing and corresponding reality described herein Execute the substantially the same function of example or realize technique or the step of substantially the same result, therefore this A little alternative embodiments are considered a part for embodiment.Therefore, claims are it is contemplated that its scope Inside include such process or step.

Claims (3)

1. a semiconductor device structure, including:
First ic package, including at least one integrated circuit device installed on the first substrate Part, and there is the multiple stacked package connectors extended from the bottom surface of described first substrate, Yi Ji On described bottom surface formed and extend to the chamber in described first substrate, described stacked package connector Arranged spaced apart with described chamber；And
Second ic package, including at least another integrated circuit being arranged on second substrate Device, connects including the plurality of stacked package that is connected on the upper surface being positioned at described second substrate Multiple joint dishes of part, and farther include to extend from the bottom surface of described second ic package Multiple joint outer parts；
Wherein, described at least another IC-components extends to described first at least partially In chamber on the described bottom surface of substrate, described second substrate is to have core substrate and have asymmetric electricity Road layer system, the upper surface of described second substrate has greater number than the lower surface of described second substrate Dielectric layer.
Semiconductor device structure the most according to claim 1, wherein, described first substrate includes More than first dielectric layer being positioned on the first surface of core material, and it is positioned at the second of described core material More than second dielectric layer on surface.
Semiconductor device structure the most according to claim 2, wherein, described second substrate includes The 3rd many dielectric layers being positioned on the first surface of the second core material, and it is positioned at described second core The 4th many dielectric layers on the second surface of material.
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9258952B2 (en) * 2009-10-07 2016-02-16 Rain Bird Corporation Volumetric budget based irrigation control
US10192810B2 (en) 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
US9905491B1 (en) * 2013-09-27 2018-02-27 STATS ChipPAC Pte. Ltd. Interposer substrate designs for semiconductor packages
US9379078B2 (en) * 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
US10971476B2 (en) * 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
US20150279815A1 (en) * 2014-03-28 2015-10-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Having Conductive Columns
US9355983B1 (en) * 2014-06-27 2016-05-31 Stats Chippac Ltd. Integrated circuit packaging system with interposer structure and method of manufacture thereof
KR102181013B1 (en) 2014-09-05 2020-11-19 삼성전자주식회사 Semiconductor Package
CN105789170A (en) * 2014-12-26 2016-07-20 恒劲科技股份有限公司 Packaging stack structure
KR102556052B1 (en) 2015-12-23 2023-07-14 삼성전자주식회사 System module and mobile computing device including the same
US20170213801A1 (en) * 2016-01-22 2017-07-27 Micron Technology, Inc. Method for manufacturing a package-on-package assembly
US11562955B2 (en) * 2016-04-27 2023-01-24 Intel Corporation High density multiple die structure
KR102400101B1 (en) * 2017-11-03 2022-05-19 삼성전자주식회사 POP semiconductor package and electronic system comprising the same
CN110265292B (en) * 2019-04-26 2021-07-27 芯盟科技有限公司 Three-dimensional memory and manufacturing method
US11881446B2 (en) * 2021-12-23 2024-01-23 Nanya Technology Corporation Semiconductor device with composite middle interconnectors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359659A (en) * 2007-07-31 2009-02-04 三星电子株式会社 Semiconductor package, semiconductor module and device comprising the module
CN102065638A (en) * 2009-11-17 2011-05-18 三星电机株式会社 Printed circuit board having electro-component and manufacturing method thereof

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
TWI290757B (en) * 2002-12-30 2007-12-01 Advanced Semiconductor Eng Thermal enhance MCM package and the manufacturing method thereof
JP3917946B2 (en) * 2003-03-11 2007-05-23 富士通株式会社 Multilayer semiconductor device
KR100541393B1 (en) * 2003-04-26 2006-01-10 삼성전자주식회사 Multi-chip BGA package
US20050077620A1 (en) * 2003-10-09 2005-04-14 Hsin Chung Hsien Miniaturized small memory card structure
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
JP4748648B2 (en) * 2005-03-31 2011-08-17 ルネサスエレクトロニクス株式会社 Semiconductor device
KR20070009136A (en) * 2005-07-15 2007-01-18 삼성전자주식회사 Packaging chip comprising interconnecting electrodes connected to plural wafers directly, and, fabricating method therefor
JP4551321B2 (en) * 2005-07-21 2010-09-29 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
US20080042265A1 (en) * 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US8264846B2 (en) * 2006-12-14 2012-09-11 Intel Corporation Ceramic package substrate with recessed device
US20080164605A1 (en) * 2007-01-08 2008-07-10 United Microelectronics Corp. Multi-chip package
US8685792B2 (en) * 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
US7884457B2 (en) * 2007-06-26 2011-02-08 Stats Chippac Ltd. Integrated circuit package system with dual side connection
US7566966B2 (en) * 2007-09-05 2009-07-28 Stats Chippac Ltd. Integrated circuit package-on-package system with anti-mold flash feature
JP5230997B2 (en) * 2007-11-26 2013-07-10 新光電気工業株式会社 Semiconductor device
JP5162226B2 (en) * 2007-12-12 2013-03-13 新光電気工業株式会社 Wiring substrate and semiconductor device
JP5265183B2 (en) * 2007-12-14 2013-08-14 新光電気工業株式会社 Semiconductor device
US8283209B2 (en) * 2008-06-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
KR101198411B1 (en) * 2008-11-17 2012-11-07 삼성전기주식회사 package on package substrate
US20110024898A1 (en) * 2009-07-31 2011-02-03 Ati Technologies Ulc Method of manufacturing substrates having asymmetric buildup layers
US20110100692A1 (en) * 2009-11-02 2011-05-05 Roden Topacio Circuit Board with Variable Topography Solder Interconnects
US8569887B2 (en) 2009-11-05 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8461036B2 (en) * 2009-12-22 2013-06-11 Intel Corporation Multiple surface finishes for microelectronic package substrates
US8472190B2 (en) * 2010-09-24 2013-06-25 Ati Technologies Ulc Stacked semiconductor chip device with thermal management
JP5707902B2 (en) * 2010-12-02 2015-04-30 ソニー株式会社 Semiconductor device and manufacturing method thereof
US8736065B2 (en) * 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8421245B2 (en) * 2010-12-22 2013-04-16 Intel Corporation Substrate with embedded stacked through-silicon via die
TWM406260U (en) * 2011-01-14 2011-06-21 Walton Advanced Eng Inc Semiconductor package having arch supporting at sides of interposer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359659A (en) * 2007-07-31 2009-02-04 三星电子株式会社 Semiconductor package, semiconductor module and device comprising the module
CN102065638A (en) * 2009-11-17 2011-05-18 三星电机株式会社 Printed circuit board having electro-component and manufacturing method thereof

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