CN103199889A - Field programmable gata array (FPGA) implementation method of iteration frequency domain anti-interference algorithm - Google Patents

Abstract

The invention provides a field programmable gata array (FPGA) implementation method of an iteration frequency domain anti-interference algorithm. The FPGA implementation method of the iteration frequency domain anti-interference algorithm includes the steps: conducting windowing operation after AD sample is conducted to satellite signals which are converted down into intermediate frequency; selecting appropriate threshold optimal coefficients after a fast Fourier transform (FFT) algorithm is conducted; deducing a self-adaptive iteration threshold and reducing the value of frequency points with frequency domain amplitudes larger than the threshold to threshold value; and finally conducting inverse fast Fourier transform (IFFT) and merging and outputting the results after the IFFT. By means of the FPGA implementation method of the iteration frequency domain anti-interference algorithm, an interference detection threshold is set self-adaptively, dynamic interference rejection capability is good, the phenomenon that hardware resources are occupied due to the fact that middle process data need to be stored in repeated judgments, the FPGA, namely the technology of exchanging time for resources, is fully used, and hardware resource consumption is reduced greatly.

Description

The FPGA implementation method of the anti-interference algorithm of a kind of iterative frequency-domain

Technical field

The hardware that the present invention relates to a kind of anti-interference algorithm realizes, particularly a kind of FPGA of the anti-interference algorithm of frequency domain based on the iteration thresholding realizes technology, is used for judgement and inhibition that spread spectrum radio communications system disturbs.

Background technology

Wireless communication technology plays an increasingly important role in the modern communication field, but because wireless signal is extremely faint, be subjected to various natural or artificial interference easily and can't use, therefore, need to introduce the antijamming capability that interference mitigation technology improves wireless communication system.Because artificial disturbance mostly is the arrowband and disturbs, effective Suppression of narrow band interference technology can greatly be improved the performance of communication system.

In anti-interference algorithm, the judgement of interference and inhibition are the cores of whole algorithm.Wherein the trap method is one of algorithm of using always.So-called trap method, exactly signal is transformed into frequency domain from time domain after, amplitude and the thresholding of frequency domain are made comparisons, sagging the signal frequency point amplitude greater than thresholding, finish interference inhibition work.

Document 1 " Suppression of Multiple Narrowband Interference in a Spread Spectrum Communication System[IEEE J; 2000; SAC-18 (8); 1347-1356] " discloses several thresholding computational algorithms commonly used, particularly single order is apart from threshold algorithm TH=K μ, wherein K is that thresholding is optimized coefficient, and μ is for receiving the signal average.But this method adopts fixed threshold, can not suppress effectively to disturb under dynamic interference environment.

The document 2 Suppression of narrow band interference research [electronic information countermeasure techniques; pp; 51-53; 2009] of adaptive threshold " under the low signal-to-noise ratio based on " proposes be approximately the narrowband Gaussian signal at spread-spectrum signal under the noiseless condition through behind the DFT, its envelope Rayleigh distributed, square obeys index distribution of envelope.By the derivation of exponential distribution probability density formula, propose to optimize COEFFICIENT K 〉=8 o'clock at single order thresholding in the threshold algorithm, under the condition of noiseless existence, can not cause damage to useful signal.Simultaneously, disclose a kind of segmentation interference suppression algorithm, chosen different thresholdings by the power that calculates current demand signal.But this algorithm complex height, expense is big.

Document 3 " a kind of overlapping windowing frequency domain suppresses arrowband algorithm of interference and research [modern defense technology, pp, 4-6,2010] " proposes a kind of overlapping windowing arrowband frequency domain interference and suppresses algorithm.Wherein use the conclusion of document 2, according to the characteristics of narrowband Gaussian signal envelope square obeys index distribution, choose thresholding and optimize COEFFICIENT K=5, with the first moment thresholding that obtains as the iteration thresholding, the judgement of disturbing and inhibition.But this algorithm is in the process of inhibition that disturbs, to sink greater than the signal amplitude of thresholding to zero, this kind method can cause damage to useful signal under the higher arrowband disturbed condition of jamming-to-signal ratio, can only be applicable to that single-tone or multitone disturb, and does not provide the particular hardware realization of algorithm in this document.

In sum, existing document has much been used the narrowband Gaussian model at the anti-interference algorithm of frequency domain, and choose decision threshold according to this characteristic of square obeys index distribution of its envelope, but when specific implementation, find, because of square numerical value of envelope often very big, can take very many storage resources, this is to be reluctant to see in the specific implementation, and existing document fails to provide the jamproof FPGA realization of the iterative frequency-domain of disturbing at the arrowband.

Summary of the invention

In order to overcome the deficiencies in the prior art, the present invention propose a kind of based on single order apart from the jamproof FPGA realization of the frequency domain of iteration self-adapting thresholding technology.From this angle of narrowband Gaussian signal envelope Rayleigh distributed, choose suitable thresholding and optimize coefficient, derive the adaptive iteration thresholding, the frequency of frequency domain amplitude greater than thresholding sunk to threshold value, can guarantee that useful signal can all pass through, can reduce simultaneously the storage resources of hardware greatly, finish the inhibition work of interference.

The technical solution adopted for the present invention to solve the technical problems may further comprise the steps:

(1) will carry out the AD sampling to the satellite-signal that changes to intermediate frequency down, the data that obtain are output as two-way, and one the tunnel carries out 1/2 window length delay, and two paths of data is input to the windowing module respectively;

(2) windowing module is carried out the windowing operation for the data of input, and window function adopts broad sense hamming window, and window length is L, adopts the quantification of 8 bit data bit wides; After the windowing operation is finished, data input FFT module;

(3) use a degree of depth to store as the data that the RAM of L checks input in the FFT module, read data afterwards and be transported to FFT nuclear, carry out the FFT computing.FFT is set to Pipelined, and Streaming I/O pattern, operating frequency are f _In, f _InIdentical with the AD sampling clock, the output of its computing has real part Re and imaginary part Im two parts, merges into one road signal with these two parts with by the mould value R that the real part imaginary part calculates jointly according to senior middle school's low level among the present invention, i.e. { Re, Im, R} is transported to and disturbs identification and suppress module;

(4) each disturbs identification as follows with the course of work that suppresses module:

A. two-port RAM nuclear RAM1 and RAM2 that to set up two degree of depth be L=512, data input selected cell is selected RAM1 work, and the data of FFT output are with clock f _InStore among the RAM1, the L point that calculates mould value R in institute's deposit data simultaneously add up and

And threshold value

K is that thresholding is optimized coefficient;

B. after RAM1 was filled with, data input selected cell was selected RAM2 work, and the data of FFT output are deposited among the RAM2, and the L point that calculates the deposit data mould value R of institute simultaneously among the repeating step a adds up and SUM and threshold value TH ₁Work;

C. in the process of RAM2 data storages, to the data among the RAM1 with clock f _sRead f _s=N*f _In, N is iterations; Can get, can be to the data read among the RAM1 3 times in this following period of time of RAM2 data storages; A flag register that bit wide is identical with the RAM1 degree of depth is set, in to RAM1 first pass process of reading, will represents a part of R of mould value in the data that read _jWith TH ₁Compare, j=1, if 2,3...L is greater than TH ₁Then the corresponding position of flag register puts 1, i.e. flag[j-1]=1 (because the bit wide of flag is since 0, so need to use j-1 to represent the response position of flag), SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged; Read the moment that finishes at first pass, calculate thresholding TH by up-to-date SUM ₂, begin RAM1 is read for second time; With the data R that reads _jWith TH ₂Relatively, if R _jGreater than thresholding TH ₂, check whether the relevant position of flag is 1 this moment, if 1, then the flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts the relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jLess than thresholding TH ₂, then flag corresponding positions and SUM remain unchanged; Read the moment that finishes at second time, calculate thresholding TH according to up-to-date SUM value ₃, begin the 3rd time read; The 3rd time to N-1; All over reading the operation done and to read the operation of doing for second time identical, to the last read data one time, namely N can obtain threshold T H all over reading data by N-1 time read operation _N, if this moment is the data R that reads _jGreater than TH _N, then with the real part Re that reads _jBe set to TH _N, imaginary part Im _jBe set to 0 output, i.e. Re _j=TH _N, Im _j=; Otherwise with the real part Re that reads _jWith imaginary part Im _jData are in statu quo exported;

D. when the data decision of RAM1 finished, the data among the RAM2 were also stored end, and begin to store new data to the work of the data repeating step c among the RAM2 to RAM1 this moment;

(5) will disturb the data of identification and the output of inhibition module with clock f _sBe input to the IFFT module, in this module by two-port RAM storage and with clock f _InRead, finish the conversion of data rate.The data input IFFT nuclear that reads carries out inverse transformation and output;

(6) the direct addition of the output of two-way IFFT module is merged, flow to external interface, anti-interference end-of-job.

The invention has the beneficial effects as follows: the FPGA based on the anti-interference algorithm of iteration thresholding that the present invention proposes realizes, can adaptive setting interference detection threshold on algorithm, and have good dynamic disturbance and suppress ability.Realizing technical employing high-frequency clock realization reading data, judgement and inhibition, avoided to take hardware resource to the storage of middle process data because repeatedly adjudicating, taken full advantage of the technology that the FPGA time exchanges resource for, significantly reduced the consumption to hardware resource.

Description of drawings

Fig. 1 is based on the FPGA realization flow figure of the anti-interference algorithm of iteration thresholding;

Fig. 2 disturbs to suppress and the judging module flow chart;

Fig. 3 is frequency spectrum and the correlation schematic diagram that does not add the spread-spectrum signal when disturbing;

Fig. 4 is frequency spectrum and the correlation schematic diagram that adds the spread-spectrum signal after the interference;

Fig. 5 is thresholding iterative process Modelsim analogous diagram;

Fig. 6 is through the frequency spectrum of the spread-spectrum signal after anti-interference and correlation schematic diagram;

Fig. 7 is the RTL figure that FPGA realizes.

Embodiment

The present invention is further described below in conjunction with drawings and Examples.

The present invention proposes a kind of FPGA realization technology based on the anti-interference algorithm of iterative frequency-domain.In the algorithm of adaptive threshold is derived, make improvement, can reduce the consumption of storage resources greatly.In its nucleus module (disturb identification with suppress module), adopt ping-pong operation to receive data, prevent that data from overflowing processing, and use high-frequency clock to finish RAM data read and follow-up thresholding iterative computation and interference decision operation.

(I) first moment iteration threshold algorithm is theoretical derives:

Signal can be expressed as S (k)+N (k) under glitch-free condition, and wherein S (k) represents useful signal, and N (k) represents noise signal.Through becoming S (n)+N (n) after the N point DFT conversion, it is a narrowband Gaussian signal.The envelope of S (n)+N (n) | S (n)+N (n) | Rayleigh distributed, and envelope square | S (n)+N (n) | ²Obeys index distribution.A lot of documents all are that the probability distribution from envelope square begins to derive, and provide the iteration thresholding, and the present invention is from its envelope | S (n)+N (n) | distribution situation derive.

Suppose signal | S (n)+N (n) | obeying parameter is the rayleigh distributed of σ, and its desired value is

Probability density function is

Choose the first moment threshold value

Wherein thresholding is optimized COEFFICIENT K=1,2,3,4,5.Then | S (n)+N (n) | the probability of＜TH

$P\left(\right|S\left(n\right)+N\left(n\right)|<\mathrm{TH})={\&Integral;}_0^{\mathrm{TH}}\frac{\mathrm{xexp}\left(\frac{-x^2}{2{\mathrm{\&sigma;}}^2}\right)}{{\mathrm{\&sigma;}}^2}\mathrm{dx}=1-\exp \left(\frac{-x^2}{2{\mathrm{\&sigma;}}^2}\right){|}_{x=\mathrm{TH}}$

Can obtain the probability of different K values, as shown in the table:

The probability distribution situation of table 1 different K values

K=1	K=2	K=3	K=4	K=5
					0.5441	0.9568	0.9991	1.0000	1.0000

The present invention finally chooses K=4, can guarantee that useful signal can all pass through, and the parameter of Xuan Zeing is fit to the hardware realization simultaneously, and multiply operation only can realize with displacement.

When DFT counts more for a long time (N〉256) desired value

Can use the average statistical of signal to substitute, namely $\frac{1}{N}\underset{n=1}{\overset{n=N}{\mathrm{\&Sigma;}}}|S\left(n\right)+N\left(n\right)|=\mathrm{\&sigma;}\sqrt{\frac{\mathrm{\&pi;}}{2}},$ Thresholding is chosen work and is finished.

Adaptive threshold is by repeatedly calculating the average statistical of signal, with the threshold value of adaptively changing correspondence, makes signal pass through the judgement of iteration thresholding, reaches and disturbs the effect that suppresses.Concrete grammar can repeat no more here referring to following performing step.

(II) a kind of FPGA of the anti-interference algorithm based on the iteration thresholding realizes, principle as shown in Figure 1, characterization step is as follows:

(1) data that the AD sampling is obtained are divided into two-way, and one the tunnel carries out 1/2 window length delay (the present invention postpones 256 points), and two paths of data is input to the windowing module respectively.

(2) windowing module is carried out the windowing operation for the data of input, and window function adopts broad sense hamming window, and window length is 512 points, adopts the quantification of 8 bit data bit wides.After the windowing operation is finished, data input FFT module.

(3) use a degree of depth to be L(L=512 in the FFT module) the RAM data of checking input store, read data afterwards and be transported to FFT nuclear, carry out the FFT computing.FFT is set to flowing water type base 2 mode of operations, and operating frequency is f _In, the output of its computing has real part Re and imaginary part Im two parts, among the present invention this two paths of signals and Qi Mo value R is merged into one road signal according to senior middle school's low level, and namely { R} is transported to and disturbs identification and suppress module for Re, Im.

(4) disturbing identification is Key Implementation part of the present invention with suppressing module, its flow process as shown in Figure 2, detailed process is as follows:

A. setting up two degree of depth is for example L=512 of L() two-port RAM nuclear RAM1 and RAM2, data input selected cell is selected RAM1 work, the data of FFT output are with clock f _InStore among the RAM1, the L point that calculates mould value R in institute's deposit data simultaneously adds up and SUM and threshold value TH ₁

B. after RAM1 was filled with, data input cell was selected RAM2 work, and the data of FFT output are deposited among the RAM2, and the L point that calculates the deposit data mould value R of institute simultaneously in the repeating step 1 adds up and SUM and threshold value TH ₁Work.

C. in the process of RAM2 data storages, to the data among the RAM1 with clock f _sRead.f _sCan determine that for example iterations is 3 times, then f according to required iterations _s=3*f _InCan get, can be to the data read among the RAM1 3 times in this following period of time of RAM2 data storages.A bit wide and RAM1(RAM2 are set) flag register (for example [511:0] flag) that the degree of depth is identical, in to RAM1 first pass process of reading, will represent a part of R of mould value in the data that read _j(j=0,1 ... 511) and TH ₁Compare, if greater than TH ₁Then the corresponding position of flag register puts 1, i.e. flag[j]=1, SUM=SUM-(R _j-TH ₁).Otherwise flag[j]=0, SUM remains unchanged.Read the moment that finishes at first pass, calculate thresholding TH by up-to-date SUM ₂, begin RAM1 is read for second time.With the data R that reads _jWith TH ₂Relatively, if R _jGreater than thresholding TH ₂, check whether the relevant position of flag is 1 this moment, if 1, then the flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts the relevant position 1, SUM=SUM-(R _j-TH ₂).If R _jLess than thresholding TH ₂, then flag corresponding positions and SUM remain unchanged.Read the moment that finishes at second time, calculate thresholding TH according to up-to-date SUM value ₃, begin the 3rd time read.If the data R that reads _jGreater than TH ₃, then with the real part Re that reads _jBe set to TH ₃, imaginary part Im _jBe set to 0 output, i.e. Re _j=TH ₃, Im _j=0; Otherwise with the real part Re that reads _jWith imaginary part Im _jData are in statu quo exported.

D. when the data decision of RAM1 finished, the data among the RAM2 were also stored end, and begin to store new data to the work of the data repeating step 3 among the RAM2 to RAM1 this moment.

(5) will disturb the data of identification and the output of inhibition module with clock f _sBe input to the IFFT module, in this module by two-port RAM storage and with clock f _InRead, finish the conversion of data rate.The data input IFFT nuclear that reads carries out inverse transformation and output.

(6) output of two-way IFFT module is merged flow to external interface, anti-interference end-of-job.

Now in conjunction with certain actual wireless band spread receiver the present invention is described further:

The hardware platform that algorithm is realized: the fpga chip of Xilinx x5v1x155 model.

Exploitation and simulated environment: ISE10.1 and Modelsim SE6.5c.

The spread-spectrum signal bandwidth of using is 2MHz, and interference signal is 0.2MHz, and jamming-to-signal ratio is 45dB.

The global clock of receiver system is 32MHz and 96MHz.Specific implementation adopts three iteration.The data bit width of AD input is 4.The IP kernel that carries out FFT and IFFT computing all adopts fixedly bit wide (scaled) pattern, and namely importing bit wide is 8, and the real part of output and imaginary part bit wide are 8.RAM nuclear in the realization all adopts 512 storage depth, and wherein RAM nuclear bit wide is 4 in the FFT module; Disturb to suppress and judging module in the RAM bit wide be 25, the real part data of most-significant byte storage FFT output, in the imaginary data of 8 storage FFT output, store the mould values for low 9; RAM nuclear bit wide in the IFFT module is 20, high 12 storage real part data, least-significant byte storage imaginary data.

The concrete steps that realize are as follows:

(1) data that will obtain the satellite-signal AD sampling that changes to intermediate frequency down are output as two-way, and one the tunnel carries out 1/2 window length delay (the present invention postpones 256 points), and two paths of data is input to the windowing module respectively.

(2) windowing module is carried out the windowing operation for the data of input, and window function adopts broad sense hamming window, and window length is 512 points, adopts the quantification of 8 bit data bit wides.After the windowing operation is finished, data input FFT module.

(3) using a degree of depth in the FFT module is that the data that 512 RAM checks input are stored, and reads data afterwards and is transported to FFT nuclear, carries out the FFT computing.FFT is set to Pipelined, and Streaming I/O pattern, its operating frequency are f _In=32MHz(f _InIdentical with the AD sampling clock), the output of its computing has real part Re and imaginary part Im two parts, among the present invention with these two parts and the mould value that calculated jointly by the real part imaginary part

Merge into one road signal according to senior middle school's low level, namely { R} is transported to and disturbs identification and suppress module for Re, Im.

(4) each disturbs identification as follows with the course of work that suppresses module:

A. set up two degree of depth and be 512 two-port RAM nuclear RAM1 and RAM2, data input selected cell is selected RAM1 work, and the data of FFT output are with clock f _In=32MHz stores among the RAM1, calculate simultaneously that 512 of mould value R in institute's deposit data add up and $\mathrm{SUM}(\mathrm{SUM}=\underset{j=1}{\overset{512}{\mathrm{\&Sigma;}}}{R}_j)$ And threshold value ${\mathrm{TH}}_1({\mathrm{<figure-callout\; id="1"\; label="TH"\; filenames="HDA00002902863600013.png,HDA00002902863600014.png"\; state="\{\{state\}\}">TH</figure-callout>}}_1=4*\frac{\mathrm{SUM}}{512}).$

B. after RAM1 was filled with, data input selected cell was selected RAM2 work, and the data of FFT output are deposited among the RAM2, and 512 that calculate the deposit data mould value R of institute simultaneously among the repeating step a are added up and SUM and threshold value TH ₁Work.

C. in the process of RAM2 data storages, to the data among the RAM1 with clock f _s=3*32=96MHz reads.A bit wide is set is 512 flag register, in to RAM1 first pass process of reading, will represent a part of R of mould value in the data that read _j, j=1,2,3...512 is with TH ₁Compare, if greater than TH ₁Then the corresponding position of flag register puts 1, i.e. flag[j-1]=1 (because the bit wide of flag is since 0, so need to use j-1 to represent the relevant position of flag bit wide), SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged.Read the moment that finishes at first pass, calculate thresholding TH by up-to-date SUM ₂(computing formula is shown in step a) begins RAM1 is read for second time.With the data R that reads _jWith TH ₂Relatively, if R _jGreater than thresholding TH ₂, check whether the relevant position of flag is 1 this moment, if 1, then the flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts the relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jLess than thresholding TH ₂, then flag corresponding positions and SUM remain unchanged.Read the moment that finishes at second time, calculate thresholding TH according to up-to-date SUM value ₃, begin the 3rd time read.If this moment is the data R that reads _jGreater than TH ₃, then with the real part Re that reads _jBe set to TH ₃, imaginary part Im _jBe set to 0 output, i.e. Re _j=TH ₃, Im _j=0; Otherwise with the real part Re that reads _jWith imaginary part Im _jData are in statu quo exported

D. when the data decision of RAM1 finished, the data among the RAM2 were also stored end, and begin to store new data to the work of the data repeating step c among the RAM2 to RAM1 this moment.

(5) data of the inhibition that will disturb and judging module output are with clock f _s=96MHz is input to the IFFT module, in this module by two-port RAM storage and with clock f _In=32MHz reduction of speed rate reads, and finishes the conversion of data rate.The data input IFFT nuclear that reads carries out inverse transformation and output.

(6) the direct addition of the output of two-way IFFT module is merged, flow to external interface, anti-interference end-of-job.

According to the characteristic of spread-spectrum signal, can judge the degree that interference signal is suppressed by the correlation peak of spread-spectrum signal and local code signal.

The frequency spectrum of the spread-spectrum signal when not adding interference and correlation are as shown in Figure 3.

Add the frequency spectrum of spread-spectrum signal after the interference signal that bandwidth 2MHz jamming-to-signal ratio is 40dB and correlation as shown in Figure 4.

The Modelsim analogous diagram of thresholding iterative process as shown in Figure 5 when FPGA realized.

Threshold1 in the signal shown in Figure 5, threshold2, the respectively corresponding iteration of the threshold3 first time, the second time and threshold value for the third time.

From overall procedure, after every judgement through 512 point data, each threshold value (as threshold1) can obtain upgrading according to the statistics of the data of new input, and namely threshold value can be according to according to the difference of input data and dynamic change.Once complete judging process from 512 point data, through declaring for the first time iteration, threshold value drops to threshold2 by threshold1, through the iteration second time, threshold value drops to threshold3 by threshold2, in the process of iteration for the third time, with data decision output, finish the interference judgement work of 512 point data.Specific implementation conforms to theory.

After the interference that signal is realized by FPGA suppressed module, the frequency spectrum of spread-spectrum signal and correlation were as shown in Figure 6.

According to Fig. 4, Fig. 5 and result shown in Figure 6, can not get tangible correlation peak after adding interference signal as can be seen, receiver can't be worked.Through after disturb suppressing, correlation peak is apparent in view, and the position is with not add interference signal identical, and interference suppresses successfully.

After the comprehensive and placement-and-routing, the RTL that FPGA realizes schemes as shown in Figure 7 through ISE.

Shown in the concrete resource consumption information slip 2.

Table 2 resource consumption figure

Claims (1)

1. the FPGA implementation method of the anti-interference algorithm of iterative frequency-domain is characterized in that comprising the steps:

(1) will carry out the AD sampling to the satellite-signal that changes to intermediate frequency down, the data that obtain are output as two-way, and one the tunnel carries out 1/2 window length delay, and two paths of data is input to the windowing module respectively;

(2) windowing module is carried out the windowing operation for the data of input, and window function adopts broad sense hamming window, and window length is L, adopts the quantification of 8 bit data bit wides; After the windowing operation is finished, data input FFT module;

(3) use a degree of depth to store as the data that the RAM of L checks input in the FFT module, read data afterwards and be transported to FFT nuclear, carry out the FFT computing; FFT is set to Pipelined, and Streaming I/O pattern, operating frequency are f _In, f _InIdentical with the AD sampling clock, the output of its computing has real part Re and imaginary part Im two parts, merges into one road signal with these two parts with by the mould value R that the real part imaginary part calculates jointly according to senior middle school's low level among the present invention, i.e. { Re, Im, R} is transported to and disturbs identification and suppress module;

(4) each disturbs identification as follows with the course of work that suppresses module:

A. two-port RAM nuclear RAM1 and RAM2 that to set up two degree of depth be L=512, data input selected cell is selected RAM1 work, and the data of FFT output are with clock f _InStore among the RAM1, the L point that calculates mould value R in institute's deposit data simultaneously add up and

And threshold value

K is that thresholding is optimized coefficient;

B. after RAM1 was filled with, data input selected cell was selected RAM2 work, and the data of FFT output are deposited among the RAM2, and the L point that calculates the deposit data mould value R of institute simultaneously among the repeating step a adds up and SUM and threshold value TH ₁Work;

C. in the process of RAM2 data storages, to the data among the RAM1 with clock f _sRead f _s=N*f _In, N is iterations; Can get, can be to the data read among the RAM1 3 times in this following period of time of RAM2 data storages; A flag register that bit wide is identical with the RAM1 degree of depth is set, in to RAM1 first pass process of reading, will represents a part of R of mould value in the data that read _jWith TH ₁Compare, j=1, if 2,3...L is greater than TH ₁Then the corresponding position of flag register puts 1, i.e. flag[j-1]=1, SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged; Read the moment that finishes at first pass, calculate thresholding TH by up-to-date SUM ₂, begin RAM1 is read for second time; With the data R that reads _jWith TH ₂Relatively, if R _jGreater than thresholding TH ₂, check whether the relevant position of flag is 1 this moment, if 1, then the flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts the relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jLess than thresholding TH ₂, then flag corresponding positions and SUM remain unchanged; Read the moment that finishes at second time, calculate thresholding TH according to up-to-date SUM value ₃, begin the 3rd time read; The 3rd time to N-1; All over reading the operation done and to read the operation of doing for second time identical, to the last read data one time, namely N can obtain threshold T H all over reading data by N-1 time read operation _N, if this moment is the data R that reads _jGreater than TH _N, then with the real part Re that reads _jBe set to TH _N, imaginary part Im _jBe set to 0 output, i.e. Re _j=TH _N, Im _j=0; Otherwise with the real part Re that reads _jWith imaginary part Im _jData are in statu quo exported;

D. when the data decision of RAM1 finished, the data among the RAM2 were also stored end, and begin to store new data to the work of the data repeating step c among the RAM2 to RAM1 this moment;

(5) will disturb the data of identification and the output of inhibition module with clock f _sBe input to the IFFT module, in this module by two-port RAM storage and with clock f _InRead, finish the conversion of data rate; The data input IFFT nuclear that reads carries out inverse transformation and output;

(6) the direct addition of the output of two-way IFFT module is merged, flow to external interface, anti-interference end-of-job.

Images